[llvm] f47c406 - [PhaseOrder] Add test where indvars dropping NSW prevents vectorization.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2024-01-23T11:37:04Z
New Revision: f47c4067fd30ef4318f6ff4d4afafd1ef8a2e262

URL: https://github.com/llvm/llvm-project/commit/f47c4067fd30ef4318f6ff4d4afafd1ef8a2e262
DIFF: https://github.com/llvm/llvm-project/commit/f47c4067fd30ef4318f6ff4d4afafd1ef8a2e262.diff

LOG: [PhaseOrder] Add test where indvars dropping NSW prevents vectorization.

End-to-end test for https://github.com/llvm/llvm-project/issues/71517,
testing IndVars/LoopVectorize interaction

Added: 
    llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll
new file mode 100644
index 00000000000000..a7e8e15804117c
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll
@@ -0,0 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -passes='default<O3>' -S -o - %s | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-macosx14.0.0"
+
+define void @s172(i32 noundef %xa, i32 noundef %xb, ptr noundef %a, ptr noundef %b) {
+; CHECK-LABEL: define void @s172(
+; CHECK-SAME: i32 noundef [[XA:%.*]], i32 noundef [[XB:%.*]], ptr nocapture noundef [[A:%.*]], ptr nocapture noundef readonly [[B:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[XA]], 32001
+; CHECK-NEXT:    br i1 [[CMP1]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]]
+; CHECK:       for.body.preheader:
+; CHECK-NEXT:    [[SUB:%.*]] = add i32 [[XA]], -1
+; CHECK-NEXT:    [[TMP0:%.*]] = sext i32 [[SUB]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = sext i32 [[XB]] to i64
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[TMP0]], [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT:    [[GEP_B:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDVARS_IV]]
+; CHECK-NEXT:    [[L_B:%.*]] = load i32, ptr [[GEP_B]], align 4
+; CHECK-NEXT:    [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV]]
+; CHECK-NEXT:    [[L_A:%.*]] = load i32, ptr [[GEP_A]], align 4
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[L_A]], [[L_B]]
+; CHECK-NEXT:    store i32 [[ADD]], ptr [[GEP_A]], align 4
+; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], [[TMP1]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT]], 32000
+; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK:       for.end:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %sub = sub nsw i32 %xa, 1
+  br label %for.cond
+
+for.cond:
+  %i.0 = phi i32 [ %sub, %entry ], [ %add3, %for.inc ]
+  %cmp = icmp slt i32 %i.0, 32000
+  br i1 %cmp, label %for.body, label %for.cond.cleanup
+
+for.body:
+  %idxprom = sext i32 %i.0 to i64
+  %gep.b = getelementptr inbounds i32, ptr %b, i64 %idxprom
+  %l.b = load i32, ptr %gep.b, align 4
+  %idxprom1 = sext i32 %i.0 to i64
+  %gep.a = getelementptr inbounds i32, ptr %a, i64 %idxprom1
+  %l.a = load i32, ptr %gep.a , align 4
+  %add = add nsw i32 %l.a, %l.b
+  store i32 %add, ptr %gep.a, align 4
+  br label %for.inc
+
+for.inc:
+  %add3 = add nsw i32 %i.0, %xb
+  br label %for.cond, !llvm.loop !0
+
+for.cond.cleanup:
+  br label %for.end
+
+for.end:
+  ret void
+}
+
+!0 = distinct !{!0, !1}
+!1 = !{!"llvm.loop.mustprogress"}
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.mustprogress"}
+;.