[llvm] [RISCV] Split tests for A into Zaamo and Zalrsc parts (PR #79111)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 23 00:51:21 PST 2024
https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/79111
So that we don't duplicate tests in later patch.
>From 6fe615335cad38dbcd8310956702d6bff70ae606 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Tue, 23 Jan 2024 16:51:10 +0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
.../{rv32a-invalid.s => rv32zaamo-invalid.s} | 7 ----
.../{rv32a-valid.s => rv32zaamo-valid.s} | 26 ------------
llvm/test/MC/RISCV/rv32zalrsc-invalid.s | 7 ++++
llvm/test/MC/RISCV/rv32zalrsc-valid.s | 36 ++++++++++++++++
.../{rv64a-invalid.s => rv64zaamo-invalid.s} | 4 --
.../{rv64a-valid.s => rv64zaamo-valid.s} | 34 ---------------
llvm/test/MC/RISCV/rv64zalrsc-invalid.s | 7 ++++
llvm/test/MC/RISCV/rv64zalrsc-valid.s | 42 +++++++++++++++++++
8 files changed, 92 insertions(+), 71 deletions(-)
rename llvm/test/MC/RISCV/{rv32a-invalid.s => rv32zaamo-invalid.s} (71%)
rename llvm/test/MC/RISCV/{rv32a-valid.s => rv32zaamo-valid.s} (85%)
create mode 100644 llvm/test/MC/RISCV/rv32zalrsc-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zalrsc-valid.s
rename llvm/test/MC/RISCV/{rv64a-invalid.s => rv64zaamo-invalid.s} (78%)
rename llvm/test/MC/RISCV/{rv64a-valid.s => rv64zaamo-valid.s} (83%)
create mode 100644 llvm/test/MC/RISCV/rv64zalrsc-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zalrsc-valid.s
diff --git a/llvm/test/MC/RISCV/rv32a-invalid.s b/llvm/test/MC/RISCV/rv32zaamo-invalid.s
similarity index 71%
rename from llvm/test/MC/RISCV/rv32a-invalid.s
rename to llvm/test/MC/RISCV/rv32zaamo-invalid.s
index 34d51fc30ca210e..f6183fbc8a1f135 100644
--- a/llvm/test/MC/RISCV/rv32a-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zaamo-invalid.s
@@ -4,15 +4,8 @@
amoswap.w a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
amomin.w a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
amomin.w a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
-lr.w a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
# Only .aq, .rl, and .aqrl suffixes are valid
amoxor.w.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
amoor.w.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
amoor.w. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
-
-# lr only takes two operands
-lr.w s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
-
-# Note: errors for use of RV64A instructions for RV32 are checked in
-# rv64a-valid.s
diff --git a/llvm/test/MC/RISCV/rv32a-valid.s b/llvm/test/MC/RISCV/rv32zaamo-valid.s
similarity index 85%
rename from llvm/test/MC/RISCV/rv32a-valid.s
rename to llvm/test/MC/RISCV/rv32zaamo-valid.s
index 1f66680c27114f2..ea1ae79558443ef 100644
--- a/llvm/test/MC/RISCV/rv32a-valid.s
+++ b/llvm/test/MC/RISCV/rv32zaamo-valid.s
@@ -9,32 +9,6 @@
# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# CHECK-ASM-AND-OBJ: lr.w t0, (t1)
-# CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10]
-lr.w t0, (t1)
-# CHECK-ASM-AND-OBJ: lr.w.aq t1, (t2)
-# CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14]
-lr.w.aq t1, (t2)
-# CHECK-ASM-AND-OBJ: lr.w.rl t2, (t3)
-# CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12]
-lr.w.rl t2, (t3)
-# CHECK-ASM-AND-OBJ: lr.w.aqrl t3, (t4)
-# CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16]
-lr.w.aqrl t3, (t4)
-
-# CHECK-ASM-AND-OBJ: sc.w t6, t5, (t4)
-# CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19]
-sc.w t6, t5, (t4)
-# CHECK-ASM-AND-OBJ: sc.w.aq t5, t4, (t3)
-# CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d]
-sc.w.aq t5, t4, (t3)
-# CHECK-ASM-AND-OBJ: sc.w.rl t4, t3, (t2)
-# CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b]
-sc.w.rl t4, t3, (t2)
-# CHECK-ASM-AND-OBJ: sc.w.aqrl t3, t2, (t1)
-# CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e]
-sc.w.aqrl t3, t2, (t1)
-
# CHECK-ASM-AND-OBJ: amoswap.w a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x08]
amoswap.w a4, ra, (s0)
diff --git a/llvm/test/MC/RISCV/rv32zalrsc-invalid.s b/llvm/test/MC/RISCV/rv32zalrsc-invalid.s
new file mode 100644
index 000000000000000..61cfc614b7c4206
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zalrsc-invalid.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 | FileCheck %s
+
+# Final operand must have parentheses
+lr.w a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
+
+# lr only takes two operands
+lr.w s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv32zalrsc-valid.s b/llvm/test/MC/RISCV/rv32zalrsc-valid.s
new file mode 100644
index 000000000000000..0d4881a4b45a7b0
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zalrsc-valid.s
@@ -0,0 +1,36 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+a -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a < %s \
+# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
+# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: lr.w t0, (t1)
+# CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10]
+lr.w t0, (t1)
+# CHECK-ASM-AND-OBJ: lr.w.aq t1, (t2)
+# CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14]
+lr.w.aq t1, (t2)
+# CHECK-ASM-AND-OBJ: lr.w.rl t2, (t3)
+# CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12]
+lr.w.rl t2, (t3)
+# CHECK-ASM-AND-OBJ: lr.w.aqrl t3, (t4)
+# CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16]
+lr.w.aqrl t3, (t4)
+
+# CHECK-ASM-AND-OBJ: sc.w t6, t5, (t4)
+# CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19]
+sc.w t6, t5, (t4)
+# CHECK-ASM-AND-OBJ: sc.w.aq t5, t4, (t3)
+# CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d]
+sc.w.aq t5, t4, (t3)
+# CHECK-ASM-AND-OBJ: sc.w.rl t4, t3, (t2)
+# CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b]
+sc.w.rl t4, t3, (t2)
+# CHECK-ASM-AND-OBJ: sc.w.aqrl t3, t2, (t1)
+# CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e]
+sc.w.aqrl t3, t2, (t1)
diff --git a/llvm/test/MC/RISCV/rv64a-invalid.s b/llvm/test/MC/RISCV/rv64zaamo-invalid.s
similarity index 78%
rename from llvm/test/MC/RISCV/rv64a-invalid.s
rename to llvm/test/MC/RISCV/rv64zaamo-invalid.s
index 2816f434e470663..70a4e557755baa5 100644
--- a/llvm/test/MC/RISCV/rv64a-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zaamo-invalid.s
@@ -4,12 +4,8 @@
amoswap.d a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
amomin.d a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
amomin.d a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
-lr.d a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
# Only .aq, .rl, and .aqrl suffixes are valid
amoxor.d.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
amoor.d.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
amoor.d. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
-
-# lr only takes two operands
-lr.d s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64a-valid.s b/llvm/test/MC/RISCV/rv64zaamo-valid.s
similarity index 83%
rename from llvm/test/MC/RISCV/rv64a-valid.s
rename to llvm/test/MC/RISCV/rv64zaamo-valid.s
index 3276b397f7194ca..73cdc55584341c5 100644
--- a/llvm/test/MC/RISCV/rv64a-valid.s
+++ b/llvm/test/MC/RISCV/rv64zaamo-valid.s
@@ -7,40 +7,6 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
-# CHECK-ASM-AND-OBJ: lr.d t0, (t1)
-# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-lr.d t0, (t1)
-# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
-# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-lr.d.aq t1, (t2)
-# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
-# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-lr.d.rl t2, (t3)
-# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
-# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-lr.d.aqrl t3, (t4)
-
-# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
-# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-sc.d t6, t5, (t4)
-# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
-# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-sc.d.aq t5, t4, (t3)
-# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
-# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-sc.d.rl t4, t3, (t2)
-# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
-# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-sc.d.aqrl t3, t2, (t1)
-
# CHECK-ASM-AND-OBJ: amoswap.d a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
diff --git a/llvm/test/MC/RISCV/rv64zalrsc-invalid.s b/llvm/test/MC/RISCV/rv64zalrsc-invalid.s
new file mode 100644
index 000000000000000..0be009725ed82ac
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zalrsc-invalid.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+a < %s 2>&1 | FileCheck %s
+
+# Final operand must have parentheses
+lr.d a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
+
+# lr only takes two operands
+lr.d s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64zalrsc-valid.s b/llvm/test/MC/RISCV/rv64zalrsc-valid.s
new file mode 100644
index 000000000000000..d4c87523b71c1e2
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zalrsc-valid.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
+# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
+# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
+
+# CHECK-ASM-AND-OBJ: lr.d t0, (t1)
+# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d t0, (t1)
+# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
+# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d.aq t1, (t2)
+# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
+# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d.rl t2, (t3)
+# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
+# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d.aqrl t3, (t4)
+
+# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
+# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d t6, t5, (t4)
+# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
+# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d.aq t5, t4, (t3)
+# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
+# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d.rl t4, t3, (t2)
+# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
+# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d.aqrl t3, t2, (t1)
More information about the llvm-commits
mailing list