[llvm] [RISCV] DAG combine special for AND/OR immediately (PR #79101)

[Liao Chunyu via llvm-commits]

https://github.com/ChunyuLiao created https://github.com/llvm/llvm-project/pull/79101

Combine:
RISCVISD::VMAND_VL x, 0/1, y -> 0/x
RISCVISD::VMXOR_VL x, 0/1, y -> x/1

td:
riscv_vmor_vl + riscv_vmand_vl + riscv_vmnot_vl,
better to select
    vmorn.mm        v0, v8, v0
instead of
    vmand.mm        v8, v8, v0
    vmorn.mm        v0, v8, v0

>From 7a0b85bd6de60a00b331b259db2df326ee6430e3 Mon Sep 17 00:00:00 2001
From: Liao Chunyu <chunyu at iscas.ac.cn>
Date: Tue, 23 Jan 2024 14:27:57 +0800
Subject: [PATCH] [RISCV] DAG combine special for AND/OR immediately

Combine:
RISCVISD::VMAND_VL x, 0/1, y -> 0/x
RISCVISD::VMXOR_VL x, 0/1, y -> x/1

td:
riscv_vmor_vl + riscv_vmand_vl + riscv_vmnot_vl,
better to select
    vmorn.mm        v0, v8, v0
instead of
    vmand.mm        v8, v8, v0
    vmorn.mm        v0, v8, v0
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   | 26 +++++++++++++++++++
 .../Target/RISCV/RISCVInstrInfoVVLPatterns.td |  5 ++++
 llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll     | 20 ++++++++++++++
 3 files changed, 51 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 76e8d21b818b259..cd8ced502e8bf3b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -15621,6 +15621,32 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
     }
     break;
   }
+  case RISCVISD::VMAND_VL: {
+    SDValue N0 = N->getOperand(0);
+    SDValue N1 = N->getOperand(1);
+    if (isNullOrNullSplat(N0))
+      return N0;
+    else if (isNullOrNullSplat(N1))
+      return N1;
+    else if (isOneOrOneSplat(N0))
+      return N1;
+    else if (isOneOrOneSplat(N1))
+      return N0;
+    break;
+  }
+  case RISCVISD::VMOR_VL: {
+    SDValue N0 = N->getOperand(0);
+    SDValue N1 = N->getOperand(1);
+    if (isNullOrNullSplat(N1))
+      return N0;
+    else if (isNullOrNullSplat(N0))
+      return N1;
+    else if (isOneOrOneSplat(N0))
+      return N0;
+    else if (isOneOrOneSplat(N1))
+      return N1;
+    break;
+  }
   case ISD::SRA:
     if (SDValue V = performSRACombine(N, DAG, Subtarget))
       return V;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 6e7be2647e8f838..1f0a7d2e4fd752e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -2736,6 +2736,11 @@ foreach mti = AllMasks in {
                                         VLOpFrag)),
               (!cast<Instruction>("PseudoVMANDN_MM_" # mti.LMul.MX)
                    VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
+    def : Pat<(mti.Mask (riscv_vmor_vl (riscv_vmand_vl VR:$rs1, VR:$rs2, VLOpFrag),
+                                       (riscv_vmnot_vl VR:$rs2, VLOpFrag),
+                                       VLOpFrag)),
+              (!cast<Instruction>("PseudoVMORN_MM_" # mti.LMul.MX)
+                   VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
     def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1,
                                        (riscv_vmnot_vl VR:$rs2, VLOpFrag),
                                        VLOpFrag)),
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
index 9e7df5eab8dda98..72749368cc07e28 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
@@ -745,3 +745,23 @@ define <vscale x 16 x double> @select_nxv16f64(<vscale x 16 x i1> %a, <vscale x
   %v = call <vscale x 16 x double> @llvm.vp.select.nxv16f64(<vscale x 16 x i1> %a, <vscale x 16 x double> %b, <vscale x 16 x double> %c, i32 %evl)
   ret <vscale x 16 x double> %v
 }
+
+define <vscale x 2 x i1> @select_zero(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: select_zero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT:    vmand.mm v0, v8, v0
+; CHECK-NEXT:    ret
+  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> zeroinitializer, i32 %evl)
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @select_one(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: select_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT:    vmorn.mm v0, v8, v0
+; CHECK-NEXT:    ret
+  %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer), i32 %evl)
+  ret <vscale x 2 x i1> %a
+}