[llvm] [RISCV] Make X5 allocatable for JALR on CPUs without RAS (PR #78417)

[Craig Topper via llvm-commits]

topperc wrote:

> > Do you have any performance or code size data to show that this change is a benefit to CPUs with RAS?
> 
> I don't have performance data as I don't have such hardware implementation. And I don't see code size change on llvm-test-suite. The thought of this PR came from a random discussion with my colleague, and ARM supports such feature. So I think maybe some low-end products need it.

It doesn't look like ARM uses it for register allocation though. This is the only code I can find on ARM that uses it

```
    if (!isDirect && !Subtarget->hasV5TOps())                                    
      CallOpc = ARMISD::CALL_NOLINK;                                             
    else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&           
             // Emit regular call when code size is the priority                 
             !Subtarget->hasMinSize())                                           
      // "mov lr, pc; b _foo" to avoid confusing the RSP                         
      CallOpc = ARMISD::CALL_NOLINK;                                             
    else                                                                         
      CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
```

https://github.com/llvm/llvm-project/pull/78417