[llvm] [RISCV] Make X5 allocatable for JALR on CPUs without RAS (PR #78417)

[Wang Pengcheng via llvm-commits]

wangpc-pp wrote:

> Do you have any performance or code size data to show that this change is a benefit to CPUs with RAS?

I don't have performance data as I don't have such hardware implementation. And I don't see code size change on llvm-test-suite.
The thought of this PR came from a random discussion with my colleague, and ARM supports such feature. So I think maybe some low-end products need it.

https://github.com/llvm/llvm-project/pull/78417