[llvm] 376f019 - [AMDGPU][NFC] Update cache policy descriptions (#78768)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 22 00:35:12 PST 2024
Author: Mirko Brkušanin
Date: 2024-01-22T09:35:08+01:00
New Revision: 376f019609b3eba578723c26e1635d1be31e6057
URL: https://github.com/llvm/llvm-project/commit/376f019609b3eba578723c26e1635d1be31e6057
DIFF: https://github.com/llvm/llvm-project/commit/376f019609b3eba578723c26e1635d1be31e6057.diff
LOG: [AMDGPU][NFC] Update cache policy descriptions (#78768)
Added:
Modified:
llvm/include/llvm/IR/IntrinsicsAMDGPU.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 21765cdd13a153..e6db9da5526aa3 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -860,7 +860,6 @@ class AMDGPUImageDimIntrinsic<AMDGPUDimProfile P_,
[llvm_i32_ty, // texfailctrl(imm; bit 0 = tfe, bit 1 = lwe)
llvm_i32_ty]), // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc;
// gfx12+ imm: bits [0-2] = th, bits [3-4] = scope)
- // TODO-GFX12: Update all other cachepolicy descriptions.
!listconcat(props, [IntrNoCallback, IntrNoFree, IntrWillReturn],
!if(P_.IsAtomic, [], [ImmArg<ArgIndex<AMDGPUImageDimIntrinsicEval<P_>.DmaskArgIndex>>]),
@@ -1088,7 +1087,8 @@ def int_amdgcn_s_buffer_load : DefaultAttrsIntrinsic <
[llvm_any_ty],
[llvm_v4i32_ty, // rsrc(SGPR)
llvm_i32_ty, // byte offset
- llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 2 = dlc)
+ llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc;
+ // gfx12+ imm: bits [0-2] = th, bits [3-4] = scope)
// Note: volatile bit is **not** permitted here.
[IntrNoMem, ImmArg<ArgIndex<2>>]>,
AMDGPURsrcIntrinsic<0>;
@@ -1128,8 +1128,13 @@ class AMDGPURawBufferLoad<LLVMType data_ty = llvm_any_ty> : DefaultAttrsIntrinsi
llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrReadMem, ImmArg<ArgIndex<3>>], "", [SDNPMemOperand]>,
AMDGPURsrcIntrinsic<0>;
@@ -1143,8 +1148,13 @@ class AMDGPURawPtrBufferLoad<LLVMType data_ty = llvm_any_ty> : DefaultAttrsIntri
llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrArgMemOnly, IntrReadMem, ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>,
@@ -1161,8 +1171,13 @@ class AMDGPUStructBufferLoad<LLVMType data_ty = llvm_any_ty> : DefaultAttrsIntri
llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrReadMem, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>,
AMDGPURsrcIntrinsic<0>;
@@ -1177,8 +1192,13 @@ class AMDGPUStructPtrBufferLoad<LLVMType data_ty = llvm_any_ty> : DefaultAttrsIn
llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrArgMemOnly, IntrReadMem, ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>,
ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>,
@@ -1194,8 +1214,13 @@ class AMDGPURawBufferStore<LLVMType data_ty = llvm_any_ty> : DefaultAttrsIntrins
llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrWriteMem, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>,
AMDGPURsrcIntrinsic<1>;
@@ -1210,8 +1235,13 @@ class AMDGPURawPtrBufferStore<LLVMType data_ty = llvm_any_ty> : DefaultAttrsIntr
llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrArgMemOnly, IntrWriteMem, WriteOnly<ArgIndex<1>>, NoCapture<ArgIndex<1>>,
ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>,
@@ -1228,8 +1258,13 @@ class AMDGPUStructBufferStore<LLVMType data_ty = llvm_any_ty> : DefaultAttrsIntr
llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrWriteMem, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>,
AMDGPURsrcIntrinsic<1>;
@@ -1245,8 +1280,13 @@ class AMDGPUStructPtrBufferStore<LLVMType data_ty = llvm_any_ty> : DefaultAttrsI
llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrArgMemOnly, IntrWriteMem, WriteOnly<ArgIndex<1>>, NoCapture<ArgIndex<1>>,
ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>,
@@ -1502,8 +1542,12 @@ def int_amdgcn_raw_tbuffer_load : DefaultAttrsIntrinsic <
llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz))
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz)
[IntrReadMem,
ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>,
AMDGPURsrcIntrinsic<0>;
@@ -1516,8 +1560,12 @@ def int_amdgcn_raw_ptr_tbuffer_load : DefaultAttrsIntrinsic <
llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz)
// volatile op (bit 31, stripped at lowering))
[IntrArgMemOnly, IntrReadMem, ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>,
ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>,
@@ -1532,8 +1580,13 @@ def int_amdgcn_raw_tbuffer_store : DefaultAttrsIntrinsic <
llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrWriteMem,
ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>,
@@ -1548,8 +1601,13 @@ def int_amdgcn_raw_ptr_tbuffer_store : DefaultAttrsIntrinsic <
llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrArgMemOnly, IntrWriteMem, WriteOnly<ArgIndex<1>>, NoCapture<ArgIndex<1>>,
ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>,
@@ -1564,8 +1622,13 @@ def int_amdgcn_struct_tbuffer_load : DefaultAttrsIntrinsic <
llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrReadMem,
ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>,
@@ -1580,8 +1643,13 @@ def int_amdgcn_struct_ptr_tbuffer_load : DefaultAttrsIntrinsic <
llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrArgMemOnly, IntrReadMem, ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>,
ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>,
@@ -1597,9 +1665,14 @@ def int_amdgcn_struct_ptr_tbuffer_store : DefaultAttrsIntrinsic <
llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
- // volatile op (bit 31, stripped at lowering))
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
+ // volatile op (bit 31, stripped at lowering))
[IntrArgMemOnly, IntrWriteMem, WriteOnly<ArgIndex<1>>, NoCapture<ArgIndex<1>>,
ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>], "", [SDNPMemOperand]>,
AMDGPURsrcIntrinsic<1>;
@@ -1614,8 +1687,13 @@ def int_amdgcn_struct_tbuffer_store : DefaultAttrsIntrinsic <
llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+),
+ // bit 2 = dlc on gfx10/gfx11),
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrWriteMem,
ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>], "", [SDNPMemOperand]>,
@@ -1676,8 +1754,13 @@ class AMDGPURawBufferLoadLDS : Intrinsic <
llvm_i32_ty, // imm offset(imm, included in bounds checking and swizzling)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+))
+ // bit 2 = dlc on gfx10/gfx11))
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrWillReturn, NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>,
ImmArg<ArgIndex<6>>, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<0>;
@@ -1693,8 +1776,13 @@ class AMDGPURawPtrBufferLoadLDS : Intrinsic <
llvm_i32_ty, // imm offset(imm, included in bounds checking and swizzling)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+))
+ // bit 2 = dlc on gfx10/gfx11))
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrWillReturn, IntrArgMemOnly,
ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>,
@@ -1714,8 +1802,13 @@ class AMDGPUStructBufferLoadLDS : Intrinsic <
llvm_i32_ty, // imm offset(imm, included in bounds checking and swizzling)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+))
+ // bit 2 = dlc on gfx10/gfx11))
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrWillReturn, NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<6>>,
ImmArg<ArgIndex<7>>, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<0>;
@@ -1732,8 +1825,13 @@ class AMDGPUStructPtrBufferLoadLDS : Intrinsic <
llvm_i32_ty, // imm offset(imm, included in bounds checking and swizzling)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
// bit 1 = slc,
- // bit 2 = dlc on gfx10+))
+ // bit 2 = dlc on gfx10/gfx11))
// swizzled buffer (bit 3 = swz),
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
+ // all:
// volatile op (bit 31, stripped at lowering))
[IntrWillReturn, IntrArgMemOnly,
ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>,
@@ -2407,8 +2505,12 @@ class AMDGPUGlobalLoadLDS : Intrinsic <
llvm_i32_ty, // imm offset (applied to both global and LDS address)
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc/sc0,
// bit 1 = slc/sc1,
- // bit 2 = dlc on gfx10+))
+ // bit 2 = dlc on gfx10/gfx11))
// bit 4 = scc/nt on gfx90a+))
+ // gfx12+:
+ // cachepolicy (bits [0-2] = th,
+ // bits [3-4] = scope)
+ // swizzled buffer (bit 6 = swz),
[IntrWillReturn, NoCapture<ArgIndex<0>>, NoCapture<ArgIndex<1>>,
ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, IntrNoCallback, IntrNoFree],
"", [SDNPMemOperand]>;
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