[llvm] [X86] Support encoding/decoding and lowering for APX variant SHL/SHR/SAR/SHLD/SHRD (PR #78853)

[Phoebe Wang via llvm-commits]

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@@ -1821,47 +1844,77 @@ defm SAR : MaskedShiftAmountPats<sra>;
 // not tracking flags for these nodes.
 multiclass MaskedRotateAmountPats<SDNode frag> {
   // (rot x (and y, BitWidth - 1)) ==> (rot x, y)
-  def : Pat<(frag GR8:$src1, (shiftMask8 CL)),
-            (!cast<Instruction>(NAME # "8rCL") GR8:$src1)>;
-  def : Pat<(frag GR16:$src1, (shiftMask16 CL)),
-            (!cast<Instruction>(NAME # "16rCL") GR16:$src1)>;
-  def : Pat<(frag GR32:$src1, (shiftMask32 CL)),
-            (!cast<Instruction>(NAME # "32rCL") GR32:$src1)>;
+  // (rot x (and y, 63)) ==> (rot x, y)
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phoebewang wrote:

63 is included by `BitWidth - 1`.

https://github.com/llvm/llvm-project/pull/78853