[llvm] [AArch64][GlobalISel] Legalize Shifts for Smaller/Larger Vectors (PR #78750)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 19 09:52:19 PST 2024
https://github.com/chuongg3 created https://github.com/llvm/llvm-project/pull/78750
Legalize shl/lshr/ashr for smaller/larger vector widths with legal element sizes
Smaller than legal vector types does not work at the moment as it relies on G_ANYEXT to work with smaller than legal vector types
>From bdbb4d846c8f2c6ef291f6a624445a78f217510c Mon Sep 17 00:00:00 2001
From: Tuan Chuong Goh <chuong.goh at arm.com>
Date: Fri, 19 Jan 2024 16:49:56 +0000
Subject: [PATCH 1/2] [AArch64] Adding tests for shifts
---
llvm/test/CodeGen/AArch64/shift.ll | 1015 ++++++++++++++++++++++++++++
1 file changed, 1015 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/shift.ll
diff --git a/llvm/test/CodeGen/AArch64/shift.ll b/llvm/test/CodeGen/AArch64/shift.ll
new file mode 100644
index 00000000000000..55ff97563e1efe
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/shift.ll
@@ -0,0 +1,1015 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for shl_v4i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v32i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v2i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v16i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v4i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v32i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v2i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v16i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v4i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v32i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v2i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v16i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v3i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v7i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v3i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v7i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v3i32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v3i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v7i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v3i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v7i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v3i32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v3i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v7i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v3i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v7i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v3i32
+
+
+define i1 @shl_i1(i1 %0, i1 %1){
+; CHECK-SD-LABEL: shl_i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: and w0, w0, #0x1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shl_i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and w8, w1, #0x1
+; CHECK-GI-NEXT: lsl w8, w0, w8
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
+ %3 = shl i1 %0, %1
+ ret i1 %3
+}
+
+define i8 @shl_i8(i8 %0, i8 %1){
+; CHECK-SD-LABEL: shl_i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-SD-NEXT: lsl w0, w0, w1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shl_i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and w8, w1, #0xff
+; CHECK-GI-NEXT: lsl w0, w0, w8
+; CHECK-GI-NEXT: ret
+ %3 = shl i8 %0, %1
+ ret i8 %3
+}
+
+define i16 @shl_i16(i16 %0, i16 %1){
+; CHECK-SD-LABEL: shl_i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-SD-NEXT: lsl w0, w0, w1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shl_i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and w8, w1, #0xffff
+; CHECK-GI-NEXT: lsl w0, w0, w8
+; CHECK-GI-NEXT: ret
+ %3 = shl i16 %0, %1
+ ret i16 %3
+}
+
+define i32 @shl_i32(i32 %0, i32 %1){
+; CHECK-LABEL: shl_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsl w0, w0, w1
+; CHECK-NEXT: ret
+ %3 = shl i32 %0, %1
+ ret i32 %3
+}
+
+define i64 @shl_i64(i64 %0, i64 %1){
+; CHECK-LABEL: shl_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsl x0, x0, x1
+; CHECK-NEXT: ret
+ %3 = shl i64 %0, %1
+ ret i64 %3
+}
+
+define i128 @shl_i128(i128 %0, i128 %1){
+; CHECK-SD-LABEL: shl_i128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsr x8, x0, #1
+; CHECK-SD-NEXT: mvn w9, w2
+; CHECK-SD-NEXT: lsl x10, x1, x2
+; CHECK-SD-NEXT: tst x2, #0x40
+; CHECK-SD-NEXT: lsr x8, x8, x9
+; CHECK-SD-NEXT: lsl x9, x0, x2
+; CHECK-SD-NEXT: orr x8, x10, x8
+; CHECK-SD-NEXT: csel x0, xzr, x9, ne
+; CHECK-SD-NEXT: csel x1, x9, x8, ne
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shl_i128:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #64 // =0x40
+; CHECK-GI-NEXT: sub x9, x2, #64
+; CHECK-GI-NEXT: lsl x10, x1, x2
+; CHECK-GI-NEXT: sub x8, x8, x2
+; CHECK-GI-NEXT: lsl x11, x0, x2
+; CHECK-GI-NEXT: lsl x9, x0, x9
+; CHECK-GI-NEXT: lsr x8, x0, x8
+; CHECK-GI-NEXT: cmp x2, #64
+; CHECK-GI-NEXT: csel x0, x11, xzr, lo
+; CHECK-GI-NEXT: orr x8, x8, x10
+; CHECK-GI-NEXT: csel x8, x8, x9, lo
+; CHECK-GI-NEXT: cmp x2, #0
+; CHECK-GI-NEXT: csel x1, x1, x8, eq
+; CHECK-GI-NEXT: ret
+ %3 = shl i128 %0, %1
+ ret i128 %3
+}
+
+define i1 @ashr_i1(i1 %0, i1 %1){
+; CHECK-SD-LABEL: ashr_i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: and w0, w0, #0x1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ashr_i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sbfx w8, w0, #0, #1
+; CHECK-GI-NEXT: and w9, w1, #0x1
+; CHECK-GI-NEXT: asr w8, w8, w9
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
+ %3 = ashr i1 %0, %1
+ ret i1 %3
+}
+
+define i8 @ashr_i8(i8 %0, i8 %1){
+; CHECK-SD-LABEL: ashr_i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sxtb w8, w0
+; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-SD-NEXT: asr w0, w8, w1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ashr_i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sxtb w8, w0
+; CHECK-GI-NEXT: and w9, w1, #0xff
+; CHECK-GI-NEXT: asr w0, w8, w9
+; CHECK-GI-NEXT: ret
+ %3 = ashr i8 %0, %1
+ ret i8 %3
+}
+
+define i16 @ashr_i16(i16 %0, i16 %1){
+; CHECK-SD-LABEL: ashr_i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sxth w8, w0
+; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-SD-NEXT: asr w0, w8, w1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ashr_i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sxth w8, w0
+; CHECK-GI-NEXT: and w9, w1, #0xffff
+; CHECK-GI-NEXT: asr w0, w8, w9
+; CHECK-GI-NEXT: ret
+ %3 = ashr i16 %0, %1
+ ret i16 %3
+}
+
+define i32 @ashr_i32(i32 %0, i32 %1){
+; CHECK-LABEL: ashr_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: asr w0, w0, w1
+; CHECK-NEXT: ret
+ %3 = ashr i32 %0, %1
+ ret i32 %3
+}
+
+define i64 @ashr_i64(i64 %0, i64 %1){
+; CHECK-LABEL: ashr_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: asr x0, x0, x1
+; CHECK-NEXT: ret
+ %3 = ashr i64 %0, %1
+ ret i64 %3
+}
+
+define i128 @ashr_i128(i128 %0, i128 %1){
+; CHECK-SD-LABEL: ashr_i128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsl x8, x1, #1
+; CHECK-SD-NEXT: mvn w9, w2
+; CHECK-SD-NEXT: lsr x10, x0, x2
+; CHECK-SD-NEXT: asr x11, x1, #63
+; CHECK-SD-NEXT: tst x2, #0x40
+; CHECK-SD-NEXT: lsl x8, x8, x9
+; CHECK-SD-NEXT: asr x9, x1, x2
+; CHECK-SD-NEXT: orr x8, x8, x10
+; CHECK-SD-NEXT: csel x1, x11, x9, ne
+; CHECK-SD-NEXT: csel x0, x9, x8, ne
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ashr_i128:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #64 // =0x40
+; CHECK-GI-NEXT: sub x9, x2, #64
+; CHECK-GI-NEXT: lsr x10, x0, x2
+; CHECK-GI-NEXT: sub x8, x8, x2
+; CHECK-GI-NEXT: asr x9, x1, x9
+; CHECK-GI-NEXT: cmp x2, #64
+; CHECK-GI-NEXT: lsl x8, x1, x8
+; CHECK-GI-NEXT: asr x11, x1, x2
+; CHECK-GI-NEXT: orr x8, x10, x8
+; CHECK-GI-NEXT: asr x10, x1, #63
+; CHECK-GI-NEXT: csel x8, x8, x9, lo
+; CHECK-GI-NEXT: cmp x2, #0
+; CHECK-GI-NEXT: csel x0, x0, x8, eq
+; CHECK-GI-NEXT: cmp x2, #64
+; CHECK-GI-NEXT: csel x1, x11, x10, lo
+; CHECK-GI-NEXT: ret
+ %3 = ashr i128 %0, %1
+ ret i128 %3
+}
+
+define i1 @lshr_i1(i1 %0, i1 %1){
+; CHECK-SD-LABEL: lshr_i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: and w0, w0, #0x1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: lshr_i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and w8, w1, #0x1
+; CHECK-GI-NEXT: and w9, w0, #0x1
+; CHECK-GI-NEXT: lsr w0, w9, w8
+; CHECK-GI-NEXT: ret
+ %3 = lshr i1 %0, %1
+ ret i1 %3
+}
+
+define i8 @lshr_i8(i8 %0, i8 %1){
+; CHECK-SD-LABEL: lshr_i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: and w8, w0, #0xff
+; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-SD-NEXT: lsr w0, w8, w1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: lshr_i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and w8, w1, #0xff
+; CHECK-GI-NEXT: and w9, w0, #0xff
+; CHECK-GI-NEXT: lsr w0, w9, w8
+; CHECK-GI-NEXT: ret
+ %3 = lshr i8 %0, %1
+ ret i8 %3
+}
+
+define i16 @lshr_i16(i16 %0, i16 %1){
+; CHECK-SD-LABEL: lshr_i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: and w8, w0, #0xffff
+; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-SD-NEXT: lsr w0, w8, w1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: lshr_i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and w8, w1, #0xffff
+; CHECK-GI-NEXT: and w9, w0, #0xffff
+; CHECK-GI-NEXT: lsr w0, w9, w8
+; CHECK-GI-NEXT: ret
+ %3 = lshr i16 %0, %1
+ ret i16 %3
+}
+
+define i32 @lshr_i32(i32 %0, i32 %1){
+; CHECK-LABEL: lshr_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsr w0, w0, w1
+; CHECK-NEXT: ret
+ %3 = lshr i32 %0, %1
+ ret i32 %3
+}
+
+define i64 @lshr_i64(i64 %0, i64 %1){
+; CHECK-LABEL: lshr_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsr x0, x0, x1
+; CHECK-NEXT: ret
+ %3 = lshr i64 %0, %1
+ ret i64 %3
+}
+
+define i128 @lshr_i128(i128 %0, i128 %1){
+; CHECK-SD-LABEL: lshr_i128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsl x8, x1, #1
+; CHECK-SD-NEXT: mvn w9, w2
+; CHECK-SD-NEXT: lsr x10, x0, x2
+; CHECK-SD-NEXT: tst x2, #0x40
+; CHECK-SD-NEXT: lsl x8, x8, x9
+; CHECK-SD-NEXT: lsr x9, x1, x2
+; CHECK-SD-NEXT: orr x8, x8, x10
+; CHECK-SD-NEXT: csel x1, xzr, x9, ne
+; CHECK-SD-NEXT: csel x0, x9, x8, ne
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: lshr_i128:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #64 // =0x40
+; CHECK-GI-NEXT: sub x9, x2, #64
+; CHECK-GI-NEXT: lsr x10, x0, x2
+; CHECK-GI-NEXT: sub x8, x8, x2
+; CHECK-GI-NEXT: lsr x9, x1, x9
+; CHECK-GI-NEXT: cmp x2, #64
+; CHECK-GI-NEXT: lsl x8, x1, x8
+; CHECK-GI-NEXT: orr x8, x10, x8
+; CHECK-GI-NEXT: lsr x10, x1, x2
+; CHECK-GI-NEXT: csel x8, x8, x9, lo
+; CHECK-GI-NEXT: cmp x2, #0
+; CHECK-GI-NEXT: csel x0, x0, x8, eq
+; CHECK-GI-NEXT: cmp x2, #64
+; CHECK-GI-NEXT: csel x1, x10, xzr, lo
+; CHECK-GI-NEXT: ret
+ %3 = lshr i128 %0, %1
+ ret i128 %3
+}
+
+; ===== Legal Vector Type =====
+
+define <8 x i8> @shl_v8i8(<8 x i8> %0, <8 x i8> %1){
+; CHECK-LABEL: shl_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushl v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %3 = shl <8 x i8> %0, %1
+ ret <8 x i8> %3
+}
+
+define <16 x i8> @shl_v16i8(<16 x i8> %0, <16 x i8> %1){
+; CHECK-LABEL: shl_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushl v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %3 = shl <16 x i8> %0, %1
+ ret <16 x i8> %3
+}
+
+define <4 x i16> @shl_v4i16(<4 x i16> %0, <4 x i16> %1){
+; CHECK-LABEL: shl_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %3 = shl <4 x i16> %0, %1
+ ret <4 x i16> %3
+}
+
+define <8 x i16> @shl_v8i16(<8 x i16> %0, <8 x i16> %1){
+; CHECK-LABEL: shl_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushl v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %3 = shl <8 x i16> %0, %1
+ ret <8 x i16> %3
+}
+
+define <2 x i32> @shl_v2i32(<2 x i32> %0, <2 x i32> %1){
+; CHECK-LABEL: shl_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushl v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %3 = shl <2 x i32> %0, %1
+ ret <2 x i32> %3
+}
+
+define <4 x i32> @shl_v4i32(<4 x i32> %0, <4 x i32> %1){
+; CHECK-LABEL: shl_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %3 = shl <4 x i32> %0, %1
+ ret <4 x i32> %3
+}
+
+define <2 x i64> @shl_v2i64(<2 x i64> %0, <2 x i64> %1){
+; CHECK-LABEL: shl_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushl v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %3 = shl <2 x i64> %0, %1
+ ret <2 x i64> %3
+}
+
+define <8 x i8> @ashr_v8i8(<8 x i8> %0, <8 x i8> %1){
+; CHECK-LABEL: ashr_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.8b, v1.8b
+; CHECK-NEXT: sshl v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %3 = ashr <8 x i8> %0, %1
+ ret <8 x i8> %3
+}
+
+define <16 x i8> @ashr_v16i8(<16 x i8> %0, <16 x i8> %1){
+; CHECK-LABEL: ashr_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.16b, v1.16b
+; CHECK-NEXT: sshl v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %3 = ashr <16 x i8> %0, %1
+ ret <16 x i8> %3
+}
+
+define <4 x i16> @ashr_v4i16(<4 x i16> %0, <4 x i16> %1){
+; CHECK-LABEL: ashr_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4h, v1.4h
+; CHECK-NEXT: sshl v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %3 = ashr <4 x i16> %0, %1
+ ret <4 x i16> %3
+}
+
+define <8 x i16> @ashr_v8i16(<8 x i16> %0, <8 x i16> %1){
+; CHECK-LABEL: ashr_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.8h, v1.8h
+; CHECK-NEXT: sshl v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %3 = ashr <8 x i16> %0, %1
+ ret <8 x i16> %3
+}
+
+define <2 x i32> @ashr_v2i32(<2 x i32> %0, <2 x i32> %1){
+; CHECK-LABEL: ashr_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.2s, v1.2s
+; CHECK-NEXT: sshl v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %3 = ashr <2 x i32> %0, %1
+ ret <2 x i32> %3
+}
+
+define <4 x i32> @ashr_v4i32(<4 x i32> %0, <4 x i32> %1){
+; CHECK-LABEL: ashr_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4s, v1.4s
+; CHECK-NEXT: sshl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %3 = ashr <4 x i32> %0, %1
+ ret <4 x i32> %3
+}
+
+define <2 x i64> @ashr_v2i64(<2 x i64> %0, <2 x i64> %1){
+; CHECK-LABEL: ashr_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.2d, v1.2d
+; CHECK-NEXT: sshl v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %3 = ashr <2 x i64> %0, %1
+ ret <2 x i64> %3
+}
+
+define <8 x i8> @lshr_v8i8(<8 x i8> %0, <8 x i8> %1){
+; CHECK-LABEL: lshr_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.8b, v1.8b
+; CHECK-NEXT: ushl v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %3 = lshr <8 x i8> %0, %1
+ ret <8 x i8> %3
+}
+
+define <16 x i8> @lshr_v16i8(<16 x i8> %0, <16 x i8> %1){
+; CHECK-LABEL: lshr_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.16b, v1.16b
+; CHECK-NEXT: ushl v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %3 = lshr <16 x i8> %0, %1
+ ret <16 x i8> %3
+}
+
+define <4 x i16> @lshr_v4i16(<4 x i16> %0, <4 x i16> %1){
+; CHECK-LABEL: lshr_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4h, v1.4h
+; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %3 = lshr <4 x i16> %0, %1
+ ret <4 x i16> %3
+}
+
+define <8 x i16> @lshr_v8i16(<8 x i16> %0, <8 x i16> %1){
+; CHECK-LABEL: lshr_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.8h, v1.8h
+; CHECK-NEXT: ushl v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %3 = lshr <8 x i16> %0, %1
+ ret <8 x i16> %3
+}
+
+define <2 x i32> @lshr_v2i32(<2 x i32> %0, <2 x i32> %1){
+; CHECK-LABEL: lshr_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.2s, v1.2s
+; CHECK-NEXT: ushl v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %3 = lshr <2 x i32> %0, %1
+ ret <2 x i32> %3
+}
+
+define <4 x i32> @lshr_v4i32(<4 x i32> %0, <4 x i32> %1){
+; CHECK-LABEL: lshr_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4s, v1.4s
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %3 = lshr <4 x i32> %0, %1
+ ret <4 x i32> %3
+}
+
+define <2 x i64> @lshr_v2i64(<2 x i64> %0, <2 x i64> %1){
+; CHECK-LABEL: lshr_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.2d, v1.2d
+; CHECK-NEXT: ushl v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %3 = lshr <2 x i64> %0, %1
+ ret <2 x i64> %3
+}
+
+; ===== Vector Larger/Smaller than Legal =====
+
+define <4 x i8> @shl_v4i8(<4 x i8> %0, <4 x i8> %1){
+; CHECK-LABEL: shl_v4i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v1.4h, #255, lsl #8
+; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %3 = shl <4 x i8> %0, %1
+ ret <4 x i8> %3
+}
+
+define <32 x i8> @shl_v32i8(<32 x i8> %0, <32 x i8> %1){
+; CHECK-LABEL: shl_v32i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushl v1.16b, v1.16b, v3.16b
+; CHECK-NEXT: ushl v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: ret
+ %3 = shl <32 x i8> %0, %1
+ ret <32 x i8> %3
+}
+
+define <2 x i16> @shl_v2i16(<2 x i16> %0, <2 x i16> %1){
+; CHECK-LABEL: shl_v2i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-NEXT: ushl v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %3 = shl <2 x i16> %0, %1
+ ret <2 x i16> %3
+}
+
+define <16 x i16> @shl_v16i16(<16 x i16> %0, <16 x i16> %1){
+; CHECK-LABEL: shl_v16i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushl v1.8h, v1.8h, v3.8h
+; CHECK-NEXT: ushl v0.8h, v0.8h, v2.8h
+; CHECK-NEXT: ret
+ %3 = shl <16 x i16> %0, %1
+ ret <16 x i16> %3
+}
+
+define <1 x i32> @shl_v1i32(<1 x i32> %0, <1 x i32> %1){
+; CHECK-SD-LABEL: shl_v1i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushl v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shl_v1i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: lsl w8, w8, w9
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
+ %3 = shl <1 x i32> %0, %1
+ ret <1 x i32> %3
+}
+
+define <8 x i32> @shl_v8i32(<8 x i32> %0, <8 x i32> %1){
+; CHECK-SD-LABEL: shl_v8i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v3.4s
+; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shl_v8i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: ushl v1.4s, v1.4s, v3.4s
+; CHECK-GI-NEXT: ret
+ %3 = shl <8 x i32> %0, %1
+ ret <8 x i32> %3
+}
+
+define <4 x i64> @shl_v4i64(<4 x i64> %0, <4 x i64> %1){
+; CHECK-SD-LABEL: shl_v4i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v3.2d
+; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v2.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shl_v4i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v2.2d
+; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v3.2d
+; CHECK-GI-NEXT: ret
+ %3 = shl <4 x i64> %0, %1
+ ret <4 x i64> %3
+}
+
+define <4 x i8> @ashr_v4i8(<4 x i8> %0, <4 x i8> %1){
+; CHECK-LABEL: ashr_v4i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl v0.4h, v0.4h, #8
+; CHECK-NEXT: bic v1.4h, #255, lsl #8
+; CHECK-NEXT: sshr v0.4h, v0.4h, #8
+; CHECK-NEXT: neg v1.4h, v1.4h
+; CHECK-NEXT: sshl v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %3 = ashr <4 x i8> %0, %1
+ ret <4 x i8> %3
+}
+
+define <32 x i8> @ashr_v32i8(<32 x i8> %0, <32 x i8> %1){
+; CHECK-LABEL: ashr_v32i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v2.16b, v2.16b
+; CHECK-NEXT: neg v3.16b, v3.16b
+; CHECK-NEXT: sshl v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: sshl v1.16b, v1.16b, v3.16b
+; CHECK-NEXT: ret
+ %3 = ashr <32 x i8> %0, %1
+ ret <32 x i8> %3
+}
+
+define <2 x i16> @ashr_v2i16(<2 x i16> %0, <2 x i16> %1){
+; CHECK-LABEL: ashr_v2i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-NEXT: shl v0.2s, v0.2s, #16
+; CHECK-NEXT: sshr v0.2s, v0.2s, #16
+; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-NEXT: neg v1.2s, v1.2s
+; CHECK-NEXT: sshl v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %3 = ashr <2 x i16> %0, %1
+ ret <2 x i16> %3
+}
+
+define <16 x i16> @ashr_v16i16(<16 x i16> %0, <16 x i16> %1){
+; CHECK-LABEL: ashr_v16i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v2.8h, v2.8h
+; CHECK-NEXT: neg v3.8h, v3.8h
+; CHECK-NEXT: sshl v0.8h, v0.8h, v2.8h
+; CHECK-NEXT: sshl v1.8h, v1.8h, v3.8h
+; CHECK-NEXT: ret
+ %3 = ashr <16 x i16> %0, %1
+ ret <16 x i16> %3
+}
+
+define <1 x i32> @ashr_v1i32(<1 x i32> %0, <1 x i32> %1){
+; CHECK-SD-LABEL: ashr_v1i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: neg v1.2s, v1.2s
+; CHECK-SD-NEXT: sshl v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ashr_v1i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: asr w8, w8, w9
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
+ %3 = ashr <1 x i32> %0, %1
+ ret <1 x i32> %3
+}
+
+define <8 x i32> @ashr_v8i32(<8 x i32> %0, <8 x i32> %1){
+; CHECK-LABEL: ashr_v8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v2.4s, v2.4s
+; CHECK-NEXT: neg v3.4s, v3.4s
+; CHECK-NEXT: sshl v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: sshl v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: ret
+ %3 = ashr <8 x i32> %0, %1
+ ret <8 x i32> %3
+}
+
+define <4 x i64> @ashr_v4i64(<4 x i64> %0, <4 x i64> %1){
+; CHECK-LABEL: ashr_v4i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v2.2d, v2.2d
+; CHECK-NEXT: neg v3.2d, v3.2d
+; CHECK-NEXT: sshl v0.2d, v0.2d, v2.2d
+; CHECK-NEXT: sshl v1.2d, v1.2d, v3.2d
+; CHECK-NEXT: ret
+ %3 = ashr <4 x i64> %0, %1
+ ret <4 x i64> %3
+}
+
+define <4 x i8> @lshr_v4i8(<4 x i8> %0, <4 x i8> %1){
+; CHECK-LABEL: lshr_v4i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v1.4h, #255, lsl #8
+; CHECK-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-NEXT: neg v1.4h, v1.4h
+; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %3 = lshr <4 x i8> %0, %1
+ ret <4 x i8> %3
+}
+
+define <32 x i8> @lshr_v32i8(<32 x i8> %0, <32 x i8> %1){
+; CHECK-LABEL: lshr_v32i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v2.16b, v2.16b
+; CHECK-NEXT: neg v3.16b, v3.16b
+; CHECK-NEXT: ushl v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: ushl v1.16b, v1.16b, v3.16b
+; CHECK-NEXT: ret
+ %3 = lshr <32 x i8> %0, %1
+ ret <32 x i8> %3
+}
+
+define <2 x i16> @lshr_v2i16(<2 x i16> %0, <2 x i16> %1){
+; CHECK-LABEL: lshr_v2i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
+; CHECK-NEXT: neg v1.2s, v1.2s
+; CHECK-NEXT: ushl v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %3 = lshr <2 x i16> %0, %1
+ ret <2 x i16> %3
+}
+
+define <16 x i16> @lshr_v16i16(<16 x i16> %0, <16 x i16> %1){
+; CHECK-LABEL: lshr_v16i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v2.8h, v2.8h
+; CHECK-NEXT: neg v3.8h, v3.8h
+; CHECK-NEXT: ushl v0.8h, v0.8h, v2.8h
+; CHECK-NEXT: ushl v1.8h, v1.8h, v3.8h
+; CHECK-NEXT: ret
+ %3 = lshr <16 x i16> %0, %1
+ ret <16 x i16> %3
+}
+
+define <1 x i32> @lshr_v1i32(<1 x i32> %0, <1 x i32> %1){
+; CHECK-SD-LABEL: lshr_v1i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: neg v1.2s, v1.2s
+; CHECK-SD-NEXT: ushl v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: lshr_v1i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: lsr w8, w8, w9
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
+ %3 = lshr <1 x i32> %0, %1
+ ret <1 x i32> %3
+}
+
+define <8 x i32> @lshr_v8i32(<8 x i32> %0, <8 x i32> %1){
+; CHECK-LABEL: lshr_v8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v2.4s, v2.4s
+; CHECK-NEXT: neg v3.4s, v3.4s
+; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: ushl v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: ret
+ %3 = lshr <8 x i32> %0, %1
+ ret <8 x i32> %3
+}
+
+define <4 x i64> @lshr_v4i64(<4 x i64> %0, <4 x i64> %1){
+; CHECK-LABEL: lshr_v4i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v2.2d, v2.2d
+; CHECK-NEXT: neg v3.2d, v3.2d
+; CHECK-NEXT: ushl v0.2d, v0.2d, v2.2d
+; CHECK-NEXT: ushl v1.2d, v1.2d, v3.2d
+; CHECK-NEXT: ret
+ %3 = lshr <4 x i64> %0, %1
+ ret <4 x i64> %3
+}
+
+; ===== Vector with Non-Pow 2 Width =====
+
+define <3 x i8> @shl_v3i8(<3 x i8> %0, <3 x i8> %1){
+; CHECK-LABEL: shl_v3i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s0, w3
+; CHECK-NEXT: fmov s1, w0
+; CHECK-NEXT: mov v0.h[1], w4
+; CHECK-NEXT: mov v1.h[1], w1
+; CHECK-NEXT: mov v0.h[2], w5
+; CHECK-NEXT: mov v1.h[2], w2
+; CHECK-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-NEXT: ushl v0.4h, v1.4h, v0.4h
+; CHECK-NEXT: umov w0, v0.h[0]
+; CHECK-NEXT: umov w1, v0.h[1]
+; CHECK-NEXT: umov w2, v0.h[2]
+; CHECK-NEXT: ret
+ %3 = shl <3 x i8> %0, %1
+ ret <3 x i8> %3
+}
+
+define <7 x i8> @shl_v7i8(<7 x i8> %0, <7 x i8> %1){
+; CHECK-LABEL: shl_v7i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushl v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %3 = shl <7 x i8> %0, %1
+ ret <7 x i8> %3
+}
+
+define <3 x i16> @shl_v3i16(<3 x i16> %0, <3 x i16> %1){
+; CHECK-LABEL: shl_v3i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %3 = shl <3 x i16> %0, %1
+ ret <3 x i16> %3
+}
+
+define <7 x i16> @shl_v7i16(<7 x i16> %0, <7 x i16> %1){
+; CHECK-LABEL: shl_v7i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushl v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %3 = shl <7 x i16> %0, %1
+ ret <7 x i16> %3
+}
+
+define <3 x i32> @shl_v3i32(<3 x i32> %0, <3 x i32> %1){
+; CHECK-LABEL: shl_v3i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %3 = shl <3 x i32> %0, %1
+ ret <3 x i32> %3
+}
+
+define <3 x i8> @ashr_v3i8(<3 x i8> %0, <3 x i8> %1){
+; CHECK-LABEL: ashr_v3i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: fmov s1, w3
+; CHECK-NEXT: mov v0.h[1], w1
+; CHECK-NEXT: mov v1.h[1], w4
+; CHECK-NEXT: mov v0.h[2], w2
+; CHECK-NEXT: mov v1.h[2], w5
+; CHECK-NEXT: shl v0.4h, v0.4h, #8
+; CHECK-NEXT: bic v1.4h, #255, lsl #8
+; CHECK-NEXT: sshr v0.4h, v0.4h, #8
+; CHECK-NEXT: neg v1.4h, v1.4h
+; CHECK-NEXT: sshl v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: umov w0, v0.h[0]
+; CHECK-NEXT: umov w1, v0.h[1]
+; CHECK-NEXT: umov w2, v0.h[2]
+; CHECK-NEXT: ret
+ %3 = ashr <3 x i8> %0, %1
+ ret <3 x i8> %3
+}
+
+define <7 x i8> @ashr_v7i8(<7 x i8> %0, <7 x i8> %1){
+; CHECK-LABEL: ashr_v7i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.8b, v1.8b
+; CHECK-NEXT: sshl v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %3 = ashr <7 x i8> %0, %1
+ ret <7 x i8> %3
+}
+
+define <3 x i16> @ashr_v3i16(<3 x i16> %0, <3 x i16> %1){
+; CHECK-LABEL: ashr_v3i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4h, v1.4h
+; CHECK-NEXT: sshl v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %3 = ashr <3 x i16> %0, %1
+ ret <3 x i16> %3
+}
+
+define <7 x i16> @ashr_v7i16(<7 x i16> %0, <7 x i16> %1){
+; CHECK-LABEL: ashr_v7i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.8h, v1.8h
+; CHECK-NEXT: sshl v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %3 = ashr <7 x i16> %0, %1
+ ret <7 x i16> %3
+}
+
+define <3 x i32> @ashr_v3i32(<3 x i32> %0, <3 x i32> %1){
+; CHECK-LABEL: ashr_v3i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4s, v1.4s
+; CHECK-NEXT: sshl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %3 = ashr <3 x i32> %0, %1
+ ret <3 x i32> %3
+}
+
+define <3 x i8> @lshr_v3i8(<3 x i8> %0, <3 x i8> %1){
+; CHECK-LABEL: lshr_v3i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s0, w3
+; CHECK-NEXT: fmov s1, w0
+; CHECK-NEXT: mov v0.h[1], w4
+; CHECK-NEXT: mov v1.h[1], w1
+; CHECK-NEXT: mov v0.h[2], w5
+; CHECK-NEXT: mov v1.h[2], w2
+; CHECK-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-NEXT: bic v1.4h, #255, lsl #8
+; CHECK-NEXT: neg v0.4h, v0.4h
+; CHECK-NEXT: ushl v0.4h, v1.4h, v0.4h
+; CHECK-NEXT: umov w0, v0.h[0]
+; CHECK-NEXT: umov w1, v0.h[1]
+; CHECK-NEXT: umov w2, v0.h[2]
+; CHECK-NEXT: ret
+ %3 = lshr <3 x i8> %0, %1
+ ret <3 x i8> %3
+}
+
+define <7 x i8> @lshr_v7i8(<7 x i8> %0, <7 x i8> %1){
+; CHECK-LABEL: lshr_v7i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.8b, v1.8b
+; CHECK-NEXT: ushl v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %3 = lshr <7 x i8> %0, %1
+ ret <7 x i8> %3
+}
+
+define <3 x i16> @lshr_v3i16(<3 x i16> %0, <3 x i16> %1){
+; CHECK-LABEL: lshr_v3i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4h, v1.4h
+; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %3 = lshr <3 x i16> %0, %1
+ ret <3 x i16> %3
+}
+
+define <7 x i16> @lshr_v7i16(<7 x i16> %0, <7 x i16> %1){
+; CHECK-LABEL: lshr_v7i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.8h, v1.8h
+; CHECK-NEXT: ushl v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %3 = lshr <7 x i16> %0, %1
+ ret <7 x i16> %3
+}
+
+define <3 x i32> @lshr_v3i32(<3 x i32> %0, <3 x i32> %1){
+; CHECK-LABEL: lshr_v3i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4s, v1.4s
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %3 = lshr <3 x i32> %0, %1
+ ret <3 x i32> %3
+}
+
+; TODO:
+; ===== Vector with Odd Element Sizes =====
>From b4c47755cda7c931d3df5d529e808b75bf8ce043 Mon Sep 17 00:00:00 2001
From: Tuan Chuong Goh <chuong.goh at arm.com>
Date: Fri, 19 Jan 2024 14:17:57 +0000
Subject: [PATCH 2/2] [AArch64][GlobalISel] Legalize Shifts for Smaller/Larger
Vectors
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 5 +-
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 2 +
llvm/test/CodeGen/AArch64/fcmp.ll | 303 ++++++++++--------
llvm/test/CodeGen/AArch64/sext.ll | 71 ++--
llvm/test/CodeGen/AArch64/shift.ll | 234 +++++++++-----
5 files changed, 385 insertions(+), 230 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 91d2497fdb7e20..994ee6ebc94345 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -5198,7 +5198,10 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
case TargetOpcode::G_FMAXIMUM:
case TargetOpcode::G_STRICT_FADD:
case TargetOpcode::G_STRICT_FSUB:
- case TargetOpcode::G_STRICT_FMUL: {
+ case TargetOpcode::G_STRICT_FMUL:
+ case TargetOpcode::G_SHL:
+ case TargetOpcode::G_ASHR:
+ case TargetOpcode::G_LSHR: {
Observer.changingInstr(MI);
moreElementsVectorSrc(MI, MoreTy, 1);
moreElementsVectorSrc(MI, MoreTy, 2);
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index e94f9d0c68ffe7..ea3b215cf5b482 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -169,6 +169,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.widenScalarToNextPow2(0)
.clampScalar(1, s32, s64)
.clampScalar(0, s32, s64)
+ .clampNumElements(0, v8s8, v16s8)
+ .clampNumElements(0, v4s16, v8s16)
.clampNumElements(0, v2s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
.moreElementsToNextPow2(0)
diff --git a/llvm/test/CodeGen/AArch64/fcmp.ll b/llvm/test/CodeGen/AArch64/fcmp.ll
index 82e29d0f8a194f..d3bc7fc6dc0634 100644
--- a/llvm/test/CodeGen/AArch64/fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/fcmp.ll
@@ -8,9 +8,9 @@
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v3f64_i32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v3f32_float
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v3f32_i32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v7f16_half
+; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for v7f16_half
; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for v16f16_half
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v7f16_i32
+; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for v7f16_i32
; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for v16f16_i32
define double @f64_double(double %a, double %b, double %d, double %e) {
@@ -437,62 +437,87 @@ define <7 x half> @v7f16_half(<7 x half> %a, <7 x half> %b, <7 x half> %d, <7 x
;
; CHECK-GI-NOFP16-LABEL: v7f16_half:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[1]
-; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[1]
-; CHECK-GI-NOFP16-NEXT: fcvt s6, h1
-; CHECK-GI-NOFP16-NEXT: fcvt s7, h0
-; CHECK-GI-NOFP16-NEXT: mov h16, v1.h[2]
-; CHECK-GI-NOFP16-NEXT: fcvt s4, h4
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[1]
+; CHECK-GI-NOFP16-NEXT: mov w9, #15 // =0xf
+; CHECK-GI-NOFP16-NEXT: fcvt s6, h0
+; CHECK-GI-NOFP16-NEXT: fcvt s7, h1
+; CHECK-GI-NOFP16-NEXT: mov h16, v0.h[2]
+; CHECK-GI-NOFP16-NEXT: mov h17, v1.h[2]
+; CHECK-GI-NOFP16-NEXT: mov h19, v1.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h20, v1.h[5]
+; CHECK-GI-NOFP16-NEXT: fcvt s18, h4
; CHECK-GI-NOFP16-NEXT: fcvt s5, h5
-; CHECK-GI-NOFP16-NEXT: fcmp s5, s4
-; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[2]
-; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[3]
-; CHECK-GI-NOFP16-NEXT: csetm w8, mi
-; CHECK-GI-NOFP16-NEXT: fcmp s7, s6
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
+; CHECK-GI-NOFP16-NEXT: fcmp s6, s7
; CHECK-GI-NOFP16-NEXT: fcvt s7, h16
-; CHECK-GI-NOFP16-NEXT: fcvt s4, h4
-; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvt s5, h5
-; CHECK-GI-NOFP16-NEXT: mov h16, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: csetm w9, mi
-; CHECK-GI-NOFP16-NEXT: fcmp s4, s7
-; CHECK-GI-NOFP16-NEXT: fmov s4, w9
-; CHECK-GI-NOFP16-NEXT: fcvt s6, h6
-; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[4]
-; CHECK-GI-NOFP16-NEXT: fcvt s16, h16
-; CHECK-GI-NOFP16-NEXT: mov v4.h[1], w8
-; CHECK-GI-NOFP16-NEXT: csetm w8, mi
-; CHECK-GI-NOFP16-NEXT: fcmp s6, s5
-; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvt s7, h7
-; CHECK-GI-NOFP16-NEXT: mov v4.h[2], w8
-; CHECK-GI-NOFP16-NEXT: csetm w8, mi
-; CHECK-GI-NOFP16-NEXT: fcvt s5, h5
-; CHECK-GI-NOFP16-NEXT: fcvt s6, h6
-; CHECK-GI-NOFP16-NEXT: fcmp s16, s7
-; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[6]
-; CHECK-GI-NOFP16-NEXT: mov h16, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[7]
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[7]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[3], w8
-; CHECK-GI-NOFP16-NEXT: csetm w8, mi
-; CHECK-GI-NOFP16-NEXT: fcmp s6, s5
-; CHECK-GI-NOFP16-NEXT: fcvt s5, h7
-; CHECK-GI-NOFP16-NEXT: fcvt s6, h16
+; CHECK-GI-NOFP16-NEXT: fmov s6, w9
+; CHECK-GI-NOFP16-NEXT: fcvt s16, h17
+; CHECK-GI-NOFP16-NEXT: mov h17, v1.h[3]
+; CHECK-GI-NOFP16-NEXT: fcvt s19, h19
+; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[6]
+; CHECK-GI-NOFP16-NEXT: cset w8, mi
+; CHECK-GI-NOFP16-NEXT: fcmp s18, s5
+; CHECK-GI-NOFP16-NEXT: mov h18, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: fmov s5, w8
+; CHECK-GI-NOFP16-NEXT: cset w9, mi
+; CHECK-GI-NOFP16-NEXT: fcmp s7, s16
+; CHECK-GI-NOFP16-NEXT: fcvt s7, h4
+; CHECK-GI-NOFP16-NEXT: fcvt s16, h17
+; CHECK-GI-NOFP16-NEXT: fmov s17, w9
+; CHECK-GI-NOFP16-NEXT: mov v4.16b, v6.16b
+; CHECK-GI-NOFP16-NEXT: fcvt s18, h18
; CHECK-GI-NOFP16-NEXT: fcvt s1, h1
+; CHECK-GI-NOFP16-NEXT: cset w8, mi
+; CHECK-GI-NOFP16-NEXT: mov v5.h[1], v17.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v4.h[1], v6.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h17, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: fcmp s7, s16
+; CHECK-GI-NOFP16-NEXT: fmov s7, w8
+; CHECK-GI-NOFP16-NEXT: mov w8, #65535 // =0xffff
+; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: mov v5.h[2], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: fmov s7, w8
+; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v6.h[0]
+; CHECK-GI-NOFP16-NEXT: cset w8, mi
+; CHECK-GI-NOFP16-NEXT: fcmp s18, s19
+; CHECK-GI-NOFP16-NEXT: fcvt s17, h17
+; CHECK-GI-NOFP16-NEXT: fcvt s18, h20
+; CHECK-GI-NOFP16-NEXT: fmov s19, w8
; CHECK-GI-NOFP16-NEXT: fcvt s0, h0
-; CHECK-GI-NOFP16-NEXT: mov v4.h[4], w8
-; CHECK-GI-NOFP16-NEXT: csetm w8, mi
-; CHECK-GI-NOFP16-NEXT: fcmp s6, s5
-; CHECK-GI-NOFP16-NEXT: mov v4.h[5], w8
-; CHECK-GI-NOFP16-NEXT: csetm w8, mi
+; CHECK-GI-NOFP16-NEXT: mov v16.16b, v7.16b
+; CHECK-GI-NOFP16-NEXT: mov v4.h[3], v6.h[0]
+; CHECK-GI-NOFP16-NEXT: cset w8, mi
+; CHECK-GI-NOFP16-NEXT: mov v5.h[3], v19.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v16.h[1], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: fcmp s17, s18
+; CHECK-GI-NOFP16-NEXT: fmov s17, w8
+; CHECK-GI-NOFP16-NEXT: mov v4.h[4], v6.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v5.h[4], v17.h[0]
+; CHECK-GI-NOFP16-NEXT: cset w8, mi
; CHECK-GI-NOFP16-NEXT: fcmp s0, s1
-; CHECK-GI-NOFP16-NEXT: mov v4.h[6], w8
-; CHECK-GI-NOFP16-NEXT: csetm w8, mi
-; CHECK-GI-NOFP16-NEXT: mov v4.h[7], w8
-; CHECK-GI-NOFP16-NEXT: mov v0.16b, v4.16b
-; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-GI-NOFP16-NEXT: mov v16.h[2], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: fmov s0, w8
+; CHECK-GI-NOFP16-NEXT: mov v4.h[5], v6.h[0]
+; CHECK-GI-NOFP16-NEXT: cset w8, mi
+; CHECK-GI-NOFP16-NEXT: mov v5.h[5], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: fmov s0, w8
+; CHECK-GI-NOFP16-NEXT: mov v16.h[3], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v4.h[6], v6.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v5.h[6], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v16.h[4], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v4.h[7], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v5.h[7], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v16.h[5], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: neg v0.8h, v4.8h
+; CHECK-GI-NOFP16-NEXT: ushl v1.8h, v5.8h, v4.8h
+; CHECK-GI-NOFP16-NEXT: mov v16.h[6], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v16.h[7], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: sshl v0.8h, v1.8h, v0.8h
+; CHECK-GI-NOFP16-NEXT: eor v1.16b, v0.16b, v16.16b
+; CHECK-GI-NOFP16-NEXT: and v0.16b, v2.16b, v0.16b
+; CHECK-GI-NOFP16-NEXT: and v1.16b, v3.16b, v1.16b
+; CHECK-GI-NOFP16-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: v7f16_half:
@@ -1112,90 +1137,110 @@ define <7 x i32> @v7f16_i32(<7 x half> %a, <7 x half> %b, <7 x i32> %d, <7 x i32
;
; CHECK-GI-NOFP16-LABEL: v7f16_i32:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h2, v1.h[1]
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[1]
-; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[2]
-; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[2]
-; CHECK-GI-NOFP16-NEXT: fcvt s6, h1
-; CHECK-GI-NOFP16-NEXT: fcvt s7, h0
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: mov h3, v1.h[1]
+; CHECK-GI-NOFP16-NEXT: mov w13, #31 // =0x1f
+; CHECK-GI-NOFP16-NEXT: fcvt s4, h0
+; CHECK-GI-NOFP16-NEXT: fcvt s5, h1
+; CHECK-GI-NOFP16-NEXT: ldr s17, [sp, #40]
+; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[2]
+; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[2]
+; CHECK-GI-NOFP16-NEXT: fmov s16, w0
; CHECK-GI-NOFP16-NEXT: fcvt s2, h2
; CHECK-GI-NOFP16-NEXT: fcvt s3, h3
+; CHECK-GI-NOFP16-NEXT: fcmp s4, s5
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
+; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[3]
+; CHECK-GI-NOFP16-NEXT: fcvt s6, h6
+; CHECK-GI-NOFP16-NEXT: fcvt s7, h7
+; CHECK-GI-NOFP16-NEXT: mov v16.s[1], w1
+; CHECK-GI-NOFP16-NEXT: cset w9, mi
+; CHECK-GI-NOFP16-NEXT: fcmp s2, s3
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h3, v1.h[4]
; CHECK-GI-NOFP16-NEXT: fcvt s4, h4
; CHECK-GI-NOFP16-NEXT: fcvt s5, h5
-; CHECK-GI-NOFP16-NEXT: fcmp s3, s2
-; CHECK-GI-NOFP16-NEXT: mov h2, v1.h[3]
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: csetm w8, mi
-; CHECK-GI-NOFP16-NEXT: fcmp s7, s6
-; CHECK-GI-NOFP16-NEXT: mov h6, v1.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h7, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov v16.s[2], w2
+; CHECK-GI-NOFP16-NEXT: cset w10, mi
+; CHECK-GI-NOFP16-NEXT: fcmp s6, s7
+; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[5]
; CHECK-GI-NOFP16-NEXT: fcvt s2, h2
+; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
; CHECK-GI-NOFP16-NEXT: fcvt s3, h3
-; CHECK-GI-NOFP16-NEXT: csetm w9, mi
-; CHECK-GI-NOFP16-NEXT: fcmp s5, s4
-; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: fcvt s6, h6
-; CHECK-GI-NOFP16-NEXT: fcvt s7, h7
-; CHECK-GI-NOFP16-NEXT: csetm w10, mi
-; CHECK-GI-NOFP16-NEXT: fcmp s3, s2
-; CHECK-GI-NOFP16-NEXT: fcvt s2, h4
-; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[6]
-; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[7]
-; CHECK-GI-NOFP16-NEXT: fcvt s3, h5
-; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[7]
-; CHECK-GI-NOFP16-NEXT: csetm w11, mi
-; CHECK-GI-NOFP16-NEXT: fcmp s7, s6
-; CHECK-GI-NOFP16-NEXT: fcvt s1, h1
-; CHECK-GI-NOFP16-NEXT: csetm w12, mi
-; CHECK-GI-NOFP16-NEXT: fcmp s3, s2
-; CHECK-GI-NOFP16-NEXT: fcvt s2, h4
-; CHECK-GI-NOFP16-NEXT: fcvt s3, h5
-; CHECK-GI-NOFP16-NEXT: fmov s4, w9
+; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[6]
+; CHECK-GI-NOFP16-NEXT: cset w11, mi
+; CHECK-GI-NOFP16-NEXT: fcmp s4, s5
+; CHECK-GI-NOFP16-NEXT: mov v16.s[3], w3
+; CHECK-GI-NOFP16-NEXT: fcvt s4, h6
+; CHECK-GI-NOFP16-NEXT: ldr s6, [sp, #32]
+; CHECK-GI-NOFP16-NEXT: fcvt s5, h7
; CHECK-GI-NOFP16-NEXT: fcvt s0, h0
-; CHECK-GI-NOFP16-NEXT: add x9, sp, #8
-; CHECK-GI-NOFP16-NEXT: csetm w13, mi
-; CHECK-GI-NOFP16-NEXT: fmov s5, w13
-; CHECK-GI-NOFP16-NEXT: mov v4.h[1], w8
-; CHECK-GI-NOFP16-NEXT: mov x8, sp
-; CHECK-GI-NOFP16-NEXT: fcmp s3, s2
-; CHECK-GI-NOFP16-NEXT: fmov s2, w7
-; CHECK-GI-NOFP16-NEXT: fmov s3, w0
-; CHECK-GI-NOFP16-NEXT: mov v5.h[1], w12
-; CHECK-GI-NOFP16-NEXT: ld1 { v2.s }[1], [x8]
-; CHECK-GI-NOFP16-NEXT: mov v3.s[1], w1
-; CHECK-GI-NOFP16-NEXT: csetm w8, mi
-; CHECK-GI-NOFP16-NEXT: mov v4.h[2], w10
+; CHECK-GI-NOFP16-NEXT: fmov s7, w4
+; CHECK-GI-NOFP16-NEXT: cset w8, mi
+; CHECK-GI-NOFP16-NEXT: fcmp s2, s3
+; CHECK-GI-NOFP16-NEXT: fcvt s1, h1
+; CHECK-GI-NOFP16-NEXT: fmov s2, w13
+; CHECK-GI-NOFP16-NEXT: mov v7.s[1], w5
+; CHECK-GI-NOFP16-NEXT: cset w12, mi
+; CHECK-GI-NOFP16-NEXT: fcmp s4, s5
+; CHECK-GI-NOFP16-NEXT: ldr s5, [sp]
+; CHECK-GI-NOFP16-NEXT: fmov s3, w12
+; CHECK-GI-NOFP16-NEXT: mov v2.s[1], w13
+; CHECK-GI-NOFP16-NEXT: cset w14, mi
; CHECK-GI-NOFP16-NEXT: fcmp s0, s1
-; CHECK-GI-NOFP16-NEXT: fmov s1, w4
-; CHECK-GI-NOFP16-NEXT: ldr s0, [sp, #24]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[2], w8
-; CHECK-GI-NOFP16-NEXT: ld1 { v2.s }[2], [x9]
-; CHECK-GI-NOFP16-NEXT: add x9, sp, #32
-; CHECK-GI-NOFP16-NEXT: mov v3.s[2], w2
-; CHECK-GI-NOFP16-NEXT: mov v1.s[1], w5
-; CHECK-GI-NOFP16-NEXT: csetm w8, mi
-; CHECK-GI-NOFP16-NEXT: mov v4.h[3], w11
-; CHECK-GI-NOFP16-NEXT: ld1 { v0.s }[1], [x9]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[3], w8
-; CHECK-GI-NOFP16-NEXT: add x8, sp, #16
-; CHECK-GI-NOFP16-NEXT: ld1 { v2.s }[3], [x8]
-; CHECK-GI-NOFP16-NEXT: mov v3.s[3], w3
-; CHECK-GI-NOFP16-NEXT: add x8, sp, #40
-; CHECK-GI-NOFP16-NEXT: mov v1.s[2], w6
-; CHECK-GI-NOFP16-NEXT: sshll v4.4s, v4.4h, #0
-; CHECK-GI-NOFP16-NEXT: ld1 { v0.s }[2], [x8]
-; CHECK-GI-NOFP16-NEXT: sshll v5.4s, v5.4h, #0
-; CHECK-GI-NOFP16-NEXT: bit v2.16b, v3.16b, v4.16b
-; CHECK-GI-NOFP16-NEXT: bit v0.16b, v1.16b, v5.16b
-; CHECK-GI-NOFP16-NEXT: mov w1, v2.s[1]
-; CHECK-GI-NOFP16-NEXT: mov w2, v2.s[2]
-; CHECK-GI-NOFP16-NEXT: mov w3, v2.s[3]
-; CHECK-GI-NOFP16-NEXT: fmov w0, s2
-; CHECK-GI-NOFP16-NEXT: mov w5, v0.s[1]
-; CHECK-GI-NOFP16-NEXT: mov w6, v0.s[2]
-; CHECK-GI-NOFP16-NEXT: fmov w4, s0
+; CHECK-GI-NOFP16-NEXT: fmov s0, w9
+; CHECK-GI-NOFP16-NEXT: mov v3.s[1], w14
+; CHECK-GI-NOFP16-NEXT: ldr s1, [sp, #24]
+; CHECK-GI-NOFP16-NEXT: mov v7.s[2], w6
+; CHECK-GI-NOFP16-NEXT: mov v2.s[2], w13
+; CHECK-GI-NOFP16-NEXT: cset w9, mi
+; CHECK-GI-NOFP16-NEXT: mov v0.s[1], w10
+; CHECK-GI-NOFP16-NEXT: fmov w10, s5
+; CHECK-GI-NOFP16-NEXT: fmov s5, w7
+; CHECK-GI-NOFP16-NEXT: mov v1.s[1], v6.s[0]
+; CHECK-GI-NOFP16-NEXT: ldr s6, [sp, #8]
+; CHECK-GI-NOFP16-NEXT: mov v3.s[2], w9
+; CHECK-GI-NOFP16-NEXT: mov w9, #-1 // =0xffffffff
+; CHECK-GI-NOFP16-NEXT: fmov s4, w9
+; CHECK-GI-NOFP16-NEXT: mov v2.s[3], w8
+; CHECK-GI-NOFP16-NEXT: mov v0.s[2], w11
+; CHECK-GI-NOFP16-NEXT: mov v5.s[1], w10
+; CHECK-GI-NOFP16-NEXT: mov v1.s[2], v17.s[0]
+; CHECK-GI-NOFP16-NEXT: mov v4.s[1], w9
+; CHECK-GI-NOFP16-NEXT: mov v3.s[3], w8
+; CHECK-GI-NOFP16-NEXT: neg v18.4s, v2.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.s[3], w8
+; CHECK-GI-NOFP16-NEXT: fmov w8, s6
+; CHECK-GI-NOFP16-NEXT: mov v4.s[2], w9
+; CHECK-GI-NOFP16-NEXT: ushl v2.4s, v3.4s, v2.4s
+; CHECK-GI-NOFP16-NEXT: ldr s3, [sp, #16]
+; CHECK-GI-NOFP16-NEXT: mov v5.s[2], w8
+; CHECK-GI-NOFP16-NEXT: mov v7.s[3], w8
+; CHECK-GI-NOFP16-NEXT: shl v0.4s, v0.4s, #31
+; CHECK-GI-NOFP16-NEXT: sshl v2.4s, v2.4s, v18.4s
+; CHECK-GI-NOFP16-NEXT: mov v4.s[3], w8
+; CHECK-GI-NOFP16-NEXT: fmov w8, s3
+; CHECK-GI-NOFP16-NEXT: mov v1.s[3], v0.s[0]
+; CHECK-GI-NOFP16-NEXT: sshr v0.4s, v0.4s, #31
+; CHECK-GI-NOFP16-NEXT: mov v5.s[3], w8
+; CHECK-GI-NOFP16-NEXT: eor v3.16b, v2.16b, v4.16b
+; CHECK-GI-NOFP16-NEXT: and v2.16b, v7.16b, v2.16b
+; CHECK-GI-NOFP16-NEXT: and v1.16b, v1.16b, v3.16b
+; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v16.16b, v5.16b
+; CHECK-GI-NOFP16-NEXT: orr v1.16b, v2.16b, v1.16b
+; CHECK-GI-NOFP16-NEXT: mov s2, v0.s[1]
+; CHECK-GI-NOFP16-NEXT: mov s3, v0.s[2]
+; CHECK-GI-NOFP16-NEXT: mov s4, v0.s[3]
+; CHECK-GI-NOFP16-NEXT: fmov w0, s0
+; CHECK-GI-NOFP16-NEXT: mov s5, v1.s[1]
+; CHECK-GI-NOFP16-NEXT: mov s6, v1.s[2]
+; CHECK-GI-NOFP16-NEXT: fmov w4, s1
+; CHECK-GI-NOFP16-NEXT: fmov w1, s2
+; CHECK-GI-NOFP16-NEXT: fmov w2, s3
+; CHECK-GI-NOFP16-NEXT: fmov w3, s4
+; CHECK-GI-NOFP16-NEXT: fmov w5, s5
+; CHECK-GI-NOFP16-NEXT: fmov w6, s6
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: v7f16_i32:
diff --git a/llvm/test/CodeGen/AArch64/sext.ll b/llvm/test/CodeGen/AArch64/sext.ll
index dd53780be14c16..f319721e0f2f0f 100644
--- a/llvm/test/CodeGen/AArch64/sext.ll
+++ b/llvm/test/CodeGen/AArch64/sext.ll
@@ -2,9 +2,6 @@
; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for sext_v3i8_v3i32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sext_v3i10_v3i32
-
define i16 @sext_i8_to_i16(i8 %a) {
; CHECK-LABEL: sext_i8_to_i16:
; CHECK: // %bb.0: // %entry
@@ -236,15 +233,31 @@ entry:
}
define <3 x i32> @sext_v3i8_v3i32(<3 x i8> %a) {
-; CHECK-LABEL: sext_v3i8_v3i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: mov v0.h[1], w1
-; CHECK-NEXT: mov v0.h[2], w2
-; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: shl v0.4s, v0.4s, #24
-; CHECK-NEXT: sshr v0.4s, v0.4s, #24
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sext_v3i8_v3i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fmov s0, w0
+; CHECK-SD-NEXT: mov v0.h[1], w1
+; CHECK-SD-NEXT: mov v0.h[2], w2
+; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: shl v0.4s, v0.4s, #24
+; CHECK-SD-NEXT: sshr v0.4s, v0.4s, #24
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sext_v3i8_v3i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov w8, #24 // =0x18
+; CHECK-GI-NEXT: fmov s1, w0
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: mov v1.s[1], w1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: mov v1.s[2], w2
+; CHECK-GI-NEXT: mov v0.s[2], w8
+; CHECK-GI-NEXT: mov v1.s[3], w8
+; CHECK-GI-NEXT: mov v0.s[3], w8
+; CHECK-GI-NEXT: neg v2.4s, v0.4s
+; CHECK-GI-NEXT: ushl v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sext <3 x i8> %a to <3 x i32>
ret <3 x i32> %c
@@ -388,15 +401,31 @@ entry:
}
define <3 x i32> @sext_v3i10_v3i32(<3 x i10> %a) {
-; CHECK-LABEL: sext_v3i10_v3i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: mov v0.h[1], w1
-; CHECK-NEXT: mov v0.h[2], w2
-; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: shl v0.4s, v0.4s, #22
-; CHECK-NEXT: sshr v0.4s, v0.4s, #22
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sext_v3i10_v3i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fmov s0, w0
+; CHECK-SD-NEXT: mov v0.h[1], w1
+; CHECK-SD-NEXT: mov v0.h[2], w2
+; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: shl v0.4s, v0.4s, #22
+; CHECK-SD-NEXT: sshr v0.4s, v0.4s, #22
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sext_v3i10_v3i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov w8, #22 // =0x16
+; CHECK-GI-NEXT: fmov s1, w0
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: mov v1.s[1], w1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: mov v1.s[2], w2
+; CHECK-GI-NEXT: mov v0.s[2], w8
+; CHECK-GI-NEXT: mov v1.s[3], w8
+; CHECK-GI-NEXT: mov v0.s[3], w8
+; CHECK-GI-NEXT: neg v2.4s, v0.4s
+; CHECK-GI-NEXT: ushl v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sext <3 x i10> %a to <3 x i32>
ret <3 x i32> %c
diff --git a/llvm/test/CodeGen/AArch64/shift.ll b/llvm/test/CodeGen/AArch64/shift.ll
index 55ff97563e1efe..15c8e1792f3d31 100644
--- a/llvm/test/CodeGen/AArch64/shift.ll
+++ b/llvm/test/CodeGen/AArch64/shift.ll
@@ -3,33 +3,11 @@
; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for shl_v4i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v32i8
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v2i16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v16i16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v4i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v32i8
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v2i16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v16i16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v4i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v32i8
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v2i16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v16i16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v3i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v7i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v3i16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v7i16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for shl_v3i32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v3i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v7i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v3i16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v7i16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ashr_v3i32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v3i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v7i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v3i16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v7i16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lshr_v3i32
-
define i1 @shl_i1(i1 %0, i1 %1){
; CHECK-SD-LABEL: shl_i1:
@@ -562,11 +540,17 @@ define <4 x i8> @shl_v4i8(<4 x i8> %0, <4 x i8> %1){
}
define <32 x i8> @shl_v32i8(<32 x i8> %0, <32 x i8> %1){
-; CHECK-LABEL: shl_v32i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ushl v1.16b, v1.16b, v3.16b
-; CHECK-NEXT: ushl v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shl_v32i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushl v1.16b, v1.16b, v3.16b
+; CHECK-SD-NEXT: ushl v0.16b, v0.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shl_v32i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushl v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: ushl v1.16b, v1.16b, v3.16b
+; CHECK-GI-NEXT: ret
%3 = shl <32 x i8> %0, %1
ret <32 x i8> %3
}
@@ -583,11 +567,17 @@ define <2 x i16> @shl_v2i16(<2 x i16> %0, <2 x i16> %1){
}
define <16 x i16> @shl_v16i16(<16 x i16> %0, <16 x i16> %1){
-; CHECK-LABEL: shl_v16i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ushl v1.8h, v1.8h, v3.8h
-; CHECK-NEXT: ushl v0.8h, v0.8h, v2.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shl_v16i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v3.8h
+; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shl_v16i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v3.8h
+; CHECK-GI-NEXT: ret
%3 = shl <16 x i16> %0, %1
ret <16 x i16> %3
}
@@ -834,20 +824,48 @@ define <4 x i64> @lshr_v4i64(<4 x i64> %0, <4 x i64> %1){
; ===== Vector with Non-Pow 2 Width =====
define <3 x i8> @shl_v3i8(<3 x i8> %0, <3 x i8> %1){
-; CHECK-LABEL: shl_v3i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov s0, w3
-; CHECK-NEXT: fmov s1, w0
-; CHECK-NEXT: mov v0.h[1], w4
-; CHECK-NEXT: mov v1.h[1], w1
-; CHECK-NEXT: mov v0.h[2], w5
-; CHECK-NEXT: mov v1.h[2], w2
-; CHECK-NEXT: bic v0.4h, #255, lsl #8
-; CHECK-NEXT: ushl v0.4h, v1.4h, v0.4h
-; CHECK-NEXT: umov w0, v0.h[0]
-; CHECK-NEXT: umov w1, v0.h[1]
-; CHECK-NEXT: umov w2, v0.h[2]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shl_v3i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov s0, w3
+; CHECK-SD-NEXT: fmov s1, w0
+; CHECK-SD-NEXT: mov v0.h[1], w4
+; CHECK-SD-NEXT: mov v1.h[1], w1
+; CHECK-SD-NEXT: mov v0.h[2], w5
+; CHECK-SD-NEXT: mov v1.h[2], w2
+; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-SD-NEXT: ushl v0.4h, v1.4h, v0.4h
+; CHECK-SD-NEXT: umov w0, v0.h[0]
+; CHECK-SD-NEXT: umov w1, v0.h[1]
+; CHECK-SD-NEXT: umov w2, v0.h[2]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shl_v3i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov s0, w0
+; CHECK-GI-NEXT: fmov s1, w1
+; CHECK-GI-NEXT: fmov s2, w3
+; CHECK-GI-NEXT: fmov s3, w4
+; CHECK-GI-NEXT: mov v0.b[1], v1.b[0]
+; CHECK-GI-NEXT: fmov s1, w2
+; CHECK-GI-NEXT: mov v2.b[1], v3.b[0]
+; CHECK-GI-NEXT: fmov s3, w5
+; CHECK-GI-NEXT: mov v0.b[2], v1.b[0]
+; CHECK-GI-NEXT: mov v2.b[2], v3.b[0]
+; CHECK-GI-NEXT: mov v0.b[3], v0.b[0]
+; CHECK-GI-NEXT: mov v2.b[3], v0.b[0]
+; CHECK-GI-NEXT: mov v0.b[4], v0.b[0]
+; CHECK-GI-NEXT: mov v2.b[4], v0.b[0]
+; CHECK-GI-NEXT: mov v0.b[5], v0.b[0]
+; CHECK-GI-NEXT: mov v2.b[5], v0.b[0]
+; CHECK-GI-NEXT: mov v0.b[6], v0.b[0]
+; CHECK-GI-NEXT: mov v2.b[6], v0.b[0]
+; CHECK-GI-NEXT: mov v0.b[7], v0.b[0]
+; CHECK-GI-NEXT: mov v2.b[7], v0.b[0]
+; CHECK-GI-NEXT: ushl v0.8b, v0.8b, v2.8b
+; CHECK-GI-NEXT: umov w0, v0.b[0]
+; CHECK-GI-NEXT: umov w1, v0.b[1]
+; CHECK-GI-NEXT: umov w2, v0.b[2]
+; CHECK-GI-NEXT: ret
%3 = shl <3 x i8> %0, %1
ret <3 x i8> %3
}
@@ -889,23 +907,52 @@ define <3 x i32> @shl_v3i32(<3 x i32> %0, <3 x i32> %1){
}
define <3 x i8> @ashr_v3i8(<3 x i8> %0, <3 x i8> %1){
-; CHECK-LABEL: ashr_v3i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: fmov s1, w3
-; CHECK-NEXT: mov v0.h[1], w1
-; CHECK-NEXT: mov v1.h[1], w4
-; CHECK-NEXT: mov v0.h[2], w2
-; CHECK-NEXT: mov v1.h[2], w5
-; CHECK-NEXT: shl v0.4h, v0.4h, #8
-; CHECK-NEXT: bic v1.4h, #255, lsl #8
-; CHECK-NEXT: sshr v0.4h, v0.4h, #8
-; CHECK-NEXT: neg v1.4h, v1.4h
-; CHECK-NEXT: sshl v0.4h, v0.4h, v1.4h
-; CHECK-NEXT: umov w0, v0.h[0]
-; CHECK-NEXT: umov w1, v0.h[1]
-; CHECK-NEXT: umov w2, v0.h[2]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ashr_v3i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov s0, w0
+; CHECK-SD-NEXT: fmov s1, w3
+; CHECK-SD-NEXT: mov v0.h[1], w1
+; CHECK-SD-NEXT: mov v1.h[1], w4
+; CHECK-SD-NEXT: mov v0.h[2], w2
+; CHECK-SD-NEXT: mov v1.h[2], w5
+; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8
+; CHECK-SD-NEXT: bic v1.4h, #255, lsl #8
+; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #8
+; CHECK-SD-NEXT: neg v1.4h, v1.4h
+; CHECK-SD-NEXT: sshl v0.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: umov w0, v0.h[0]
+; CHECK-SD-NEXT: umov w1, v0.h[1]
+; CHECK-SD-NEXT: umov w2, v0.h[2]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ashr_v3i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov s0, w3
+; CHECK-GI-NEXT: fmov s1, w4
+; CHECK-GI-NEXT: fmov s2, w1
+; CHECK-GI-NEXT: mov v0.b[1], v1.b[0]
+; CHECK-GI-NEXT: fmov s1, w0
+; CHECK-GI-NEXT: mov v1.b[1], v2.b[0]
+; CHECK-GI-NEXT: fmov s2, w5
+; CHECK-GI-NEXT: mov v0.b[2], v2.b[0]
+; CHECK-GI-NEXT: fmov s2, w2
+; CHECK-GI-NEXT: mov v1.b[2], v2.b[0]
+; CHECK-GI-NEXT: mov v0.b[3], v0.b[0]
+; CHECK-GI-NEXT: mov v1.b[3], v0.b[0]
+; CHECK-GI-NEXT: mov v0.b[4], v0.b[0]
+; CHECK-GI-NEXT: mov v1.b[4], v0.b[0]
+; CHECK-GI-NEXT: mov v0.b[5], v0.b[0]
+; CHECK-GI-NEXT: mov v1.b[5], v0.b[0]
+; CHECK-GI-NEXT: mov v0.b[6], v0.b[0]
+; CHECK-GI-NEXT: mov v1.b[6], v0.b[0]
+; CHECK-GI-NEXT: mov v0.b[7], v0.b[0]
+; CHECK-GI-NEXT: mov v1.b[7], v0.b[0]
+; CHECK-GI-NEXT: neg v0.8b, v0.8b
+; CHECK-GI-NEXT: sshl v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: umov w0, v0.b[0]
+; CHECK-GI-NEXT: umov w1, v0.b[1]
+; CHECK-GI-NEXT: umov w2, v0.b[2]
+; CHECK-GI-NEXT: ret
%3 = ashr <3 x i8> %0, %1
ret <3 x i8> %3
}
@@ -951,22 +998,51 @@ define <3 x i32> @ashr_v3i32(<3 x i32> %0, <3 x i32> %1){
}
define <3 x i8> @lshr_v3i8(<3 x i8> %0, <3 x i8> %1){
-; CHECK-LABEL: lshr_v3i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov s0, w3
-; CHECK-NEXT: fmov s1, w0
-; CHECK-NEXT: mov v0.h[1], w4
-; CHECK-NEXT: mov v1.h[1], w1
-; CHECK-NEXT: mov v0.h[2], w5
-; CHECK-NEXT: mov v1.h[2], w2
-; CHECK-NEXT: bic v0.4h, #255, lsl #8
-; CHECK-NEXT: bic v1.4h, #255, lsl #8
-; CHECK-NEXT: neg v0.4h, v0.4h
-; CHECK-NEXT: ushl v0.4h, v1.4h, v0.4h
-; CHECK-NEXT: umov w0, v0.h[0]
-; CHECK-NEXT: umov w1, v0.h[1]
-; CHECK-NEXT: umov w2, v0.h[2]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: lshr_v3i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov s0, w3
+; CHECK-SD-NEXT: fmov s1, w0
+; CHECK-SD-NEXT: mov v0.h[1], w4
+; CHECK-SD-NEXT: mov v1.h[1], w1
+; CHECK-SD-NEXT: mov v0.h[2], w5
+; CHECK-SD-NEXT: mov v1.h[2], w2
+; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-SD-NEXT: bic v1.4h, #255, lsl #8
+; CHECK-SD-NEXT: neg v0.4h, v0.4h
+; CHECK-SD-NEXT: ushl v0.4h, v1.4h, v0.4h
+; CHECK-SD-NEXT: umov w0, v0.h[0]
+; CHECK-SD-NEXT: umov w1, v0.h[1]
+; CHECK-SD-NEXT: umov w2, v0.h[2]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: lshr_v3i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov s0, w3
+; CHECK-GI-NEXT: fmov s1, w4
+; CHECK-GI-NEXT: fmov s2, w1
+; CHECK-GI-NEXT: mov v0.b[1], v1.b[0]
+; CHECK-GI-NEXT: fmov s1, w0
+; CHECK-GI-NEXT: mov v1.b[1], v2.b[0]
+; CHECK-GI-NEXT: fmov s2, w5
+; CHECK-GI-NEXT: mov v0.b[2], v2.b[0]
+; CHECK-GI-NEXT: fmov s2, w2
+; CHECK-GI-NEXT: mov v1.b[2], v2.b[0]
+; CHECK-GI-NEXT: mov v0.b[3], v0.b[0]
+; CHECK-GI-NEXT: mov v1.b[3], v0.b[0]
+; CHECK-GI-NEXT: mov v0.b[4], v0.b[0]
+; CHECK-GI-NEXT: mov v1.b[4], v0.b[0]
+; CHECK-GI-NEXT: mov v0.b[5], v0.b[0]
+; CHECK-GI-NEXT: mov v1.b[5], v0.b[0]
+; CHECK-GI-NEXT: mov v0.b[6], v0.b[0]
+; CHECK-GI-NEXT: mov v1.b[6], v0.b[0]
+; CHECK-GI-NEXT: mov v0.b[7], v0.b[0]
+; CHECK-GI-NEXT: mov v1.b[7], v0.b[0]
+; CHECK-GI-NEXT: neg v0.8b, v0.8b
+; CHECK-GI-NEXT: ushl v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: umov w0, v0.b[0]
+; CHECK-GI-NEXT: umov w1, v0.b[1]
+; CHECK-GI-NEXT: umov w2, v0.b[2]
+; CHECK-GI-NEXT: ret
%3 = lshr <3 x i8> %0, %1
ret <3 x i8> %3
}
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