[llvm] [AArch64] Convert UADDV(add(zext, zext)) into UADDLV(concat). (PR #78301)
Rin Dobrescu via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 19 07:35:51 PST 2024
https://github.com/Rin18 updated https://github.com/llvm/llvm-project/pull/78301
>From 4fa5aeb5ac3d6f0c5ff410b60a1f2f9d144d98ab Mon Sep 17 00:00:00 2001
From: Rin Dobrescu <rin.dobrescu at arm.com>
Date: Tue, 16 Jan 2024 15:42:32 +0000
Subject: [PATCH 1/6] [AArch64] Convert UADDV(add(zext(64-bit source),
zext(64-bit source))) into UADDLV(concat).
---
.../Target/AArch64/AArch64ISelLowering.cpp | 47 +++++++-
.../AArch64/aarch64-combine-add-zext.ll | 20 ++++
llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll | 12 +-
llvm/test/CodeGen/AArch64/neon-dotreduce.ll | 53 +++++----
llvm/test/CodeGen/AArch64/vecreduce-add.ll | 110 ++++++++++++------
5 files changed, 175 insertions(+), 67 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/aarch64-combine-add-zext.ll
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index a3035bf78da27f..a9a7c2cb8605e1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16561,11 +16561,14 @@ static SDValue performVecReduceAddCombine(SDNode *N, SelectionDAG &DAG,
VecReudceAdd8);
}
-// Given an (integer) vecreduce, we know the order of the inputs does not
-// matter. We can convert UADDV(add(zext(extract_lo(x)), zext(extract_hi(x))))
-// into UADDV(UADDLP(x)). This can also happen through an extra add, where we
-// transform UADDV(add(y, add(zext(extract_lo(x)), zext(extract_hi(x))))).
+// Turn UADDV(add(zext(extract_lo(x)), zext(extract_hi(x)))) into
+// UADDV(UADDLP(x)). If that fails, then convert UADDV(add(zext(64-bit source),
+// zext(64-bit source))) into UADDLV(concat).
static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) {
+ // Given an (integer) vecreduce, we know the order of the inputs does not
+ // matter. We can convert UADDV(add(zext(extract_lo(x)), zext(extract_hi(x))))
+ // into UADDV(UADDLP(x)). This can also happen through an extra add, where we
+ // transform UADDV(add(y, add(zext(extract_lo(x)), zext(extract_hi(x))))).
auto DetectAddExtract = [&](SDValue A) {
// Look for add(zext(extract_lo(x)), zext(extract_hi(x))), returning
// UADDLP(x) if found.
@@ -16599,6 +16602,34 @@ static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) {
return DAG.getNode(Opcode, SDLoc(A), VT, Ext0.getOperand(0));
};
+ // We can convert a UADDV(add(zext(64-bit source), zext(64-bit source))) into
+ // UADDLV(concat), where the concat represents the 64-bit zext sources.
+ auto DetectZextConcat = [&](SDValue A, SelectionDAG &DAG) {
+ // Look for add(zext(64-bit source), zext(64-bit source)), returning
+ // UADDLV(concat(zext, zext)) if found.
+ if (A.getOpcode() != ISD::ADD)
+ return SDValue();
+ EVT VT = A.getValueType();
+ if (VT != MVT::v4i32)
+ return SDValue();
+ SDValue Op0 = A.getOperand(0);
+ SDValue Op1 = A.getOperand(1);
+ if (Op0.getOpcode() != ISD::ZERO_EXTEND)
+ return SDValue();
+ SDValue Ext0 = Op0.getOperand(0);
+ SDValue Ext1 = Op1.getOperand(0);
+ EVT ExtVT0 = Ext0.getValueType();
+ EVT ExtVT1 = Ext1.getValueType();
+ // Check zext VTs are the same and 64-bit length.
+ if (ExtVT0 != ExtVT1 || !(ExtVT0 == MVT::v8i8 || ExtVT0 == MVT::v4i16))
+ return SDValue();
+ // Get VT for concat of zext sources.
+ EVT PairVT = ExtVT0.getDoubleNumVectorElementsVT(*DAG.getContext());
+ SDValue Concat =
+ DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(A), PairVT, Ext0, Ext1);
+ return DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), MVT::v4i32, Concat);
+ };
+
if (SDValue R = DetectAddExtract(A))
return R;
@@ -16610,6 +16641,10 @@ static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) {
if (SDValue R = performUADDVAddCombine(A.getOperand(1), DAG))
return DAG.getNode(ISD::ADD, SDLoc(A), A.getValueType(), R,
A.getOperand(0));
+
+ if (SDValue R = DetectZextConcat(A, DAG))
+ return R;
+
return SDValue();
}
@@ -16617,7 +16652,9 @@ static SDValue performUADDVCombine(SDNode *N, SelectionDAG &DAG) {
SDValue A = N->getOperand(0);
if (A.getOpcode() == ISD::ADD)
if (SDValue R = performUADDVAddCombine(A, DAG))
- return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), R);
+ return R.getOpcode() == AArch64ISD::UADDLV
+ ? R
+ : DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), R);
return SDValue();
}
diff --git a/llvm/test/CodeGen/AArch64/aarch64-combine-add-zext.ll b/llvm/test/CodeGen/AArch64/aarch64-combine-add-zext.ll
new file mode 100644
index 00000000000000..1cb0206c3fdbc1
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/aarch64-combine-add-zext.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+
+define i32 @test_add_zext(<4 x i16> %a, <4 x i16> %b) local_unnamed_addr #0 {
+; CHECK-LABEL: test_add_zext:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: uaddlv s0, v0.8h
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
+ %z1 = zext <4 x i16> %a to <4 x i32>
+ %z2 = zext <4 x i16> %b to <4 x i32>
+ %z = add <4 x i32> %z1, %z2
+ %r = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %z)
+ ret i32 %r
+}
+
+declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
diff --git a/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll b/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll
index 1fc177f034975d..24cce9a2b26b58 100644
--- a/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll
+++ b/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll
@@ -18,14 +18,14 @@ define i32 @lower_lshr(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <
; CHECK-NEXT: mov v4.s[2], v6.s[0]
; CHECK-NEXT: mov v0.s[3], v1.s[0]
; CHECK-NEXT: mov v4.s[3], v3.s[0]
-; CHECK-NEXT: xtn v2.4h, v0.4s
+; CHECK-NEXT: xtn v1.4h, v0.4s
; CHECK-NEXT: shrn v0.4h, v0.4s, #16
-; CHECK-NEXT: xtn v1.4h, v4.4s
+; CHECK-NEXT: xtn v2.4h, v4.4s
; CHECK-NEXT: shrn v3.4h, v4.4s, #16
-; CHECK-NEXT: uhadd v0.4h, v2.4h, v0.4h
-; CHECK-NEXT: uhadd v1.4h, v1.4h, v3.4h
-; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: addv s0, v0.4s
+; CHECK-NEXT: uhadd v0.4h, v1.4h, v0.4h
+; CHECK-NEXT: uhadd v1.4h, v2.4h, v3.4h
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: uaddlv s0, v0.8h
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
%l87 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)
diff --git a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
index 706aa4ad1b4665..e4767594851eae 100644
--- a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+++ b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
@@ -1039,17 +1039,21 @@ define i32 @test_udot_v25i8_nomla(ptr nocapture readonly %a1) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldp q2, q1, [x0]
; CHECK-NEXT: movi v0.2d, #0000000000000000
-; CHECK-NEXT: ushll v3.8h, v1.8b, #0
-; CHECK-NEXT: ushll v4.8h, v2.8b, #0
+; CHECK-NEXT: ushll v3.8h, v2.8b, #0
+; CHECK-NEXT: ushll v4.8h, v1.8b, #0
; CHECK-NEXT: ushll2 v1.8h, v1.16b, #0
-; CHECK-NEXT: ushll2 v2.8h, v2.16b, #0
-; CHECK-NEXT: uaddl2 v5.4s, v4.8h, v3.8h
+; CHECK-NEXT: ext v5.16b, v3.16b, v3.16b, #8
+; CHECK-NEXT: ext v6.16b, v4.16b, v4.16b, #8
; CHECK-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-NEXT: uaddl v3.4s, v4.4h, v3.4h
+; CHECK-NEXT: mov v3.d[1], v4.d[0]
; CHECK-NEXT: mov v0.s[0], v1.s[0]
-; CHECK-NEXT: uaddw2 v1.4s, v5.4s, v2.8h
-; CHECK-NEXT: uaddw v0.4s, v0.4s, v2.4h
-; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
+; CHECK-NEXT: ushll2 v1.8h, v2.16b, #0
+; CHECK-NEXT: mov v5.d[1], v6.d[0]
+; CHECK-NEXT: uaddlv s2, v3.8h
+; CHECK-NEXT: uaddw v0.4s, v0.4s, v1.4h
+; CHECK-NEXT: uaddlv s3, v5.8h
+; CHECK-NEXT: add v0.4s, v2.4s, v0.4s
+; CHECK-NEXT: uaddw2 v1.4s, v3.4s, v1.8h
; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-NEXT: addv s0, v0.4s
; CHECK-NEXT: fmov w0, s0
@@ -1631,23 +1635,30 @@ define i32 @test_udot_v33i8_nomla(ptr nocapture readonly %a1) {
; CHECK-LABEL: test_udot_v33i8_nomla:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b1, [x0, #32]
-; CHECK-NEXT: ldp q3, q2, [x0]
+; CHECK-NEXT: ldp q2, q3, [x0]
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
-; CHECK-NEXT: ushll v4.8h, v2.8b, #0
-; CHECK-NEXT: ushll v5.8h, v3.8b, #0
-; CHECK-NEXT: ushll2 v2.8h, v2.16b, #0
-; CHECK-NEXT: ushll2 v3.8h, v3.16b, #0
+; CHECK-NEXT: ushll2 v4.8h, v2.16b, #0
+; CHECK-NEXT: ushll2 v5.8h, v3.16b, #0
+; CHECK-NEXT: ushll v3.8h, v3.8b, #0
+; CHECK-NEXT: ushll v2.8h, v2.8b, #0
; CHECK-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-NEXT: uaddl2 v6.4s, v3.8h, v2.8h
-; CHECK-NEXT: uaddl v2.4s, v3.4h, v2.4h
+; CHECK-NEXT: ext v6.16b, v4.16b, v4.16b, #8
+; CHECK-NEXT: ext v7.16b, v5.16b, v5.16b, #8
+; CHECK-NEXT: mov v4.d[1], v5.d[0]
+; CHECK-NEXT: ext v16.16b, v2.16b, v2.16b, #8
; CHECK-NEXT: mov v0.s[0], v1.s[0]
-; CHECK-NEXT: uaddl2 v1.4s, v5.8h, v4.8h
-; CHECK-NEXT: add v1.4s, v1.4s, v6.4s
-; CHECK-NEXT: uaddw v0.4s, v0.4s, v5.4h
-; CHECK-NEXT: uaddw v0.4s, v0.4s, v4.4h
-; CHECK-NEXT: add v1.4s, v2.4s, v1.4s
-; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ext v1.16b, v3.16b, v3.16b, #8
+; CHECK-NEXT: mov v6.d[1], v7.d[0]
+; CHECK-NEXT: uaddlv s4, v4.8h
+; CHECK-NEXT: mov v16.d[1], v1.d[0]
+; CHECK-NEXT: uaddw v0.4s, v0.4s, v2.4h
+; CHECK-NEXT: uaddlv s1, v6.8h
+; CHECK-NEXT: uaddlv s2, v16.8h
+; CHECK-NEXT: uaddw v0.4s, v0.4s, v3.4h
+; CHECK-NEXT: add v1.4s, v1.4s, v2.4s
+; CHECK-NEXT: add v0.4s, v4.4s, v0.4s
+; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-NEXT: addv s0, v0.4s
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-add.ll b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
index 0b43e3b695a396..173b8e5470cf3f 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-add.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
@@ -306,11 +306,15 @@ entry:
define i32 @add_v16i8_v16i32_zext(<16 x i8> %x) {
; CHECK-SD-BASE-LABEL: add_v16i8_v16i32_zext:
; CHECK-SD-BASE: // %bb.0: // %entry
-; CHECK-SD-BASE-NEXT: ushll2 v1.8h, v0.16b, #0
-; CHECK-SD-BASE-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-SD-BASE-NEXT: uaddl2 v2.4s, v0.8h, v1.8h
-; CHECK-SD-BASE-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v2.4s
+; CHECK-SD-BASE-NEXT: ushll v1.8h, v0.8b, #0
+; CHECK-SD-BASE-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-SD-BASE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-SD-BASE-NEXT: ext v3.16b, v0.16b, v0.16b, #8
+; CHECK-SD-BASE-NEXT: mov v1.d[1], v0.d[0]
+; CHECK-SD-BASE-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-SD-BASE-NEXT: uaddlv s0, v1.8h
+; CHECK-SD-BASE-NEXT: uaddlv s1, v2.8h
+; CHECK-SD-BASE-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-SD-BASE-NEXT: addv s0, v0.4s
; CHECK-SD-BASE-NEXT: fmov w0, s0
; CHECK-SD-BASE-NEXT: ret
@@ -1131,11 +1135,15 @@ entry:
define i32 @add_v16i8_v16i32_acc_zext(<16 x i8> %x, i32 %a) {
; CHECK-SD-BASE-LABEL: add_v16i8_v16i32_acc_zext:
; CHECK-SD-BASE: // %bb.0: // %entry
-; CHECK-SD-BASE-NEXT: ushll2 v1.8h, v0.16b, #0
-; CHECK-SD-BASE-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-SD-BASE-NEXT: uaddl2 v2.4s, v0.8h, v1.8h
-; CHECK-SD-BASE-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v2.4s
+; CHECK-SD-BASE-NEXT: ushll v1.8h, v0.8b, #0
+; CHECK-SD-BASE-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-SD-BASE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-SD-BASE-NEXT: ext v3.16b, v0.16b, v0.16b, #8
+; CHECK-SD-BASE-NEXT: mov v1.d[1], v0.d[0]
+; CHECK-SD-BASE-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-SD-BASE-NEXT: uaddlv s0, v1.8h
+; CHECK-SD-BASE-NEXT: uaddlv s1, v2.8h
+; CHECK-SD-BASE-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-SD-BASE-NEXT: addv s0, v0.4s
; CHECK-SD-BASE-NEXT: fmov w8, s0
; CHECK-SD-BASE-NEXT: add w0, w8, w0
@@ -1887,21 +1895,45 @@ entry:
}
define i32 @add_pair_v4i16_v4i32_zext(<4 x i16> %x, <4 x i16> %y) {
-; CHECK-SD-LABEL: add_pair_v4i16_v4i32_zext:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-SD-NEXT: addv s0, v0.4s
-; CHECK-SD-NEXT: fmov w0, s0
-; CHECK-SD-NEXT: ret
+; CHECK-SD-BASE-LABEL: add_pair_v4i16_v4i32_zext:
+; CHECK-SD-BASE: // %bb.0: // %entry
+; CHECK-SD-BASE-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-BASE-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-BASE-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-BASE-NEXT: uaddlv s0, v0.8h
+; CHECK-SD-BASE-NEXT: fmov w0, s0
+; CHECK-SD-BASE-NEXT: ret
;
-; CHECK-GI-LABEL: add_pair_v4i16_v4i32_zext:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: uaddlv s0, v0.4h
-; CHECK-GI-NEXT: uaddlv s1, v1.4h
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: fmov w9, s1
-; CHECK-GI-NEXT: add w0, w8, w9
-; CHECK-GI-NEXT: ret
+; CHECK-SD-DOT-LABEL: add_pair_v4i16_v4i32_zext:
+; CHECK-SD-DOT: // %bb.0: // %entry
+; CHECK-SD-DOT-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-DOT-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-DOT-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-DOT-NEXT: uaddlv s0, v0.8h
+; CHECK-SD-DOT-NEXT: fmov w0, s0
+; CHECK-SD-DOT-NEXT: ret
+;
+; CHECK-GI-BASE-LABEL: add_pair_v4i16_v4i32_zext:
+; CHECK-GI-BASE: // %bb.0: // %entry
+; CHECK-GI-BASE-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-GI-BASE-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-GI-BASE-NEXT: addv s0, v0.4s
+; CHECK-GI-BASE-NEXT: addv s1, v1.4s
+; CHECK-GI-BASE-NEXT: fmov w8, s0
+; CHECK-GI-BASE-NEXT: fmov w9, s1
+; CHECK-GI-BASE-NEXT: add w0, w8, w9
+; CHECK-GI-BASE-NEXT: ret
+;
+; CHECK-GI-DOT-LABEL: add_pair_v4i16_v4i32_zext:
+; CHECK-GI-DOT: // %bb.0: // %entry
+; CHECK-GI-DOT-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-GI-DOT-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-GI-DOT-NEXT: addv s0, v0.4s
+; CHECK-GI-DOT-NEXT: addv s1, v1.4s
+; CHECK-GI-DOT-NEXT: fmov w8, s0
+; CHECK-GI-DOT-NEXT: fmov w9, s1
+; CHECK-GI-DOT-NEXT: add w0, w8, w9
+; CHECK-GI-DOT-NEXT: ret
entry:
%xx = zext <4 x i16> %x to <4 x i32>
%z1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
@@ -3364,17 +3396,25 @@ entry:
define i32 @add_pair_v16i8_v16i32_zext(<16 x i8> %x, <16 x i8> %y) {
; CHECK-SD-BASE-LABEL: add_pair_v16i8_v16i32_zext:
; CHECK-SD-BASE: // %bb.0: // %entry
-; CHECK-SD-BASE-NEXT: ushll2 v2.8h, v0.16b, #0
-; CHECK-SD-BASE-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-SD-BASE-NEXT: ushll2 v3.8h, v1.16b, #0
-; CHECK-SD-BASE-NEXT: ushll v1.8h, v1.8b, #0
-; CHECK-SD-BASE-NEXT: uaddl2 v4.4s, v0.8h, v2.8h
-; CHECK-SD-BASE-NEXT: uaddl v0.4s, v0.4h, v2.4h
-; CHECK-SD-BASE-NEXT: uaddl2 v2.4s, v1.8h, v3.8h
-; CHECK-SD-BASE-NEXT: uaddl v1.4s, v1.4h, v3.4h
-; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v4.4s
-; CHECK-SD-BASE-NEXT: add v1.4s, v1.4s, v2.4s
-; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-SD-BASE-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-SD-BASE-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-SD-BASE-NEXT: ushll v3.8h, v1.8b, #0
+; CHECK-SD-BASE-NEXT: ushll2 v1.8h, v1.16b, #0
+; CHECK-SD-BASE-NEXT: ext v4.16b, v2.16b, v2.16b, #8
+; CHECK-SD-BASE-NEXT: ext v5.16b, v0.16b, v0.16b, #8
+; CHECK-SD-BASE-NEXT: ext v6.16b, v3.16b, v3.16b, #8
+; CHECK-SD-BASE-NEXT: ext v7.16b, v1.16b, v1.16b, #8
+; CHECK-SD-BASE-NEXT: mov v2.d[1], v0.d[0]
+; CHECK-SD-BASE-NEXT: mov v3.d[1], v1.d[0]
+; CHECK-SD-BASE-NEXT: mov v4.d[1], v5.d[0]
+; CHECK-SD-BASE-NEXT: mov v6.d[1], v7.d[0]
+; CHECK-SD-BASE-NEXT: uaddlv s0, v2.8h
+; CHECK-SD-BASE-NEXT: uaddlv s2, v3.8h
+; CHECK-SD-BASE-NEXT: uaddlv s1, v4.8h
+; CHECK-SD-BASE-NEXT: uaddlv s3, v6.8h
+; CHECK-SD-BASE-NEXT: add v0.4s, v1.4s, v0.4s
+; CHECK-SD-BASE-NEXT: add v1.4s, v3.4s, v2.4s
+; CHECK-SD-BASE-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-SD-BASE-NEXT: addv s0, v0.4s
; CHECK-SD-BASE-NEXT: fmov w0, s0
; CHECK-SD-BASE-NEXT: ret
>From 0bd61c6d8703352805261b4b32a4953e8dff315f Mon Sep 17 00:00:00 2001
From: Rin Dobrescu <rin.dobrescu at arm.com>
Date: Wed, 17 Jan 2024 12:14:53 +0000
Subject: [PATCH 2/6] Move combine function and check for same Opcode
---
.../Target/AArch64/AArch64ISelLowering.cpp | 80 +++---
llvm/test/CodeGen/AArch64/neon-dotreduce.ll | 53 ++--
llvm/test/CodeGen/AArch64/vecreduce-add.ll | 239 +++++++-----------
3 files changed, 152 insertions(+), 220 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index a9a7c2cb8605e1..fedd50dd163e9b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16561,14 +16561,11 @@ static SDValue performVecReduceAddCombine(SDNode *N, SelectionDAG &DAG,
VecReudceAdd8);
}
-// Turn UADDV(add(zext(extract_lo(x)), zext(extract_hi(x)))) into
-// UADDV(UADDLP(x)). If that fails, then convert UADDV(add(zext(64-bit source),
-// zext(64-bit source))) into UADDLV(concat).
+// Given an (integer) vecreduce, we know the order of the inputs does not
+// matter. We can convert UADDV(add(zext(extract_lo(x)), zext(extract_hi(x))))
+// into UADDV(UADDLP(x)). This can also happen through an extra add, where we
+// transform UADDV(add(y, add(zext(extract_lo(x)), zext(extract_hi(x))))).
static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) {
- // Given an (integer) vecreduce, we know the order of the inputs does not
- // matter. We can convert UADDV(add(zext(extract_lo(x)), zext(extract_hi(x))))
- // into UADDV(UADDLP(x)). This can also happen through an extra add, where we
- // transform UADDV(add(y, add(zext(extract_lo(x)), zext(extract_hi(x))))).
auto DetectAddExtract = [&](SDValue A) {
// Look for add(zext(extract_lo(x)), zext(extract_hi(x))), returning
// UADDLP(x) if found.
@@ -16602,34 +16599,6 @@ static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) {
return DAG.getNode(Opcode, SDLoc(A), VT, Ext0.getOperand(0));
};
- // We can convert a UADDV(add(zext(64-bit source), zext(64-bit source))) into
- // UADDLV(concat), where the concat represents the 64-bit zext sources.
- auto DetectZextConcat = [&](SDValue A, SelectionDAG &DAG) {
- // Look for add(zext(64-bit source), zext(64-bit source)), returning
- // UADDLV(concat(zext, zext)) if found.
- if (A.getOpcode() != ISD::ADD)
- return SDValue();
- EVT VT = A.getValueType();
- if (VT != MVT::v4i32)
- return SDValue();
- SDValue Op0 = A.getOperand(0);
- SDValue Op1 = A.getOperand(1);
- if (Op0.getOpcode() != ISD::ZERO_EXTEND)
- return SDValue();
- SDValue Ext0 = Op0.getOperand(0);
- SDValue Ext1 = Op1.getOperand(0);
- EVT ExtVT0 = Ext0.getValueType();
- EVT ExtVT1 = Ext1.getValueType();
- // Check zext VTs are the same and 64-bit length.
- if (ExtVT0 != ExtVT1 || !(ExtVT0 == MVT::v8i8 || ExtVT0 == MVT::v4i16))
- return SDValue();
- // Get VT for concat of zext sources.
- EVT PairVT = ExtVT0.getDoubleNumVectorElementsVT(*DAG.getContext());
- SDValue Concat =
- DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(A), PairVT, Ext0, Ext1);
- return DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), MVT::v4i32, Concat);
- };
-
if (SDValue R = DetectAddExtract(A))
return R;
@@ -16641,20 +16610,45 @@ static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) {
if (SDValue R = performUADDVAddCombine(A.getOperand(1), DAG))
return DAG.getNode(ISD::ADD, SDLoc(A), A.getValueType(), R,
A.getOperand(0));
-
- if (SDValue R = DetectZextConcat(A, DAG))
- return R;
-
return SDValue();
}
+// We can convert a UADDV(add(zext(64-bit source), zext(64-bit source))) into
+// UADDLV(concat), where the concat represents the 64-bit zext sources.
+static SDValue performUADDVZextCombine(SDValue A, SelectionDAG &DAG) {
+ // Look for add(zext(64-bit source), zext(64-bit source)), returning
+ // UADDLV(concat(zext, zext)) if found.
+ if (A.getOpcode() != ISD::ADD)
+ return SDValue();
+ EVT VT = A.getValueType();
+ if (VT != MVT::v4i32)
+ return SDValue();
+ SDValue Op0 = A.getOperand(0);
+ SDValue Op1 = A.getOperand(1);
+ if (Op0.getOpcode() != ISD::ZERO_EXTEND || Op0.getOpcode() != Op1.getOpcode())
+ return SDValue();
+ SDValue Ext0 = Op0.getOperand(0);
+ SDValue Ext1 = Op1.getOperand(0);
+ EVT ExtVT0 = Ext0.getValueType();
+ EVT ExtVT1 = Ext1.getValueType();
+ // Check zext VTs are the same and 64-bit length.
+ if (ExtVT0 != ExtVT1 || !(ExtVT0 == MVT::v8i8 || ExtVT0 == MVT::v4i16))
+ return SDValue();
+ // Get VT for concat of zext sources.
+ EVT PairVT = ExtVT0.getDoubleNumVectorElementsVT(*DAG.getContext());
+ SDValue Concat =
+ DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(A), PairVT, Ext0, Ext1);
+ return DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), MVT::v4i32, Concat);
+}
+
static SDValue performUADDVCombine(SDNode *N, SelectionDAG &DAG) {
SDValue A = N->getOperand(0);
- if (A.getOpcode() == ISD::ADD)
+ if (A.getOpcode() == ISD::ADD) {
if (SDValue R = performUADDVAddCombine(A, DAG))
- return R.getOpcode() == AArch64ISD::UADDLV
- ? R
- : DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), R);
+ return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), R);
+ else if (SDValue R = performUADDVZextCombine(A, DAG))
+ return R;
+ }
return SDValue();
}
diff --git a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
index e4767594851eae..706aa4ad1b4665 100644
--- a/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+++ b/llvm/test/CodeGen/AArch64/neon-dotreduce.ll
@@ -1039,21 +1039,17 @@ define i32 @test_udot_v25i8_nomla(ptr nocapture readonly %a1) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldp q2, q1, [x0]
; CHECK-NEXT: movi v0.2d, #0000000000000000
-; CHECK-NEXT: ushll v3.8h, v2.8b, #0
-; CHECK-NEXT: ushll v4.8h, v1.8b, #0
+; CHECK-NEXT: ushll v3.8h, v1.8b, #0
+; CHECK-NEXT: ushll v4.8h, v2.8b, #0
; CHECK-NEXT: ushll2 v1.8h, v1.16b, #0
-; CHECK-NEXT: ext v5.16b, v3.16b, v3.16b, #8
-; CHECK-NEXT: ext v6.16b, v4.16b, v4.16b, #8
+; CHECK-NEXT: ushll2 v2.8h, v2.16b, #0
+; CHECK-NEXT: uaddl2 v5.4s, v4.8h, v3.8h
; CHECK-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-NEXT: uaddl v3.4s, v4.4h, v3.4h
; CHECK-NEXT: mov v0.s[0], v1.s[0]
-; CHECK-NEXT: ushll2 v1.8h, v2.16b, #0
-; CHECK-NEXT: mov v5.d[1], v6.d[0]
-; CHECK-NEXT: uaddlv s2, v3.8h
-; CHECK-NEXT: uaddw v0.4s, v0.4s, v1.4h
-; CHECK-NEXT: uaddlv s3, v5.8h
-; CHECK-NEXT: add v0.4s, v2.4s, v0.4s
-; CHECK-NEXT: uaddw2 v1.4s, v3.4s, v1.8h
+; CHECK-NEXT: uaddw2 v1.4s, v5.4s, v2.8h
+; CHECK-NEXT: uaddw v0.4s, v0.4s, v2.4h
+; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-NEXT: addv s0, v0.4s
; CHECK-NEXT: fmov w0, s0
@@ -1635,30 +1631,23 @@ define i32 @test_udot_v33i8_nomla(ptr nocapture readonly %a1) {
; CHECK-LABEL: test_udot_v33i8_nomla:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b1, [x0, #32]
-; CHECK-NEXT: ldp q2, q3, [x0]
+; CHECK-NEXT: ldp q3, q2, [x0]
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
-; CHECK-NEXT: ushll2 v4.8h, v2.16b, #0
-; CHECK-NEXT: ushll2 v5.8h, v3.16b, #0
-; CHECK-NEXT: ushll v3.8h, v3.8b, #0
-; CHECK-NEXT: ushll v2.8h, v2.8b, #0
+; CHECK-NEXT: ushll v4.8h, v2.8b, #0
+; CHECK-NEXT: ushll v5.8h, v3.8b, #0
+; CHECK-NEXT: ushll2 v2.8h, v2.16b, #0
+; CHECK-NEXT: ushll2 v3.8h, v3.16b, #0
; CHECK-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-NEXT: ext v6.16b, v4.16b, v4.16b, #8
-; CHECK-NEXT: ext v7.16b, v5.16b, v5.16b, #8
-; CHECK-NEXT: mov v4.d[1], v5.d[0]
-; CHECK-NEXT: ext v16.16b, v2.16b, v2.16b, #8
+; CHECK-NEXT: uaddl2 v6.4s, v3.8h, v2.8h
+; CHECK-NEXT: uaddl v2.4s, v3.4h, v2.4h
; CHECK-NEXT: mov v0.s[0], v1.s[0]
-; CHECK-NEXT: ext v1.16b, v3.16b, v3.16b, #8
-; CHECK-NEXT: mov v6.d[1], v7.d[0]
-; CHECK-NEXT: uaddlv s4, v4.8h
-; CHECK-NEXT: mov v16.d[1], v1.d[0]
-; CHECK-NEXT: uaddw v0.4s, v0.4s, v2.4h
-; CHECK-NEXT: uaddlv s1, v6.8h
-; CHECK-NEXT: uaddlv s2, v16.8h
-; CHECK-NEXT: uaddw v0.4s, v0.4s, v3.4h
-; CHECK-NEXT: add v1.4s, v1.4s, v2.4s
-; CHECK-NEXT: add v0.4s, v4.4s, v0.4s
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: uaddl2 v1.4s, v5.8h, v4.8h
+; CHECK-NEXT: add v1.4s, v1.4s, v6.4s
+; CHECK-NEXT: uaddw v0.4s, v0.4s, v5.4h
+; CHECK-NEXT: uaddw v0.4s, v0.4s, v4.4h
+; CHECK-NEXT: add v1.4s, v2.4s, v1.4s
+; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: addv s0, v0.4s
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-add.ll b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
index 173b8e5470cf3f..6badebc62e68a1 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-add.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
@@ -306,15 +306,11 @@ entry:
define i32 @add_v16i8_v16i32_zext(<16 x i8> %x) {
; CHECK-SD-BASE-LABEL: add_v16i8_v16i32_zext:
; CHECK-SD-BASE: // %bb.0: // %entry
-; CHECK-SD-BASE-NEXT: ushll v1.8h, v0.8b, #0
-; CHECK-SD-BASE-NEXT: ushll2 v0.8h, v0.16b, #0
-; CHECK-SD-BASE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-SD-BASE-NEXT: ext v3.16b, v0.16b, v0.16b, #8
-; CHECK-SD-BASE-NEXT: mov v1.d[1], v0.d[0]
-; CHECK-SD-BASE-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-SD-BASE-NEXT: uaddlv s0, v1.8h
-; CHECK-SD-BASE-NEXT: uaddlv s1, v2.8h
-; CHECK-SD-BASE-NEXT: add v0.4s, v1.4s, v0.4s
+; CHECK-SD-BASE-NEXT: ushll2 v1.8h, v0.16b, #0
+; CHECK-SD-BASE-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-SD-BASE-NEXT: uaddl2 v2.4s, v0.8h, v1.8h
+; CHECK-SD-BASE-NEXT: uaddl v0.4s, v0.4h, v1.4h
+; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v2.4s
; CHECK-SD-BASE-NEXT: addv s0, v0.4s
; CHECK-SD-BASE-NEXT: fmov w0, s0
; CHECK-SD-BASE-NEXT: ret
@@ -1135,15 +1131,11 @@ entry:
define i32 @add_v16i8_v16i32_acc_zext(<16 x i8> %x, i32 %a) {
; CHECK-SD-BASE-LABEL: add_v16i8_v16i32_acc_zext:
; CHECK-SD-BASE: // %bb.0: // %entry
-; CHECK-SD-BASE-NEXT: ushll v1.8h, v0.8b, #0
-; CHECK-SD-BASE-NEXT: ushll2 v0.8h, v0.16b, #0
-; CHECK-SD-BASE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-SD-BASE-NEXT: ext v3.16b, v0.16b, v0.16b, #8
-; CHECK-SD-BASE-NEXT: mov v1.d[1], v0.d[0]
-; CHECK-SD-BASE-NEXT: mov v2.d[1], v3.d[0]
-; CHECK-SD-BASE-NEXT: uaddlv s0, v1.8h
-; CHECK-SD-BASE-NEXT: uaddlv s1, v2.8h
-; CHECK-SD-BASE-NEXT: add v0.4s, v1.4s, v0.4s
+; CHECK-SD-BASE-NEXT: ushll2 v1.8h, v0.16b, #0
+; CHECK-SD-BASE-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-SD-BASE-NEXT: uaddl2 v2.4s, v0.8h, v1.8h
+; CHECK-SD-BASE-NEXT: uaddl v0.4s, v0.4h, v1.4h
+; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v2.4s
; CHECK-SD-BASE-NEXT: addv s0, v0.4s
; CHECK-SD-BASE-NEXT: fmov w8, s0
; CHECK-SD-BASE-NEXT: add w0, w8, w0
@@ -1442,37 +1434,21 @@ entry:
}
define zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, i8 %a) {
-; CHECK-SD-BASE-LABEL: add_v16i8_v16i8_acc:
-; CHECK-SD-BASE: // %bb.0: // %entry
-; CHECK-SD-BASE-NEXT: addv b0, v0.16b
-; CHECK-SD-BASE-NEXT: fmov w8, s0
-; CHECK-SD-BASE-NEXT: add w8, w8, w0
-; CHECK-SD-BASE-NEXT: and w0, w8, #0xff
-; CHECK-SD-BASE-NEXT: ret
-;
-; CHECK-SD-DOT-LABEL: add_v16i8_v16i8_acc:
-; CHECK-SD-DOT: // %bb.0: // %entry
-; CHECK-SD-DOT-NEXT: addv b0, v0.16b
-; CHECK-SD-DOT-NEXT: fmov w8, s0
-; CHECK-SD-DOT-NEXT: add w8, w8, w0
-; CHECK-SD-DOT-NEXT: and w0, w8, #0xff
-; CHECK-SD-DOT-NEXT: ret
-;
-; CHECK-GI-BASE-LABEL: add_v16i8_v16i8_acc:
-; CHECK-GI-BASE: // %bb.0: // %entry
-; CHECK-GI-BASE-NEXT: addv b0, v0.16b
-; CHECK-GI-BASE-NEXT: fmov w8, s0
-; CHECK-GI-BASE-NEXT: add w8, w0, w8, uxtb
-; CHECK-GI-BASE-NEXT: and w0, w8, #0xff
-; CHECK-GI-BASE-NEXT: ret
+; CHECK-SD-LABEL: add_v16i8_v16i8_acc:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: addv b0, v0.16b
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: add w8, w8, w0
+; CHECK-SD-NEXT: and w0, w8, #0xff
+; CHECK-SD-NEXT: ret
;
-; CHECK-GI-DOT-LABEL: add_v16i8_v16i8_acc:
-; CHECK-GI-DOT: // %bb.0: // %entry
-; CHECK-GI-DOT-NEXT: addv b0, v0.16b
-; CHECK-GI-DOT-NEXT: fmov w8, s0
-; CHECK-GI-DOT-NEXT: add w8, w0, w8, uxtb
-; CHECK-GI-DOT-NEXT: and w0, w8, #0xff
-; CHECK-GI-DOT-NEXT: ret
+; CHECK-GI-LABEL: add_v16i8_v16i8_acc:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addv b0, v0.16b
+; CHECK-GI-NEXT: fmov w8, s0
+; CHECK-GI-NEXT: add w8, w0, w8, uxtb
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: ret
entry:
%z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %x)
%r = add i8 %z, %a
@@ -1895,45 +1871,23 @@ entry:
}
define i32 @add_pair_v4i16_v4i32_zext(<4 x i16> %x, <4 x i16> %y) {
-; CHECK-SD-BASE-LABEL: add_pair_v4i16_v4i32_zext:
-; CHECK-SD-BASE: // %bb.0: // %entry
-; CHECK-SD-BASE-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-BASE-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-SD-BASE-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-SD-BASE-NEXT: uaddlv s0, v0.8h
-; CHECK-SD-BASE-NEXT: fmov w0, s0
-; CHECK-SD-BASE-NEXT: ret
-;
-; CHECK-SD-DOT-LABEL: add_pair_v4i16_v4i32_zext:
-; CHECK-SD-DOT: // %bb.0: // %entry
-; CHECK-SD-DOT-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-DOT-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-SD-DOT-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-SD-DOT-NEXT: uaddlv s0, v0.8h
-; CHECK-SD-DOT-NEXT: fmov w0, s0
-; CHECK-SD-DOT-NEXT: ret
-;
-; CHECK-GI-BASE-LABEL: add_pair_v4i16_v4i32_zext:
-; CHECK-GI-BASE: // %bb.0: // %entry
-; CHECK-GI-BASE-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-BASE-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-GI-BASE-NEXT: addv s0, v0.4s
-; CHECK-GI-BASE-NEXT: addv s1, v1.4s
-; CHECK-GI-BASE-NEXT: fmov w8, s0
-; CHECK-GI-BASE-NEXT: fmov w9, s1
-; CHECK-GI-BASE-NEXT: add w0, w8, w9
-; CHECK-GI-BASE-NEXT: ret
+; CHECK-SD-LABEL: add_pair_v4i16_v4i32_zext:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: uaddlv s0, v0.8h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; CHECK-GI-DOT-LABEL: add_pair_v4i16_v4i32_zext:
-; CHECK-GI-DOT: // %bb.0: // %entry
-; CHECK-GI-DOT-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-DOT-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-GI-DOT-NEXT: addv s0, v0.4s
-; CHECK-GI-DOT-NEXT: addv s1, v1.4s
-; CHECK-GI-DOT-NEXT: fmov w8, s0
-; CHECK-GI-DOT-NEXT: fmov w9, s1
-; CHECK-GI-DOT-NEXT: add w0, w8, w9
-; CHECK-GI-DOT-NEXT: ret
+; CHECK-GI-LABEL: add_pair_v4i16_v4i32_zext:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: uaddlv s0, v0.4h
+; CHECK-GI-NEXT: uaddlv s1, v1.4h
+; CHECK-GI-NEXT: fmov w8, s0
+; CHECK-GI-NEXT: fmov w9, s1
+; CHECK-GI-NEXT: add w0, w8, w9
+; CHECK-GI-NEXT: ret
entry:
%xx = zext <4 x i16> %x to <4 x i32>
%z1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
@@ -3396,25 +3350,17 @@ entry:
define i32 @add_pair_v16i8_v16i32_zext(<16 x i8> %x, <16 x i8> %y) {
; CHECK-SD-BASE-LABEL: add_pair_v16i8_v16i32_zext:
; CHECK-SD-BASE: // %bb.0: // %entry
-; CHECK-SD-BASE-NEXT: ushll v2.8h, v0.8b, #0
-; CHECK-SD-BASE-NEXT: ushll2 v0.8h, v0.16b, #0
-; CHECK-SD-BASE-NEXT: ushll v3.8h, v1.8b, #0
-; CHECK-SD-BASE-NEXT: ushll2 v1.8h, v1.16b, #0
-; CHECK-SD-BASE-NEXT: ext v4.16b, v2.16b, v2.16b, #8
-; CHECK-SD-BASE-NEXT: ext v5.16b, v0.16b, v0.16b, #8
-; CHECK-SD-BASE-NEXT: ext v6.16b, v3.16b, v3.16b, #8
-; CHECK-SD-BASE-NEXT: ext v7.16b, v1.16b, v1.16b, #8
-; CHECK-SD-BASE-NEXT: mov v2.d[1], v0.d[0]
-; CHECK-SD-BASE-NEXT: mov v3.d[1], v1.d[0]
-; CHECK-SD-BASE-NEXT: mov v4.d[1], v5.d[0]
-; CHECK-SD-BASE-NEXT: mov v6.d[1], v7.d[0]
-; CHECK-SD-BASE-NEXT: uaddlv s0, v2.8h
-; CHECK-SD-BASE-NEXT: uaddlv s2, v3.8h
-; CHECK-SD-BASE-NEXT: uaddlv s1, v4.8h
-; CHECK-SD-BASE-NEXT: uaddlv s3, v6.8h
-; CHECK-SD-BASE-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-SD-BASE-NEXT: add v1.4s, v3.4s, v2.4s
-; CHECK-SD-BASE-NEXT: add v0.4s, v1.4s, v0.4s
+; CHECK-SD-BASE-NEXT: ushll2 v2.8h, v0.16b, #0
+; CHECK-SD-BASE-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-SD-BASE-NEXT: ushll2 v3.8h, v1.16b, #0
+; CHECK-SD-BASE-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-SD-BASE-NEXT: uaddl2 v4.4s, v0.8h, v2.8h
+; CHECK-SD-BASE-NEXT: uaddl v0.4s, v0.4h, v2.4h
+; CHECK-SD-BASE-NEXT: uaddl2 v2.4s, v1.8h, v3.8h
+; CHECK-SD-BASE-NEXT: uaddl v1.4s, v1.4h, v3.4h
+; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v4.4s
+; CHECK-SD-BASE-NEXT: add v1.4s, v1.4s, v2.4s
+; CHECK-SD-BASE-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-SD-BASE-NEXT: addv s0, v0.4s
; CHECK-SD-BASE-NEXT: fmov w0, s0
; CHECK-SD-BASE-NEXT: ret
@@ -3630,10 +3576,12 @@ entry:
define i32 @add_pair_v4i8_v4i32_zext(<4 x i8> %x, <4 x i8> %y) {
; CHECK-SD-LABEL: add_pair_v4i8_v4i32_zext:
; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
; CHECK-SD-NEXT: bic v1.4h, #255, lsl #8
-; CHECK-SD-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-SD-NEXT: addv s0, v0.4s
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: uaddlv s0, v0.8h
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
@@ -5418,33 +5366,19 @@ entry:
}
define i32 @extract_hi_lo(<8 x i16> %a) {
-; CHECK-SD-BASE-LABEL: extract_hi_lo:
-; CHECK-SD-BASE: // %bb.0: // %entry
-; CHECK-SD-BASE-NEXT: uaddlv s0, v0.8h
-; CHECK-SD-BASE-NEXT: fmov w0, s0
-; CHECK-SD-BASE-NEXT: ret
-;
-; CHECK-SD-DOT-LABEL: extract_hi_lo:
-; CHECK-SD-DOT: // %bb.0: // %entry
-; CHECK-SD-DOT-NEXT: uaddlv s0, v0.8h
-; CHECK-SD-DOT-NEXT: fmov w0, s0
-; CHECK-SD-DOT-NEXT: ret
-;
-; CHECK-GI-BASE-LABEL: extract_hi_lo:
-; CHECK-GI-BASE: // %bb.0: // %entry
-; CHECK-GI-BASE-NEXT: ushll v1.4s, v0.4h, #0
-; CHECK-GI-BASE-NEXT: uaddw2 v0.4s, v1.4s, v0.8h
-; CHECK-GI-BASE-NEXT: addv s0, v0.4s
-; CHECK-GI-BASE-NEXT: fmov w0, s0
-; CHECK-GI-BASE-NEXT: ret
+; CHECK-SD-LABEL: extract_hi_lo:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddlv s0, v0.8h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; CHECK-GI-DOT-LABEL: extract_hi_lo:
-; CHECK-GI-DOT: // %bb.0: // %entry
-; CHECK-GI-DOT-NEXT: ushll v1.4s, v0.4h, #0
-; CHECK-GI-DOT-NEXT: uaddw2 v0.4s, v1.4s, v0.8h
-; CHECK-GI-DOT-NEXT: addv s0, v0.4s
-; CHECK-GI-DOT-NEXT: fmov w0, s0
-; CHECK-GI-DOT-NEXT: ret
+; CHECK-GI-LABEL: extract_hi_lo:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0
+; CHECK-GI-NEXT: uaddw2 v0.4s, v1.4s, v0.8h
+; CHECK-GI-NEXT: addv s0, v0.4s
+; CHECK-GI-NEXT: fmov w0, s0
+; CHECK-GI-NEXT: ret
entry:
%e1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%e2 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -5456,12 +5390,20 @@ entry:
}
define i32 @extract_hi_hi(<8 x i16> %a) {
-; CHECK-LABEL: extract_hi_hi:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl2 v0.4s, v0.8h, v0.8h
-; CHECK-NEXT: addv s0, v0.4s
-; CHECK-NEXT: fmov w0, s0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extract_hi_hi:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov v0.d[1], v0.d[0]
+; CHECK-SD-NEXT: uaddlv s0, v0.8h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extract_hi_hi:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: uaddl2 v0.4s, v0.8h, v0.8h
+; CHECK-GI-NEXT: addv s0, v0.4s
+; CHECK-GI-NEXT: fmov w0, s0
+; CHECK-GI-NEXT: ret
entry:
%e2 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%z2 = zext <4 x i16> %e2 to <4 x i32>
@@ -5471,12 +5413,19 @@ entry:
}
define i32 @extract_lo_lo(<8 x i16> %a) {
-; CHECK-LABEL: extract_lo_lo:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v0.4s, v0.4h, v0.4h
-; CHECK-NEXT: addv s0, v0.4s
-; CHECK-NEXT: fmov w0, s0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: extract_lo_lo:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov v0.d[1], v0.d[0]
+; CHECK-SD-NEXT: uaddlv s0, v0.8h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: extract_lo_lo:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: uaddl v0.4s, v0.4h, v0.4h
+; CHECK-GI-NEXT: addv s0, v0.4s
+; CHECK-GI-NEXT: fmov w0, s0
+; CHECK-GI-NEXT: ret
entry:
%e1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%z1 = zext <4 x i16> %e1 to <4 x i32>
>From 29cbab322e26a656300108d7146fd86116f72caa Mon Sep 17 00:00:00 2001
From: Rin Dobrescu <rin.dobrescu at arm.com>
Date: Wed, 17 Jan 2024 15:15:26 +0000
Subject: [PATCH 3/6] Remove unnecessary change in vecreduce-add.ll
---
llvm/test/CodeGen/AArch64/vecreduce-add.ll | 44 +++++++++++++++-------
1 file changed, 30 insertions(+), 14 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-add.ll b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
index 6badebc62e68a1..38bb8b0d57a3f4 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-add.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
@@ -1434,21 +1434,37 @@ entry:
}
define zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, i8 %a) {
-; CHECK-SD-LABEL: add_v16i8_v16i8_acc:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: addv b0, v0.16b
-; CHECK-SD-NEXT: fmov w8, s0
-; CHECK-SD-NEXT: add w8, w8, w0
-; CHECK-SD-NEXT: and w0, w8, #0xff
-; CHECK-SD-NEXT: ret
+; CHECK-SD-BASE-LABEL: add_v16i8_v16i8_acc:
+; CHECK-SD-BASE: // %bb.0: // %entry
+; CHECK-SD-BASE-NEXT: addv b0, v0.16b
+; CHECK-SD-BASE-NEXT: fmov w8, s0
+; CHECK-SD-BASE-NEXT: add w8, w8, w0
+; CHECK-SD-BASE-NEXT: and w0, w8, #0xff
+; CHECK-SD-BASE-NEXT: ret
;
-; CHECK-GI-LABEL: add_v16i8_v16i8_acc:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: addv b0, v0.16b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: add w8, w0, w8, uxtb
-; CHECK-GI-NEXT: and w0, w8, #0xff
-; CHECK-GI-NEXT: ret
+; CHECK-SD-DOT-LABEL: add_v16i8_v16i8_acc:
+; CHECK-SD-DOT: // %bb.0: // %entry
+; CHECK-SD-DOT-NEXT: addv b0, v0.16b
+; CHECK-SD-DOT-NEXT: fmov w8, s0
+; CHECK-SD-DOT-NEXT: add w8, w8, w0
+; CHECK-SD-DOT-NEXT: and w0, w8, #0xff
+; CHECK-SD-DOT-NEXT: ret
+;
+; CHECK-GI-BASE-LABEL: add_v16i8_v16i8_acc:
+; CHECK-GI-BASE: // %bb.0: // %entry
+; CHECK-GI-BASE-NEXT: addv b0, v0.16b
+; CHECK-GI-BASE-NEXT: fmov w8, s0
+; CHECK-GI-BASE-NEXT: add w8, w0, w8, uxtb
+; CHECK-GI-BASE-NEXT: and w0, w8, #0xff
+; CHECK-GI-BASE-NEXT: ret
+;
+; CHECK-GI-DOT-LABEL: add_v16i8_v16i8_acc:
+; CHECK-GI-DOT: // %bb.0: // %entry
+; CHECK-GI-DOT-NEXT: addv b0, v0.16b
+; CHECK-GI-DOT-NEXT: fmov w8, s0
+; CHECK-GI-DOT-NEXT: add w8, w0, w8, uxtb
+; CHECK-GI-DOT-NEXT: and w0, w8, #0xff
+; CHECK-GI-DOT-NEXT: ret
entry:
%z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %x)
%r = add i8 %z, %a
>From 4e7e86ae622d40a71291f1fcaacb102ee948307b Mon Sep 17 00:00:00 2001
From: Rin Dobrescu <rin.dobrescu at arm.com>
Date: Thu, 18 Jan 2024 11:59:57 +0000
Subject: [PATCH 4/6] Cover more types and add test cases.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 20 +++++-
.../AArch64/aarch64-combine-add-zext.ll | 38 ++++++++++-
llvm/test/CodeGen/AArch64/vecreduce-add.ll | 66 ++++++++-----------
3 files changed, 80 insertions(+), 44 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index fedd50dd163e9b..91fa760bedd4d7 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16621,7 +16621,7 @@ static SDValue performUADDVZextCombine(SDValue A, SelectionDAG &DAG) {
if (A.getOpcode() != ISD::ADD)
return SDValue();
EVT VT = A.getValueType();
- if (VT != MVT::v4i32)
+ if (VT != MVT::v8i16 && VT != MVT::v4i32 && VT != MVT::v2i64)
return SDValue();
SDValue Op0 = A.getOperand(0);
SDValue Op1 = A.getOperand(1);
@@ -16632,13 +16632,27 @@ static SDValue performUADDVZextCombine(SDValue A, SelectionDAG &DAG) {
EVT ExtVT0 = Ext0.getValueType();
EVT ExtVT1 = Ext1.getValueType();
// Check zext VTs are the same and 64-bit length.
- if (ExtVT0 != ExtVT1 || !(ExtVT0 == MVT::v8i8 || ExtVT0 == MVT::v4i16))
+ if (ExtVT0 != ExtVT1 ||
+ !(ExtVT0 == MVT::v8i8 || ExtVT0 == MVT::v4i16 || ExtVT0 == MVT::v2i32))
return SDValue();
// Get VT for concat of zext sources.
EVT PairVT = ExtVT0.getDoubleNumVectorElementsVT(*DAG.getContext());
SDValue Concat =
DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(A), PairVT, Ext0, Ext1);
- return DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), MVT::v4i32, Concat);
+
+ switch (VT.getSimpleVT().SimpleTy) {
+ case MVT::v2i64:
+ return DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), MVT::v2i64, Concat);
+ case MVT::v4i32:
+ return DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), MVT::v4i32, Concat);
+ case MVT::v8i16: {
+ SDValue Uaddlv =
+ DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), MVT::v4i32, Concat);
+ return DAG.getNode(AArch64ISD::NVCAST, SDLoc(A), MVT::v8i16, Uaddlv);
+ }
+ default:
+ return SDValue();
+ }
}
static SDValue performUADDVCombine(SDNode *N, SelectionDAG &DAG) {
diff --git a/llvm/test/CodeGen/AArch64/aarch64-combine-add-zext.ll b/llvm/test/CodeGen/AArch64/aarch64-combine-add-zext.ll
index 1cb0206c3fdbc1..b1b995931ac024 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-combine-add-zext.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-combine-add-zext.ll
@@ -1,8 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
-define i32 @test_add_zext(<4 x i16> %a, <4 x i16> %b) local_unnamed_addr #0 {
-; CHECK-LABEL: test_add_zext:
+define i16 @test_add_zext_v8i16(<8 x i8> %a, <8 x i8> %b) local_unnamed_addr #0 {
+; CHECK-LABEL: test_add_zext_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: uaddlv h0, v0.16b
+; CHECK-NEXT: umov w0, v0.h[0]
+; CHECK-NEXT: ret
+ %z1 = zext <8 x i8> %a to <8 x i16>
+ %z2 = zext <8 x i8> %b to <8 x i16>
+ %z = add <8 x i16> %z1, %z2
+ %r = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %z)
+ ret i16 %r
+}
+
+define i32 @test_add_zext_v4i32(<4 x i16> %a, <4 x i16> %b) local_unnamed_addr #0 {
+; CHECK-LABEL: test_add_zext_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
@@ -17,4 +33,22 @@ define i32 @test_add_zext(<4 x i16> %a, <4 x i16> %b) local_unnamed_addr #0 {
ret i32 %r
}
+define i64 @test_add_zext_v2i64(<2 x i32> %a, <2 x i32> %b) local_unnamed_addr #0 {
+; CHECK-LABEL: test_add_zext_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: uaddlv d0, v0.4s
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
+ %z1 = zext <2 x i32> %a to <2 x i64>
+ %z2 = zext <2 x i32> %b to <2 x i64>
+ %z = add <2 x i64> %z1, %z2
+ %r = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %z)
+ ret i64 %r
+}
+
+declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
+declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-add.ll b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
index 38bb8b0d57a3f4..ad82d2e7955c27 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-add.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
@@ -1434,37 +1434,21 @@ entry:
}
define zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, i8 %a) {
-; CHECK-SD-BASE-LABEL: add_v16i8_v16i8_acc:
-; CHECK-SD-BASE: // %bb.0: // %entry
-; CHECK-SD-BASE-NEXT: addv b0, v0.16b
-; CHECK-SD-BASE-NEXT: fmov w8, s0
-; CHECK-SD-BASE-NEXT: add w8, w8, w0
-; CHECK-SD-BASE-NEXT: and w0, w8, #0xff
-; CHECK-SD-BASE-NEXT: ret
-;
-; CHECK-SD-DOT-LABEL: add_v16i8_v16i8_acc:
-; CHECK-SD-DOT: // %bb.0: // %entry
-; CHECK-SD-DOT-NEXT: addv b0, v0.16b
-; CHECK-SD-DOT-NEXT: fmov w8, s0
-; CHECK-SD-DOT-NEXT: add w8, w8, w0
-; CHECK-SD-DOT-NEXT: and w0, w8, #0xff
-; CHECK-SD-DOT-NEXT: ret
-;
-; CHECK-GI-BASE-LABEL: add_v16i8_v16i8_acc:
-; CHECK-GI-BASE: // %bb.0: // %entry
-; CHECK-GI-BASE-NEXT: addv b0, v0.16b
-; CHECK-GI-BASE-NEXT: fmov w8, s0
-; CHECK-GI-BASE-NEXT: add w8, w0, w8, uxtb
-; CHECK-GI-BASE-NEXT: and w0, w8, #0xff
-; CHECK-GI-BASE-NEXT: ret
+; CHECK-SD-LABEL: add_v16i8_v16i8_acc:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: addv b0, v0.16b
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: add w8, w8, w0
+; CHECK-SD-NEXT: and w0, w8, #0xff
+; CHECK-SD-NEXT: ret
;
-; CHECK-GI-DOT-LABEL: add_v16i8_v16i8_acc:
-; CHECK-GI-DOT: // %bb.0: // %entry
-; CHECK-GI-DOT-NEXT: addv b0, v0.16b
-; CHECK-GI-DOT-NEXT: fmov w8, s0
-; CHECK-GI-DOT-NEXT: add w8, w0, w8, uxtb
-; CHECK-GI-DOT-NEXT: and w0, w8, #0xff
-; CHECK-GI-DOT-NEXT: ret
+; CHECK-GI-LABEL: add_v16i8_v16i8_acc:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addv b0, v0.16b
+; CHECK-GI-NEXT: fmov w8, s0
+; CHECK-GI-NEXT: add w8, w0, w8, uxtb
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: ret
entry:
%z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %x)
%r = add i8 %z, %a
@@ -1783,8 +1767,10 @@ entry:
define i64 @add_pair_v2i32_v2i64_zext(<2 x i32> %x, <2 x i32> %y) {
; CHECK-SD-LABEL: add_pair_v2i32_v2i64_zext:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: uaddl v0.2d, v0.2s, v1.2s
-; CHECK-SD-NEXT: addp d0, v0.2d
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: uaddlv d0, v0.4s
; CHECK-SD-NEXT: fmov x0, d0
; CHECK-SD-NEXT: ret
;
@@ -3300,8 +3286,8 @@ define i64 @add_pair_v2i16_v2i64_zext(<2 x i16> %x, <2 x i16> %y) {
; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
-; CHECK-SD-NEXT: uaddl v0.2d, v0.2s, v1.2s
-; CHECK-SD-NEXT: addp d0, v0.2d
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: uaddlv d0, v0.4s
; CHECK-SD-NEXT: fmov x0, d0
; CHECK-SD-NEXT: ret
;
@@ -3714,9 +3700,11 @@ entry:
define zeroext i16 @add_pair_v8i8_v8i16_zext(<8 x i8> %x, <8 x i8> %y) {
; CHECK-SD-LABEL: add_pair_v8i8_v8i16_zext:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: uaddl v0.8h, v0.8b, v1.8b
-; CHECK-SD-NEXT: addv h0, v0.8h
-; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: uaddlv h0, v0.16b
+; CHECK-SD-NEXT: umov w0, v0.h[0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: add_pair_v8i8_v8i16_zext:
@@ -4051,8 +4039,8 @@ define i64 @add_pair_v2i8_v2i64_zext(<2 x i8> %x, <2 x i8> %y) {
; CHECK-SD-NEXT: movi d2, #0x0000ff000000ff
; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
-; CHECK-SD-NEXT: uaddl v0.2d, v0.2s, v1.2s
-; CHECK-SD-NEXT: addp d0, v0.2d
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: uaddlv d0, v0.4s
; CHECK-SD-NEXT: fmov x0, d0
; CHECK-SD-NEXT: ret
;
>From 39bdfd8877b69a22f0c95cbec225c0870b3377c3 Mon Sep 17 00:00:00 2001
From: Rin Dobrescu <rin.dobrescu at arm.com>
Date: Fri, 19 Jan 2024 09:36:54 +0000
Subject: [PATCH 5/6] Replace ADD check with assert and make 64-bit check
clearer.
---
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 91fa760bedd4d7..b222e9108eb862 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16569,8 +16569,7 @@ static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) {
auto DetectAddExtract = [&](SDValue A) {
// Look for add(zext(extract_lo(x)), zext(extract_hi(x))), returning
// UADDLP(x) if found.
- if (A.getOpcode() != ISD::ADD)
- return SDValue();
+ assert(A.getOpcode() == ISD::ADD);
EVT VT = A.getValueType();
SDValue Op0 = A.getOperand(0);
SDValue Op1 = A.getOperand(1);
@@ -16618,8 +16617,7 @@ static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) {
static SDValue performUADDVZextCombine(SDValue A, SelectionDAG &DAG) {
// Look for add(zext(64-bit source), zext(64-bit source)), returning
// UADDLV(concat(zext, zext)) if found.
- if (A.getOpcode() != ISD::ADD)
- return SDValue();
+ assert(A.getOpcode() == ISD::ADD);
EVT VT = A.getValueType();
if (VT != MVT::v8i16 && VT != MVT::v4i32 && VT != MVT::v2i64)
return SDValue();
@@ -16633,7 +16631,7 @@ static SDValue performUADDVZextCombine(SDValue A, SelectionDAG &DAG) {
EVT ExtVT1 = Ext1.getValueType();
// Check zext VTs are the same and 64-bit length.
if (ExtVT0 != ExtVT1 ||
- !(ExtVT0 == MVT::v8i8 || ExtVT0 == MVT::v4i16 || ExtVT0 == MVT::v2i32))
+ VT.getScalarSizeInBits() != (2 * ExtVT0.getScalarSizeInBits()))
return SDValue();
// Get VT for concat of zext sources.
EVT PairVT = ExtVT0.getDoubleNumVectorElementsVT(*DAG.getContext());
>From e7182ba2595a975dea2251c3de02f05a38b63e6b Mon Sep 17 00:00:00 2001
From: Rin Dobrescu <rin.dobrescu at arm.com>
Date: Fri, 19 Jan 2024 15:31:09 +0000
Subject: [PATCH 6/6] Change default to return llvm_unreachable.
---
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index b222e9108eb862..eccb53a8174792 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16640,16 +16640,15 @@ static SDValue performUADDVZextCombine(SDValue A, SelectionDAG &DAG) {
switch (VT.getSimpleVT().SimpleTy) {
case MVT::v2i64:
- return DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), MVT::v2i64, Concat);
case MVT::v4i32:
- return DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), MVT::v4i32, Concat);
+ return DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), VT, Concat);
case MVT::v8i16: {
SDValue Uaddlv =
DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), MVT::v4i32, Concat);
return DAG.getNode(AArch64ISD::NVCAST, SDLoc(A), MVT::v8i16, Uaddlv);
}
default:
- return SDValue();
+ llvm_unreachable("Unhandled vector type");
}
}
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