[llvm] [RISCV] Fix stack size computation when M extension disabled (PR #78602)

[Craig Topper via llvm-commits]

topperc wrote:

> > @asb I surmise there may be certain embedded RV32I cores out there that might require it, but we don't have any on our end. However, the code in question was the only place I found where we emit a mul instruction, so I don't anticipate much effort beyond this patch to support this configuration.
> > The original motivation for this came from the fact that certain tests are defined without `-mattr=+m` and therefore crash when a patch does something to change the stack size to an inconvenient value. I didn't think it would be justified for me to sneak in the attribute simply to hide the crash, hence this patch.
> 
> @simeonkr , @asb I found this contribution very useful.
> 
> Permit a small info addition here:
> 
> * there are lots of popular softcores (fpga/asic) `rv32i` (m-less)
>   https://github.com/riscvarchive/riscv-cores-list
> * there are real world mcu like CH32Vxxx (think of atmel/attiny popularity level):
>   https://www.wch-ic.com/products/CH32V003.html
> * GCC land also permits a m-less code emission

This patch is specifically for Zve* or V without M. rv32i should already support m-less code emission using library calls for multiply.

https://github.com/llvm/llvm-project/pull/78602