[llvm] [RISCV] Add IntrArgMemOnly for vector load/store intrinsic (PR #78415)

[Wang Pengcheng via llvm-commits]

================
@@ -177,7 +179,8 @@ let TargetPrefix = "riscv" in {
                     [LLVMMatchType<0>, llvm_ptr_ty,
                      LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                      llvm_anyint_ty, LLVMMatchType<1>],
-                    [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<4>>, IntrReadMem]>,
+                    [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<4>>, IntrReadMem,
----------------
wangpc-pp wrote:

Oh I misread it, I was reading the line below.

https://github.com/llvm/llvm-project/pull/78415