[llvm] [RISCV] Add IntrArgMemOnly for vector load/store intrinsic (PR #78415)
Jianjian Guan via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 17 01:29:27 PST 2024
https://github.com/jacquesguan created https://github.com/llvm/llvm-project/pull/78415
IntrArgMemOnly means the intrinsic only accesses memory that its pointer-typed argument(s) points to. I think RVV load/store intrinsics meets it. Add IntrArgMemOnly would help in some passes, by example, it could add `alais.scope` to intrinsics callee when try to inline a function that has noalais parameter(s).
>From affc8d540aa419a883c8046678cf2c05b8dfd37f Mon Sep 17 00:00:00 2001
From: Jianjian GUAN <jacquesguan at me.com>
Date: Wed, 17 Jan 2024 15:26:03 +0800
Subject: [PATCH] [RISCV] Add IntrArgMemOnly for vector load/store intrinsic
---
llvm/include/llvm/IR/IntrinsicsRISCV.td | 81 ++++++++++++++++---------
1 file changed, 53 insertions(+), 28 deletions(-)
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index a391bc53cdb0e99..b140e31ca263e18 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -147,7 +147,8 @@ let TargetPrefix = "riscv" in {
class RISCVUSMLoad
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[llvm_ptr_ty, llvm_anyint_ty],
- [NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<0>>, IntrReadMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = 1;
}
// For unit stride load
@@ -155,7 +156,8 @@ let TargetPrefix = "riscv" in {
class RISCVUSLoad
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_ptr_ty, llvm_anyint_ty],
- [NoCapture<ArgIndex<1>>, IntrReadMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<1>>, IntrReadMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = 2;
}
// For unit stride fault-only-first load
@@ -177,7 +179,8 @@ let TargetPrefix = "riscv" in {
[LLVMMatchType<0>, llvm_ptr_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<1>],
- [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<4>>, IntrReadMem]>,
+ [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<4>>, IntrReadMem,
+ IntrArgMemOnly]>,
RISCVVIntrinsic {
let VLOperand = 3;
}
@@ -200,7 +203,8 @@ let TargetPrefix = "riscv" in {
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_ptr_ty,
llvm_anyint_ty, LLVMMatchType<1>],
- [NoCapture<ArgIndex<1>>, IntrReadMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<1>>, IntrReadMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = 3;
}
// For strided load with mask
@@ -210,7 +214,8 @@ let TargetPrefix = "riscv" in {
[LLVMMatchType<0>, llvm_ptr_ty, llvm_anyint_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<1>,
LLVMMatchType<1>],
- [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<5>>, IntrReadMem]>,
+ [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<5>>, IntrReadMem,
+ IntrArgMemOnly]>,
RISCVVIntrinsic {
let VLOperand = 4;
}
@@ -220,7 +225,8 @@ let TargetPrefix = "riscv" in {
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_ptr_ty,
llvm_anyvector_ty, llvm_anyint_ty],
- [NoCapture<ArgIndex<1>>, IntrReadMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<1>>, IntrReadMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = 3;
}
// For indexed load with mask
@@ -230,7 +236,8 @@ let TargetPrefix = "riscv" in {
[LLVMMatchType<0>, llvm_ptr_ty, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<2>],
- [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<5>>, IntrReadMem]>,
+ [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<5>>, IntrReadMem,
+ IntrArgMemOnly]>,
RISCVVIntrinsic {
let VLOperand = 4;
}
@@ -239,7 +246,8 @@ let TargetPrefix = "riscv" in {
class RISCVUSStore
: DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty, llvm_ptr_ty, llvm_anyint_ty],
- [NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<1>>, IntrWriteMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = 2;
}
// For unit stride store with mask
@@ -249,7 +257,8 @@ let TargetPrefix = "riscv" in {
[llvm_anyvector_ty, llvm_ptr_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty],
- [NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<1>>, IntrWriteMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = 3;
}
// For strided store
@@ -258,7 +267,8 @@ let TargetPrefix = "riscv" in {
: DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty, llvm_ptr_ty,
llvm_anyint_ty, LLVMMatchType<1>],
- [NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<1>>, IntrWriteMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = 3;
}
// For stride store with mask
@@ -267,7 +277,8 @@ let TargetPrefix = "riscv" in {
: DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty, llvm_ptr_ty, llvm_anyint_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<1>],
- [NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<1>>, IntrWriteMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = 4;
}
// For indexed store
@@ -276,7 +287,8 @@ let TargetPrefix = "riscv" in {
: DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty, llvm_ptr_ty,
llvm_anyint_ty, llvm_anyint_ty],
- [NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<1>>, IntrWriteMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = 3;
}
// For indexed store with mask
@@ -285,7 +297,8 @@ let TargetPrefix = "riscv" in {
: DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty, llvm_ptr_ty, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
- [NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<1>>, IntrWriteMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = 4;
}
// For destination vector type is the same as source vector.
@@ -992,7 +1005,8 @@ let TargetPrefix = "riscv" in {
!add(nf, -1))),
!listconcat(!listsplat(LLVMMatchType<0>, nf),
[llvm_ptr_ty, llvm_anyint_ty]),
- [NoCapture<ArgIndex<nf>>, IntrReadMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<nf>>, IntrReadMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = !add(nf, 1);
}
// For unit stride segment load with mask
@@ -1004,8 +1018,9 @@ let TargetPrefix = "riscv" in {
[llvm_ptr_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<1>]),
- [ImmArg<ArgIndex<!add(nf, 3)>>, NoCapture<ArgIndex<nf>>, IntrReadMem]>,
- RISCVVIntrinsic {
+ [ImmArg<ArgIndex<!add(nf, 3)>>, NoCapture<ArgIndex<nf>>, IntrReadMem,
+ IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = !add(nf, 2);
}
@@ -1046,7 +1061,8 @@ let TargetPrefix = "riscv" in {
!add(nf, -1))),
!listconcat(!listsplat(LLVMMatchType<0>, nf),
[llvm_ptr_ty, llvm_anyint_ty, LLVMMatchType<1>]),
- [NoCapture<ArgIndex<nf>>, IntrReadMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<nf>>, IntrReadMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = !add(nf, 2);
}
// For stride segment load with mask
@@ -1059,8 +1075,9 @@ let TargetPrefix = "riscv" in {
llvm_anyint_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMMatchType<1>, LLVMMatchType<1>]),
- [ImmArg<ArgIndex<!add(nf, 4)>>, NoCapture<ArgIndex<nf>>, IntrReadMem]>,
- RISCVVIntrinsic {
+ [ImmArg<ArgIndex<!add(nf, 4)>>, NoCapture<ArgIndex<nf>>,
+ IntrReadMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = !add(nf, 3);
}
@@ -1071,7 +1088,8 @@ let TargetPrefix = "riscv" in {
!add(nf, -1))),
!listconcat(!listsplat(LLVMMatchType<0>, nf),
[llvm_ptr_ty, llvm_anyvector_ty, llvm_anyint_ty]),
- [NoCapture<ArgIndex<nf>>, IntrReadMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<nf>>, IntrReadMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = !add(nf, 2);
}
// For indexed segment load with mask
@@ -1084,8 +1102,9 @@ let TargetPrefix = "riscv" in {
llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<2>]),
- [ImmArg<ArgIndex<!add(nf, 4)>>, NoCapture<ArgIndex<nf>>, IntrReadMem]>,
- RISCVVIntrinsic {
+ [ImmArg<ArgIndex<!add(nf, 4)>>, NoCapture<ArgIndex<nf>>,
+ IntrReadMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = !add(nf, 3);
}
@@ -1096,7 +1115,8 @@ let TargetPrefix = "riscv" in {
!listconcat([llvm_anyvector_ty],
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
[llvm_ptr_ty, llvm_anyint_ty]),
- [NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<nf>>, IntrWriteMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = !add(nf, 1);
}
// For unit stride segment store with mask
@@ -1108,7 +1128,8 @@ let TargetPrefix = "riscv" in {
[llvm_ptr_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty]),
- [NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<nf>>, IntrWriteMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = !add(nf, 2);
}
@@ -1120,7 +1141,8 @@ let TargetPrefix = "riscv" in {
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
[llvm_ptr_ty, llvm_anyint_ty,
LLVMMatchType<1>]),
- [NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<nf>>, IntrWriteMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = !add(nf, 2);
}
// For stride segment store with mask
@@ -1132,7 +1154,8 @@ let TargetPrefix = "riscv" in {
[llvm_ptr_ty, llvm_anyint_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMMatchType<1>]),
- [NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<nf>>, IntrWriteMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = !add(nf, 3);
}
@@ -1144,7 +1167,8 @@ let TargetPrefix = "riscv" in {
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
[llvm_ptr_ty, llvm_anyvector_ty,
llvm_anyint_ty]),
- [NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<nf>>, IntrWriteMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = !add(nf, 2);
}
// For indexed segment store with mask
@@ -1156,7 +1180,8 @@ let TargetPrefix = "riscv" in {
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty]),
- [NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {
+ [NoCapture<ArgIndex<nf>>, IntrWriteMem, IntrArgMemOnly]>,
+ RISCVVIntrinsic {
let VLOperand = !add(nf, 3);
}
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