[llvm] 7fe5269 - [RISCV] Bump Zfbfmin, Zvfbfmin, and Zvfbfwma to 1.0. (#78021)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 16 08:42:26 PST 2024
Author: Craig Topper
Date: 2024-01-16T08:42:21-08:00
New Revision: 7fe5269b544b33c9e32de50b76fe0b67022de6d3
URL: https://github.com/llvm/llvm-project/commit/7fe5269b544b33c9e32de50b76fe0b67022de6d3
DIFF: https://github.com/llvm/llvm-project/commit/7fe5269b544b33c9e32de50b76fe0b67022de6d3.diff
LOG: [RISCV] Bump Zfbfmin, Zvfbfmin, and Zvfbfwma to 1.0. (#78021)
Added:
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/unittests/Support/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index dfc24555f40489..fd0970bd87fd14 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1064,12 +1064,12 @@
// CHECK-ZFA-EXT: __riscv_zfa 1000000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32izfbfmin0p8 -x c -E -dM %s \
+// RUN: -march=rv32izfbfmin1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64izfbfmin0p8 -x c -E -dM %s \
+// RUN: -march=rv64izfbfmin1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s
-// CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 8000{{$}}
+// CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 1000000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zicfilp0p4 -x c -E -dM %s \
@@ -1128,20 +1128,20 @@
// CHECK-ZVBC-EXT: __riscv_zvbc 1000000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32ifzvfbfmin0p8 -x c -E -dM %s \
+// RUN: -march=rv32ifzvfbfmin1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64ifzvfbfmin0p8 -x c -E -dM %s \
+// RUN: -march=rv64ifzvfbfmin1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s
-// CHECK-ZVFBFMIN-EXT: __riscv_zvfbfmin 8000{{$}}
+// CHECK-ZVFBFMIN-EXT: __riscv_zvfbfmin 1000000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32ifzvfbfwma0p8 -x c -E -dM %s \
+// RUN: -march=rv32ifzvfbfwma1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64ifzvfbfwma0p8 -x c -E -dM %s \
+// RUN: -march=rv64ifzvfbfwma1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
-// CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 8000{{$}}
+// CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 1000000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zve32x_zvkg1p0 -x c -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 0155d5dbc0e841..40fbaaa24e839a 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -216,7 +216,7 @@ The primary goal of experimental support is to assist in the process of ratifica
LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`_.
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
- LLVM implements assembler support for the `0.8.0 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_.
+ LLVM implements assembler support for the `1.0.0-rc2 specification <https://github.com/riscv/riscv-bfloat16/releases/tag/v59042fc71c31a9bcb2f1957621c960ed36fac401>`_.
``experimental-zicfilp``, ``experimental-zicfiss``
LLVM implements the `0.4 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0>`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index f4b3947e80faeb..d991878a5f1eca 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -187,7 +187,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zcmop", {0, 2}},
- {"zfbfmin", {0, 8}},
+ {"zfbfmin", {1, 0}},
{"zicfilp", {0, 4}},
{"zicfiss", {0, 4}},
@@ -198,8 +198,8 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"ztso", {0, 1}},
- {"zvfbfmin", {0, 8}},
- {"zvfbfwma", {0, 8}},
+ {"zvfbfmin", {1, 0}},
+ {"zvfbfwma", {1, 0}},
};
static void verifyTables() {
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 9a6e78c09ad8c3..60ef404ac345d1 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -238,7 +238,7 @@
; RV32XCVMEM: .attribute 5, "rv32i2p1_xcvmem1p0"
; RV32XCVSIMD: .attribute 5, "rv32i2p1_xcvsimd1p0"
; RV32XCVBI: .attribute 5, "rv32i2p1_xcvbi1p0"
-; RV32XSFVFWMACCQQQ: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0_xsfvfwmaccqqq1p0"
+; RV32XSFVFWMACCQQQ: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"
; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0"
; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0"
; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"
@@ -279,9 +279,9 @@
; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
-; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8"
-; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
-; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
+; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
+; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
+; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4"
@@ -327,7 +327,7 @@
; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0"
; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0"
; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p1_xventanacondops1p0"
-; RV64XSFVFWMACCQQQ: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0_xsfvfwmaccqqq1p0"
+; RV64XSFVFWMACCQQQ: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"
; RV64XTHEADBA: .attribute 5, "rv64i2p1_xtheadba1p0"
; RV64XTHEADBB: .attribute 5, "rv64i2p1_xtheadbb1p0"
; RV64XTHEADBS: .attribute 5, "rv64i2p1_xtheadbs1p0"
@@ -372,9 +372,9 @@
; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2"
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
-; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8"
-; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
-; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
+; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
+; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
+; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0"
; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 4f8a8dfdbcec90..0e508bb80f6b94 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -273,14 +273,14 @@
.attribute arch, "rv32i_ssaia1p0"
# CHECK: attribute 5, "rv32i2p1_ssaia1p0"
-.attribute arch, "rv32i_zfbfmin0p8"
-# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8"
+.attribute arch, "rv32i_zfbfmin1p0"
+# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
-.attribute arch, "rv32i_zvfbfmin0p8"
-# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
+.attribute arch, "rv32i_zvfbfmin1p0"
+# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
-.attribute arch, "rv32i_zvfbfwma0p8"
-# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
+.attribute arch, "rv32i_zvfbfwma1p0"
+# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
.attribute arch, "rv32izacas1p0"
# CHECK: attribute 5, "rv32i2p1_a2p1_zacas1p0"
@@ -313,4 +313,4 @@
# CHECK: .attribute 5, "rv32i2p1_zicfiss0p4_zicsr2p0_zimop0p1"
.attribute arch, "rv64i_xsfvfwmaccqqq"
-# CHECK: attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0_xsfvfwmaccqqq1p0"
+# CHECK: attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 997551e5c44c09..c8e77cdccf4e8a 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -788,11 +788,11 @@ Experimental extensions
zicond 1.0
zimop 0.1
zacas 1.0
- zfbfmin 0.8
+ zfbfmin 1.0
zcmop 0.2
ztso 0.1
- zvfbfmin 0.8
- zvfbfwma 0.8
+ zvfbfmin 1.0
+ zvfbfwma 1.0
Use -march to specify the target's extension.
For example, clang -march=rv32i_v1p0)";
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