[llvm] [X86][APX] Avoid generating illegal MI_ND ndd instructions (PR #78233)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 16 02:16:45 PST 2024
https://github.com/XinWang10 updated https://github.com/llvm/llvm-project/pull/78233
>From cd71e7968e2c83e4e21017e479a32904a15ba3a9 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Mon, 15 Jan 2024 19:55:44 -0800
Subject: [PATCH 1/7] Invalid encoding for ndd mi32
---
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 39 +-
llvm/lib/Target/X86/X86InstrArithmetic.td | 8 +-
llvm/lib/Target/X86/X86InstrFragments.td | 3 +
llvm/lib/Target/X86/X86InstrInfo.cpp | 34 ++
llvm/lib/Target/X86/X86InstrUtils.td | 6 +-
.../apx/invalid-segment-prefix-with-ndd.ll | 443 ++++++++++++++++++
6 files changed, 525 insertions(+), 8 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/apx/invalid-segment-prefix-with-ndd.ll
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 53ce720be2da4c..1b7d48f69ad5dd 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -222,6 +222,9 @@ namespace {
bool selectAddr(SDNode *Parent, SDValue N, SDValue &Base,
SDValue &Scale, SDValue &Index, SDValue &Disp,
SDValue &Segment);
+ bool selectNoSegADDRAddr(SDNode *Parent, SDValue N, SDValue &Base,
+ SDValue &Scale, SDValue &Index, SDValue &Disp,
+ SDValue &Segment);
bool selectVectorAddr(MemSDNode *Parent, SDValue BasePtr, SDValue IndexOp,
SDValue ScaleOp, SDValue &Base, SDValue &Scale,
SDValue &Index, SDValue &Disp, SDValue &Segment);
@@ -2908,8 +2911,38 @@ bool X86DAGToDAGISel::selectAddr(SDNode *Parent, SDValue N, SDValue &Base,
AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
if (AddrSpace == X86AS::FS)
AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
- if (AddrSpace == X86AS::SS)
+ if (AddrSpace == X86AS::SS){
+ llvm_unreachable("debug");
AM.Segment = CurDAG->getRegister(X86::SS, MVT::i16);
+ }
+ }
+
+ // Save the DL and VT before calling matchAddress, it can invalidate N.
+ SDLoc DL(N);
+ MVT VT = N.getSimpleValueType();
+
+ if (matchAddress(N, AM))
+ return false;
+
+ getAddressOperands(AM, DL, VT, Base, Scale, Index, Disp, Segment);
+ return true;
+}
+
+/// Returns true if it is able to pattern match an addressing mode with no
+/// segment reg prefix. It returns the operands which make up the maximal
+/// addressing mode it can match by reference.
+bool X86DAGToDAGISel::selectNoSegADDRAddr(SDNode *Parent, SDValue N,
+ SDValue &Base, SDValue &Scale,
+ SDValue &Index, SDValue &Disp,
+ SDValue &Segment) {
+ X86ISelAddressMode AM;
+
+ if (Parent) {
+ unsigned AddrSpace =
+ cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
+ if (AddrSpace == X86AS::GS || AddrSpace == X86AS::FS ||
+ AddrSpace == X86AS::SS)
+ return false;
}
// Save the DL and VT before calling matchAddress, it can invalidate N.
@@ -2919,6 +2952,10 @@ bool X86DAGToDAGISel::selectAddr(SDNode *Parent, SDValue N, SDValue &Base,
if (matchAddress(N, AM))
return false;
+ // FS prefix.
+ if (AM.SymbolFlags == 13)
+ return false;
+
getAddressOperands(AM, DL, VT, Base, Scale, Index, Disp, Segment);
return true;
}
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index 76b0fe5f5cad18..4bbae0af811561 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -755,8 +755,8 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
def 64mi8_ND : BinOpMI8_RF<mnemonic, Xi64, MemMRM>;
def 8mi_ND : BinOpMI_RF<0x80, mnemonic, Xi8 , opnode, MemMRM>;
def 16mi_ND : BinOpMI_RF<0x81, mnemonic, Xi16, opnode, MemMRM>, PD;
- def 32mi_ND : BinOpMI_RF<0x81, mnemonic, Xi32, opnode, MemMRM>;
- def 64mi32_ND : BinOpMI_RF<0x81, mnemonic, Xi64, opnode, MemMRM>;
+ def 32mi_ND : BinOpMI_RF<0x81, mnemonic, Xi32, opnode, MemMRM, nosegaddr>;
+ def 64mi32_ND : BinOpMI_RF<0x81, mnemonic, Xi64, opnode, MemMRM, nosegaddr>;
def 16mi8_NF_ND : BinOpMI8_R<mnemonic, Xi16, MemMRM>, NF, PD;
def 32mi8_NF_ND : BinOpMI8_R<mnemonic, Xi32, MemMRM>, NF;
def 64mi8_NF_ND : BinOpMI8_R<mnemonic, Xi64, MemMRM>, NF;
@@ -940,8 +940,8 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
def 32mi8_ND : BinOpMI8F_RF<mnemonic, Xi32, MemMRM>;
def 64mi8_ND : BinOpMI8F_RF<mnemonic, Xi64, MemMRM>;
def 16mi_ND : BinOpMIF_RF<0x81, mnemonic, Xi16, opnode, MemMRM>, PD;
- def 32mi_ND : BinOpMIF_RF<0x81, mnemonic, Xi32, opnode, MemMRM>;
- def 64mi32_ND : BinOpMIF_RF<0x81, mnemonic, Xi64, opnode, MemMRM>;
+ def 32mi_ND : BinOpMIF_RF<0x81, mnemonic, Xi32, opnode, MemMRM, nosegaddr>;
+ def 64mi32_ND : BinOpMIF_RF<0x81, mnemonic, Xi64, opnode, MemMRM, nosegaddr>;
}
let Predicates = [In64BitMode] in {
def 8mi_EVEX : BinOpMIF_MF<0x80, mnemonic, Xi8 , opnode, MemMRM>, PL;
diff --git a/llvm/lib/Target/X86/X86InstrFragments.td b/llvm/lib/Target/X86/X86InstrFragments.td
index adf527d72f5b43..d3e847a3c6b9e3 100644
--- a/llvm/lib/Target/X86/X86InstrFragments.td
+++ b/llvm/lib/Target/X86/X86InstrFragments.td
@@ -362,6 +362,9 @@ def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
[tglobaltlsaddr], []>;
+def nosegaddr : ComplexPattern<i64, 5, "selectNoSegADDRAddr",
+ [], [SDNPWantParent]>;
+
def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>;
// A relocatable immediate is an operand that can be relocated by the linker to
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index bddda6891356e8..6662021c66ed1c 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -7251,6 +7251,40 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
MI.getOpcode() != X86::ADD64rr)
return nullptr;
+ // MI_ND Instructions with 32 bit imm would exceed maximum code length if they
+ // need segment register prefix.
+ if (MOs.size() == X86::AddrNumOperands &&
+ (MOs[4].getReg() == X86::GS || MOs[4].getReg() == X86::FS))
+ switch (MI.getOpcode()) {
+ default:
+ break;
+ case X86::ADD32ri_ND:
+ case X86::ADD64ri32_ND:
+ case X86::ADD32ri_NF_ND:
+ case X86::ADD64ri32_NF_ND:
+ case X86::SUB32ri_ND:
+ case X86::SUB64ri32_ND:
+ case X86::SUB32ri_NF_ND:
+ case X86::SUB64ri32_NF_ND:
+ case X86::AND32ri_ND:
+ case X86::AND64ri32_ND:
+ case X86::AND32ri_NF_ND:
+ case X86::AND64ri32_NF_ND:
+ case X86::XOR32ri_ND:
+ case X86::XOR64ri32_ND:
+ case X86::XOR32ri_NF_ND:
+ case X86::XOR64ri32_NF_ND:
+ case X86::OR32ri_ND:
+ case X86::OR64ri32_ND:
+ case X86::OR32ri_NF_ND:
+ case X86::OR64ri32_NF_ND:
+ case X86::ADC32ri_ND:
+ case X86::ADC64ri32_ND:
+ case X86::SBB32ri_ND:
+ case X86::SBB64ri32_ND:
+ return nullptr;
+ }
+
// Don't fold loads into indirect calls that need a KCFI check as we'll
// have to unfold these in X86TargetLowering::EmitKCFICheck anyway.
if (MI.isCall() && MI.getCFIType())
diff --git a/llvm/lib/Target/X86/X86InstrUtils.td b/llvm/lib/Target/X86/X86InstrUtils.td
index f4ae15837fbf54..d28aac4038a469 100644
--- a/llvm/lib/Target/X86/X86InstrUtils.td
+++ b/llvm/lib/Target/X86/X86InstrUtils.td
@@ -1182,7 +1182,7 @@ class BinOpMI_R<bits<8> o, string m, X86TypeInfo t, Format f>
Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, NDD<1>;
// BinOpMI_R - Instructions that read "[mem], imm" and write "reg", EFLAGS.
class BinOpMI_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node,
- Format f>
+ Format f, ComplexPattern addr = addr>
: BinOpMI<o, m, binop_ndd_args, t, f, (outs t.RegClass:$dst),
[(set t.RegClass:$dst, EFLAGS, (node (t.LoadNode addr:$src1), t.ImmOperator:$src2))]>,
Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, DefEFLAGS, NDD<1>;
@@ -1201,14 +1201,14 @@ class BinOpMI_MF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, For
}
// BinOpMIF_RF - Instructions that read "[mem], imm", write "reg" and
// read/write EFLAGS.
-class BinOpMIF_RF<bits<8> o, string m, X86TypeInfo t, SDNode node, Format f>
+class BinOpMIF_RF<bits<8> o, string m, X86TypeInfo t, SDNode node, Format f, ComplexPattern addr = addr>
: BinOpMI<o, m, binop_ndd_args, t, f, (outs t.RegClass:$dst),
[(set t.RegClass:$dst, EFLAGS, (node (t.VT (load addr:$src1)),
t.ImmOperator:$src2, EFLAGS))]>,
Sched<[WriteADC.Folded, WriteADC.ReadAfterFold]>, DefEFLAGS, UseEFLAGS, NDD<1>;
// BinOpMIF_MF - Instructions that read "[mem], imm", write "[mem]" and
// read/write EFLAGS.
-class BinOpMIF_MF<bits<8> o, string m, X86TypeInfo t, SDNode node, Format f>
+class BinOpMIF_MF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, Format f>
: BinOpMI<o, m, binop_args, t, f, (outs),
[(store (node (t.VT (load addr:$src1)),
t.ImmOperator:$src2, EFLAGS), addr:$src1), (implicit EFLAGS)]>,
diff --git a/llvm/test/CodeGen/X86/apx/invalid-segment-prefix-with-ndd.ll b/llvm/test/CodeGen/X86/apx/invalid-segment-prefix-with-ndd.ll
new file mode 100644
index 00000000000000..47439c41074fb7
--- /dev/null
+++ b/llvm/test/CodeGen/X86/apx/invalid-segment-prefix-with-ndd.ll
@@ -0,0 +1,443 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs --show-mc-encoding | FileCheck %s
+
+ at tm_nest_level = internal thread_local global i32 0
+define i32 @add32mi_FS() nounwind {
+; CHECK-LABEL: add32mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: addl %ecx, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x01,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i32, ptr @tm_nest_level
+ %add = add nsw i32 %t, 123456
+ ret i32 %add
+}
+
+define i32 @add32mi_GS() {
+; CHECK-LABEL: add32mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl $123456, %eax # encoding: [0xb8,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: addl %eax, %gs:255, %eax # encoding: [0x65,0x62,0xf4,0x7c,0x18,0x01,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a= inttoptr i32 255 to ptr addrspace(256)
+ %t = load i32, ptr addrspace(256) %a
+ %add = add nsw i32 %t, 123456
+ ret i32 %add
+}
+
+define i64 @add64mi_FS() nounwind {
+; CHECK-LABEL: add64mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: addq %rcx, tm_nest_level at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x01,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i64, ptr @tm_nest_level
+ %add = add nsw i64 %t, 123456
+ ret i64 %add
+}
+
+define i64 @add64mi_GS() {
+; CHECK-LABEL: add64mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl $123456, %eax # encoding: [0xb8,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: addq %rax, %gs:255, %rax # encoding: [0x65,0x62,0xf4,0xfc,0x18,0x01,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a= inttoptr i64 255 to ptr addrspace(256)
+ %t = load i64, ptr addrspace(256) %a
+ %add = add nsw i64 %t, 123456
+ ret i64 %add
+}
+
+define i32 @sub32mi_FS() nounwind {
+; CHECK-LABEL: sub32mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: movl $-123456, %ecx # encoding: [0xb9,0xc0,0x1d,0xfe,0xff]
+; CHECK-NEXT: # imm = 0xFFFE1DC0
+; CHECK-NEXT: addl %ecx, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x01,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i32, ptr @tm_nest_level
+ %sub = sub nsw i32 %t, 123456
+ ret i32 %sub
+}
+
+define i32 @sub32mi_GS() {
+; CHECK-LABEL: sub32mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl $-123456, %eax # encoding: [0xb8,0xc0,0x1d,0xfe,0xff]
+; CHECK-NEXT: # imm = 0xFFFE1DC0
+; CHECK-NEXT: addl %eax, %gs:255, %eax # encoding: [0x65,0x62,0xf4,0x7c,0x18,0x01,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a= inttoptr i32 255 to ptr addrspace(256)
+ %t = load i32, ptr addrspace(256) %a
+ %sub = sub nsw i32 %t, 123456
+ ret i32 %sub
+}
+
+define i64 @sub64mi_FS() nounwind {
+; CHECK-LABEL: sub64mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: movq $-123456, %rcx # encoding: [0x48,0xc7,0xc1,0xc0,0x1d,0xfe,0xff]
+; CHECK-NEXT: # imm = 0xFFFE1DC0
+; CHECK-NEXT: addq %rcx, tm_nest_level at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x01,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i64, ptr @tm_nest_level
+ %sub = sub nsw i64 %t, 123456
+ ret i64 %sub
+}
+
+define i64 @sub64mi_GS() {
+; CHECK-LABEL: sub64mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq $-123456, %rax # encoding: [0x48,0xc7,0xc0,0xc0,0x1d,0xfe,0xff]
+; CHECK-NEXT: # imm = 0xFFFE1DC0
+; CHECK-NEXT: addq %rax, %gs:255, %rax # encoding: [0x65,0x62,0xf4,0xfc,0x18,0x01,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a= inttoptr i64 255 to ptr addrspace(256)
+ %t = load i64, ptr addrspace(256) %a
+ %sub = sub nsw i64 %t, 123456
+ ret i64 %sub
+}
+
+define i32 @or32mi_FS() nounwind {
+; CHECK-LABEL: or32mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: orl %ecx, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x09,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i32, ptr @tm_nest_level
+ %or = or i32 %t, 123456
+ ret i32 %or
+}
+
+define i32 @or32mi_GS() {
+; CHECK-LABEL: or32mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl $123456, %eax # encoding: [0xb8,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: orl %eax, %gs:255, %eax # encoding: [0x65,0x62,0xf4,0x7c,0x18,0x09,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a= inttoptr i32 255 to ptr addrspace(256)
+ %t = load i32, ptr addrspace(256) %a
+ %or = or i32 %t, 123456
+ ret i32 %or
+}
+
+define i64 @or64mi_FS() nounwind {
+; CHECK-LABEL: or64mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: orq %rcx, tm_nest_level at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x09,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i64, ptr @tm_nest_level
+ %or = or i64 %t, 123456
+ ret i64 %or
+}
+
+define i64 @or64mi_GS() {
+; CHECK-LABEL: or64mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl $123456, %eax # encoding: [0xb8,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: orq %rax, %gs:255, %rax # encoding: [0x65,0x62,0xf4,0xfc,0x18,0x09,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a= inttoptr i64 255 to ptr addrspace(256)
+ %t = load i64, ptr addrspace(256) %a
+ %or = or i64 %t, 123456
+ ret i64 %or
+}
+
+define i32 @xor32mi_FS() nounwind {
+; CHECK-LABEL: xor32mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: xorl %ecx, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x31,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i32, ptr @tm_nest_level
+ %xor = xor i32 %t, 123456
+ ret i32 %xor
+}
+
+define i32 @xor32mi_GS() {
+; CHECK-LABEL: xor32mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl $123456, %eax # encoding: [0xb8,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: xorl %eax, %gs:255, %eax # encoding: [0x65,0x62,0xf4,0x7c,0x18,0x31,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a= inttoptr i32 255 to ptr addrspace(256)
+ %t = load i32, ptr addrspace(256) %a
+ %xor = xor i32 %t, 123456
+ ret i32 %xor
+}
+
+define i64 @xor64mi_FS() nounwind {
+; CHECK-LABEL: xor64mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: xorq %rcx, tm_nest_level at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x31,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i64, ptr @tm_nest_level
+ %xor = xor i64 %t, 123456
+ ret i64 %xor
+}
+
+define i64 @xor64mi_GS() {
+; CHECK-LABEL: xor64mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl $123456, %eax # encoding: [0xb8,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: xorq %rax, %gs:255, %rax # encoding: [0x65,0x62,0xf4,0xfc,0x18,0x31,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a= inttoptr i64 255 to ptr addrspace(256)
+ %t = load i64, ptr addrspace(256) %a
+ %xor = xor i64 %t, 123456
+ ret i64 %xor
+}
+
+define i32 @and32mi_FS() nounwind {
+; CHECK-LABEL: and32mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: andl %ecx, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x21,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i32, ptr @tm_nest_level
+ %and = and i32 %t, 123456
+ ret i32 %and
+}
+
+define i32 @and32mi_GS() {
+; CHECK-LABEL: and32mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl $123456, %eax # encoding: [0xb8,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: andl %eax, %gs:255, %eax # encoding: [0x65,0x62,0xf4,0x7c,0x18,0x21,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a= inttoptr i32 255 to ptr addrspace(256)
+ %t = load i32, ptr addrspace(256) %a
+ %and = and i32 %t, 123456
+ ret i32 %and
+}
+
+define i64 @and64mi_FS() nounwind {
+; CHECK-LABEL: and64mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: movq tm_nest_level at TPOFF(%rax), %rax # encoding: [0x48,0x8b,0x80,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 3, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: andl $123456, %eax, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe0,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i64, ptr @tm_nest_level
+ %and = and i64 %t, 123456
+ ret i64 %and
+}
+
+define i64 @and64mi_GS() {
+; CHECK-LABEL: and64mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq %gs:255, %rax # encoding: [0x65,0x48,0x8b,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: andl $123456, %eax, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe0,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a= inttoptr i64 255 to ptr addrspace(256)
+ %t = load i64, ptr addrspace(256) %a
+ %and = and i64 %t, 123456
+ ret i64 %and
+}
+
+define i32 @adc32mi_FS(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: adc32mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: subl %edi, %esi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x29,0xfe]
+; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: adcl %ecx, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x11,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i32, ptr @tm_nest_level
+ %s = add i32 %t, 123456
+ %k = icmp ugt i32 %x, %y
+ %z = zext i1 %k to i32
+ %r = add i32 %s, %z
+ ret i32 %r
+}
+
+define i32 @adc32mi_GS(i32 %x, i32 %y) {
+; CHECK-LABEL: adc32mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subl %edi, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xfe]
+; CHECK-NEXT: movl $123456, %eax # encoding: [0xb8,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: adcl %eax, %gs:255, %eax # encoding: [0x65,0x62,0xf4,0x7c,0x18,0x11,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a = inttoptr i32 255 to ptr addrspace(256)
+ %t = load i32, ptr addrspace(256) %a
+ %s = add i32 %t, 123456
+ %k = icmp ugt i32 %x, %y
+ %z = zext i1 %k to i32
+ %r = add i32 %s, %z
+ ret i32 %r
+}
+
+define i64 @adc64mi_FS(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: adc64mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: subq %rdi, %rsi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x29,0xfe]
+; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: adcq %rcx, tm_nest_level at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x11,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i64, ptr @tm_nest_level
+ %s = add i64 %t, 123456
+ %k = icmp ugt i64 %x, %y
+ %z = zext i1 %k to i64
+ %r = add i64 %s, %z
+ ret i64 %r
+}
+
+define i64 @adc64mi_GS(i64 %x, i64 %y) {
+; CHECK-LABEL: adc64mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subq %rdi, %rsi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xfe]
+; CHECK-NEXT: movl $123456, %eax # encoding: [0xb8,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: # imm = 0x1E240
+; CHECK-NEXT: adcq %rax, %gs:255, %rax # encoding: [0x65,0x62,0xf4,0xfc,0x18,0x11,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a = inttoptr i64 255 to ptr addrspace(256)
+ %t = load i64, ptr addrspace(256) %a
+ %s = add i64 %t, 123456
+ %k = icmp ugt i64 %x, %y
+ %z = zext i1 %k to i64
+ %r = add i64 %s, %z
+ ret i64 %r
+}
+
+define i32 @sbb32mi_FS(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: sbb32mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: subl %edi, %esi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x29,0xfe]
+; CHECK-NEXT: sbbl $0, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x98,A,A,A,A,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: addl $-123456, %eax, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xc0,0xc0,0x1d,0xfe,0xff]
+; CHECK-NEXT: # imm = 0xFFFE1DC0
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i32, ptr @tm_nest_level
+ %s = sub i32 %t, 123456
+ %k = icmp ugt i32 %x, %y
+ %z = zext i1 %k to i32
+ %r = sub i32 %s, %z
+ ret i32 %r
+}
+
+define i32 @sbb32mi_GS(i32 %x, i32 %y) {
+; CHECK-LABEL: sbb32mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl %gs:255, %eax # encoding: [0x65,0x8b,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: subl %edi, %esi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x29,0xfe]
+; CHECK-NEXT: sbbl $0, %eax, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xd8,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: addl $-123456, %eax, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xc0,0xc0,0x1d,0xfe,0xff]
+; CHECK-NEXT: # imm = 0xFFFE1DC0
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a= inttoptr i32 255 to ptr addrspace(256)
+ %t = load i32, ptr addrspace(256) %a
+ %s = sub i32 %t, 123456
+ %k = icmp ugt i32 %x, %y
+ %z = zext i1 %k to i32
+ %r = sub i32 %s, %z
+ ret i32 %r
+}
+
+define i64 @sbb64mi_FS(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: sbb64mi_FS:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: subq %rdi, %rsi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x29,0xfe]
+; CHECK-NEXT: sbbq $0, tm_nest_level at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x98,A,A,A,A,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: addq $-123456, %rax, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xc0,0xc0,0x1d,0xfe,0xff]
+; CHECK-NEXT: # imm = 0xFFFE1DC0
+; CHECK-NEXT: retq # encoding: [0xc3]
+
+ %t = load i64, ptr @tm_nest_level
+ %s = sub i64 %t, 123456
+ %k = icmp ugt i64 %x, %y
+ %z = zext i1 %k to i64
+ %r = sub i64 %s, %z
+ ret i64 %r
+}
+
+define i64 @sbb64mi_GS(i64 %x, i64 %y) {
+; CHECK-LABEL: sbb64mi_GS:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq %gs:255, %rax # encoding: [0x65,0x48,0x8b,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: subq %rdi, %rsi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x29,0xfe]
+; CHECK-NEXT: sbbq $0, %rax, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xd8,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: addq $-123456, %rax, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xc0,0xc0,0x1d,0xfe,0xff]
+; CHECK-NEXT: # imm = 0xFFFE1DC0
+; CHECK-NEXT: retq # encoding: [0xc3]
+entry:
+ %a= inttoptr i64 255 to ptr addrspace(256)
+ %t = load i64, ptr addrspace(256) %a
+ %s = sub i64 %t, 123456
+ %k = icmp ugt i64 %x, %y
+ %z = zext i1 %k to i64
+ %r = sub i64 %s, %z
+ ret i64 %r
+}
>From 105b9762c804574a2ffd5068da866de41b2f8ff8 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Mon, 15 Jan 2024 22:01:38 -0800
Subject: [PATCH 2/7] add omit test for and
---
llvm/test/CodeGen/X86/apx/and.ll | 595 +++++++++++++++++++++++++++++++
1 file changed, 595 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/apx/and.ll
diff --git a/llvm/test/CodeGen/X86/apx/and.ll b/llvm/test/CodeGen/X86/apx/and.ll
new file mode 100644
index 00000000000000..2a8875d094ba25
--- /dev/null
+++ b/llvm/test/CodeGen/X86/apx/and.ll
@@ -0,0 +1,595 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s
+
+define i8 @and8rr(i8 noundef %a, i8 noundef %b) {
+; CHECK-LABEL: and8rr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl %esi, %edi, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i8 %a, %b
+ ret i8 %and
+}
+
+define i16 @and16rr(i16 noundef %a, i16 noundef %b) {
+; CHECK-LABEL: and16rr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl %esi, %edi, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i16 %a, %b
+ ret i16 %and
+}
+
+define i32 @and32rr(i32 noundef %a, i32 noundef %b) {
+; CHECK-LABEL: and32rr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl %esi, %edi, %eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i32 %a, %b
+ ret i32 %and
+}
+
+define i64 @and64rr(i64 noundef %a, i64 noundef %b) {
+; CHECK-LABEL: and64rr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andq %rsi, %rdi, %rax
+; CHECK-NEXT: retq
+entry:
+ %and = and i64 %a, %b
+ ret i64 %and
+}
+
+define i8 @and8rm(i8 noundef %a, ptr %b) {
+; CHECK-LABEL: and8rm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andb (%rsi), %dil, %al
+; CHECK-NEXT: retq
+entry:
+ %t = load i8, ptr %b
+ %and = and i8 %a, %t
+ ret i8 %and
+}
+
+define i16 @and16rm(i16 noundef %a, ptr %b) {
+; CHECK-LABEL: and16rm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andw (%rsi), %di, %ax
+; CHECK-NEXT: retq
+entry:
+ %t = load i16, ptr %b
+ %and = and i16 %a, %t
+ ret i16 %and
+}
+
+define i32 @and32rm(i32 noundef %a, ptr %b) {
+; CHECK-LABEL: and32rm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl (%rsi), %edi, %eax
+; CHECK-NEXT: retq
+entry:
+ %t = load i32, ptr %b
+ %and = and i32 %a, %t
+ ret i32 %and
+}
+
+define i64 @and64rm(i64 noundef %a, ptr %b) {
+; CHECK-LABEL: and64rm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andq (%rsi), %rdi, %rax
+; CHECK-NEXT: retq
+entry:
+ %t = load i64, ptr %b
+ %and = and i64 %a, %t
+ ret i64 %and
+}
+
+define i16 @and16ri8(i16 noundef %a) {
+; CHECK-LABEL: and16ri8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123, %edi, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i16 %a, 123
+ ret i16 %and
+}
+
+define i32 @and32ri8(i32 noundef %a) {
+; CHECK-LABEL: and32ri8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123, %edi, %eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i32 %a, 123
+ ret i32 %and
+}
+
+define i64 @and64ri8(i64 noundef %a) {
+; CHECK-LABEL: and64ri8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123, %edi, %eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i64 %a, 123
+ ret i64 %and
+}
+
+define i8 @and8ri(i8 noundef %a) {
+; CHECK-LABEL: and8ri:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andb $123, %dil, %al
+; CHECK-NEXT: retq
+entry:
+ %and = and i8 %a, 123
+ ret i8 %and
+}
+
+define i16 @and16ri(i16 noundef %a) {
+; CHECK-LABEL: and16ri:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $1234, %edi, %eax # imm = 0x4D2
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %and = and i16 %a, 1234
+ ret i16 %and
+}
+
+define i32 @and32ri(i32 noundef %a) {
+; CHECK-LABEL: and32ri:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123456, %edi, %eax # imm = 0x1E240
+; CHECK-NEXT: retq
+entry:
+ %and = and i32 %a, 123456
+ ret i32 %and
+}
+
+define i64 @and64ri(i64 noundef %a) {
+; CHECK-LABEL: and64ri:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123456, %edi, %eax # imm = 0x1E240
+; CHECK-NEXT: retq
+entry:
+ %and = and i64 %a, 123456
+ ret i64 %and
+}
+
+define i8 @and8mr(ptr %a, i8 noundef %b) {
+; CHECK-LABEL: and8mr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andb %sil, (%rdi), %al
+; CHECK-NEXT: retq
+entry:
+ %t= load i8, ptr %a
+ %and = and i8 %t, %b
+ ret i8 %and
+}
+
+define i16 @and16mr(ptr %a, i16 noundef %b) {
+; CHECK-LABEL: and16mr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andw %si, (%rdi), %ax
+; CHECK-NEXT: retq
+entry:
+ %t= load i16, ptr %a
+ %and = and i16 %t, %b
+ ret i16 %and
+}
+
+define i32 @and32mr(ptr %a, i32 noundef %b) {
+; CHECK-LABEL: and32mr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl %esi, (%rdi), %eax
+; CHECK-NEXT: retq
+entry:
+ %t= load i32, ptr %a
+ %and = and i32 %t, %b
+ ret i32 %and
+}
+
+define i64 @and64mr(ptr %a, i64 noundef %b) {
+; CHECK-LABEL: and64mr:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andq %rsi, (%rdi), %rax
+; CHECK-NEXT: retq
+entry:
+ %t= load i64, ptr %a
+ %and = and i64 %t, %b
+ ret i64 %and
+}
+
+define i16 @and16mi8(ptr %a) {
+; CHECK-LABEL: and16mi8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movzwl (%rdi), %eax
+; CHECK-NEXT: andl $123, %eax, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %t= load i16, ptr %a
+ %and = and i16 %t, 123
+ ret i16 %and
+}
+
+define i32 @and32mi8(ptr %a) {
+; CHECK-LABEL: and32mi8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123, (%rdi), %eax
+; CHECK-NEXT: retq
+entry:
+ %t= load i32, ptr %a
+ %and = and i32 %t, 123
+ ret i32 %and
+}
+
+define i64 @and64mi8(ptr %a) {
+; CHECK-LABEL: and64mi8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq (%rdi), %rax
+; CHECK-NEXT: andl $123, %eax, %eax
+; CHECK-NEXT: retq
+entry:
+ %t= load i64, ptr %a
+ %and = and i64 %t, 123
+ ret i64 %and
+}
+
+define i8 @and8mi(ptr %a) {
+; CHECK-LABEL: and8mi:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andb $123, (%rdi), %al
+; CHECK-NEXT: retq
+entry:
+ %t= load i8, ptr %a
+ %and = and i8 %t, 123
+ ret i8 %and
+}
+
+define i16 @and16mi(ptr %a) {
+; CHECK-LABEL: and16mi:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movzwl (%rdi), %eax
+; CHECK-NEXT: andl $1234, %eax, %eax # imm = 0x4D2
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %t= load i16, ptr %a
+ %and = and i16 %t, 1234
+ ret i16 %and
+}
+
+define i32 @and32mi(ptr %a) {
+; CHECK-LABEL: and32mi:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123456, (%rdi), %eax # imm = 0x1E240
+; CHECK-NEXT: retq
+entry:
+ %t= load i32, ptr %a
+ %and = and i32 %t, 123456
+ ret i32 %and
+}
+
+define i64 @and64mi(ptr %a) {
+; CHECK-LABEL: and64mi:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq (%rdi), %rax
+; CHECK-NEXT: andl $123456, %eax, %eax # imm = 0x1E240
+; CHECK-NEXT: retq
+entry:
+ %t= load i64, ptr %a
+ %and = and i64 %t, 123456
+ ret i64 %and
+}
+
+ at d64 = dso_local global i64 0
+
+define i1 @andflag8rr(i8 %a, i8 %b) {
+; CHECK-LABEL: andflag8rr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: notb %sil, %al
+; CHECK-NEXT: andb %al, %dil, %cl
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movb %cl, d64(%rip)
+; CHECK-NEXT: retq
+ %xor = xor i8 %b, -1
+ %v0 = and i8 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i8 %v0, 0
+ store i8 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag16rr(i16 %a, i16 %b) {
+; CHECK-LABEL: andflag16rr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: notl %esi, %eax
+; CHECK-NEXT: andw %ax, %di, %cx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movw %cx, d64(%rip)
+; CHECK-NEXT: retq
+ %xor = xor i16 %b, -1
+ %v0 = and i16 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i16 %v0, 0
+ store i16 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag32rr(i32 %a, i32 %b) {
+; CHECK-LABEL: andflag32rr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andl %esi, %edi, %ecx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movl %ecx, d64(%rip)
+; CHECK-NEXT: retq
+ %v0 = and i32 %a, %b ; 0xff << 50
+ %v1 = icmp eq i32 %v0, 0
+ store i32 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag64rr(i64 %a, i64 %b) {
+; CHECK-LABEL: andflag64rr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andq %rsi, %rdi, %rcx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movq %rcx, d64(%rip)
+; CHECK-NEXT: retq
+ %v0 = and i64 %a, %b ; 0xff << 50
+ %v1 = icmp eq i64 %v0, 0
+ store i64 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag8rm(ptr %ptr, i8 %b) {
+; CHECK-LABEL: andflag8rm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: notb %sil, %al
+; CHECK-NEXT: andb (%rdi), %al, %cl
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movb %cl, d64(%rip)
+; CHECK-NEXT: retq
+ %a = load i8, ptr %ptr
+ %xor = xor i8 %b, -1
+ %v0 = and i8 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i8 %v0, 0
+ store i8 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag16rm(ptr %ptr, i16 %b) {
+; CHECK-LABEL: andflag16rm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: notl %esi, %eax
+; CHECK-NEXT: andw (%rdi), %ax, %cx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movw %cx, d64(%rip)
+; CHECK-NEXT: retq
+ %a = load i16, ptr %ptr
+ %xor = xor i16 %b, -1
+ %v0 = and i16 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i16 %v0, 0
+ store i16 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag32rm(ptr %ptr, i32 %b) {
+; CHECK-LABEL: andflag32rm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andl (%rdi), %esi, %ecx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movl %ecx, d64(%rip)
+; CHECK-NEXT: retq
+ %a = load i32, ptr %ptr
+ %v0 = and i32 %a, %b ; 0xff << 50
+ %v1 = icmp eq i32 %v0, 0
+ store i32 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag64rm(ptr %ptr, i64 %b) {
+; CHECK-LABEL: andflag64rm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andq (%rdi), %rsi, %rcx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movq %rcx, d64(%rip)
+; CHECK-NEXT: retq
+ %a = load i64, ptr %ptr
+ %v0 = and i64 %a, %b ; 0xff << 50
+ %v1 = icmp eq i64 %v0, 0
+ store i64 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag8ri(i8 %a) {
+; CHECK-LABEL: andflag8ri:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andb $-124, %dil, %cl
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movb %cl, d64(%rip)
+; CHECK-NEXT: retq
+ %xor = xor i8 123, -1
+ %v0 = and i8 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i8 %v0, 0
+ store i8 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag16ri(i16 %a) {
+; CHECK-LABEL: andflag16ri:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andw $-1235, %di, %cx # imm = 0xFB2D
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movw %cx, d64(%rip)
+; CHECK-NEXT: retq
+ %xor = xor i16 1234, -1
+ %v0 = and i16 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i16 %v0, 0
+ store i16 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag32ri(i32 %a) {
+; CHECK-LABEL: andflag32ri:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andl $123456, %edi, %ecx # imm = 0x1E240
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movl %ecx, d64(%rip)
+; CHECK-NEXT: retq
+ %v0 = and i32 %a, 123456 ; 0xff << 50
+ %v1 = icmp eq i32 %v0, 0
+ store i32 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag64ri(i64 %a) {
+; CHECK-LABEL: andflag64ri:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andq $123456, %rdi, %rcx # imm = 0x1E240
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movq %rcx, d64(%rip)
+; CHECK-NEXT: retq
+ %v0 = and i64 %a, 123456 ; 0xff << 50
+ %v1 = icmp eq i64 %v0, 0
+ store i64 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag16ri8(i16 %a) {
+; CHECK-LABEL: andflag16ri8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andw $-124, %di, %cx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movw %cx, d64(%rip)
+; CHECK-NEXT: retq
+ %xor = xor i16 123, -1
+ %v0 = and i16 %a, %xor ; 0xff << 50
+ %v1 = icmp eq i16 %v0, 0
+ store i16 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag32ri8(i32 %a) {
+; CHECK-LABEL: andflag32ri8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andl $123, %edi, %ecx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movl %ecx, d64(%rip)
+; CHECK-NEXT: retq
+ %v0 = and i32 %a, 123 ; 0xff << 50
+ %v1 = icmp eq i32 %v0, 0
+ store i32 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define i1 @andflag64ri8(i64 %a) {
+; CHECK-LABEL: andflag64ri8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andq $123, %rdi, %rcx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: movq %rcx, d64(%rip)
+; CHECK-NEXT: retq
+ %v0 = and i64 %a, 123 ; 0xff << 50
+ %v1 = icmp eq i64 %v0, 0
+ store i64 %v0, ptr @d64
+ ret i1 %v1
+}
+
+define void @and8mr_legacy(ptr %a, i8 noundef %b) {
+; CHECK-LABEL: and8mr_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andb %sil, (%rdi)
+; CHECK-NEXT: retq
+entry:
+ %t= load i8, ptr %a
+ %and = and i8 %t, %b
+ store i8 %and, ptr %a
+ ret void
+}
+
+define void @and16mr_legacy(ptr %a, i16 noundef %b) {
+; CHECK-LABEL: and16mr_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andw %si, (%rdi)
+; CHECK-NEXT: retq
+entry:
+ %t= load i16, ptr %a
+ %and = and i16 %t, %b
+ store i16 %and, ptr %a
+ ret void
+}
+
+define void @and32mr_legacy(ptr %a, i32 noundef %b) {
+; CHECK-LABEL: and32mr_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl %esi, (%rdi)
+; CHECK-NEXT: retq
+entry:
+ %t= load i32, ptr %a
+ %and = and i32 %t, %b
+ store i32 %and, ptr %a
+ ret void
+}
+
+define void @and64mr_legacy(ptr %a, i64 noundef %b) {
+; CHECK-LABEL: and64mr_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andq %rsi, (%rdi)
+; CHECK-NEXT: retq
+entry:
+ %t= load i64, ptr %a
+ %and = and i64 %t, %b
+ store i64 %and, ptr %a
+ ret void
+}
+
+define void @and8mi_legacy(ptr %a) {
+; CHECK-LABEL: and8mi_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andb $123, (%rdi)
+; CHECK-NEXT: retq
+entry:
+ %t= load i8, ptr %a
+ %and = and i8 %t, 123
+ store i8 %and, ptr %a
+ ret void
+}
+
+define void @and16mi_legacy(ptr %a) {
+; CHECK-LABEL: and16mi_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andw $1234, (%rdi) # imm = 0x4D2
+; CHECK-NEXT: retq
+entry:
+ %t= load i16, ptr %a
+ %and = and i16 %t, 1234
+ store i16 %and, ptr %a
+ ret void
+}
+
+define void @and32mi_legacy(ptr %a) {
+; CHECK-LABEL: and32mi_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andl $123456, (%rdi) # imm = 0x1E240
+; CHECK-NEXT: retq
+entry:
+ %t= load i32, ptr %a
+ %and = and i32 %t, 123456
+ store i32 %and, ptr %a
+ ret void
+}
+
+define void @and64mi_legacy(ptr %a) {
+; CHECK-LABEL: and64mi_legacy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andq $123456, (%rdi) # imm = 0x1E240
+; CHECK-NEXT: retq
+entry:
+ %t= load i64, ptr %a
+ %and = and i64 %t, 123456
+ store i64 %and, ptr %a
+ ret void
+}
>From 9fa72a2760dbafb1b19461516897377718151cb4 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Mon, 15 Jan 2024 22:04:21 -0800
Subject: [PATCH 3/7] rename test
---
...ix-with-ndd.ll => invalid-ndd-encoding-with-segment-prefix.ll} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename llvm/test/CodeGen/X86/apx/{invalid-segment-prefix-with-ndd.ll => invalid-ndd-encoding-with-segment-prefix.ll} (100%)
diff --git a/llvm/test/CodeGen/X86/apx/invalid-segment-prefix-with-ndd.ll b/llvm/test/CodeGen/X86/apx/invalid-ndd-encoding-with-segment-prefix.ll
similarity index 100%
rename from llvm/test/CodeGen/X86/apx/invalid-segment-prefix-with-ndd.ll
rename to llvm/test/CodeGen/X86/apx/invalid-ndd-encoding-with-segment-prefix.ll
>From b22be902df0edc9ebc5113653370dda5f1206813 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Mon, 15 Jan 2024 22:15:07 -0800
Subject: [PATCH 4/7] restore debug change
---
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 1b7d48f69ad5dd..c08d48d9beb082 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2911,10 +2911,8 @@ bool X86DAGToDAGISel::selectAddr(SDNode *Parent, SDValue N, SDValue &Base,
AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
if (AddrSpace == X86AS::FS)
AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
- if (AddrSpace == X86AS::SS){
- llvm_unreachable("debug");
+ if (AddrSpace == X86AS::SS)
AM.Segment = CurDAG->getRegister(X86::SS, MVT::i16);
- }
}
// Save the DL and VT before calling matchAddress, it can invalidate N.
>From 7d82fe8a58af6bc0b1a878a46d26a4fa387e2ed5 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Mon, 15 Jan 2024 23:27:30 -0800
Subject: [PATCH 5/7] add test for ss prefix
---
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 4 +-
llvm/lib/Target/X86/X86InstrInfo.cpp | 3 +-
...nvalid-ndd-encoding-with-segment-prefix.ll | 164 +++++++++---------
3 files changed, 88 insertions(+), 83 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index c08d48d9beb082..44d42ce929797b 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2950,8 +2950,8 @@ bool X86DAGToDAGISel::selectNoSegADDRAddr(SDNode *Parent, SDValue N,
if (matchAddress(N, AM))
return false;
- // FS prefix.
- if (AM.SymbolFlags == 13)
+ // TLS variable using FS prefix in linux.
+ if (AM.SymbolFlags == X86II::MO_TPOFF)
return false;
getAddressOperands(AM, DL, VT, Base, Scale, Index, Disp, Segment);
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 6662021c66ed1c..5ddd9fc6cc2ae1 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -7254,7 +7254,8 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
// MI_ND Instructions with 32 bit imm would exceed maximum code length if they
// need segment register prefix.
if (MOs.size() == X86::AddrNumOperands &&
- (MOs[4].getReg() == X86::GS || MOs[4].getReg() == X86::FS))
+ (MOs[4].getReg() == X86::GS || MOs[4].getReg() == X86::FS ||
+ MOs[4].getReg() == X86::SS))
switch (MI.getOpcode()) {
default:
break;
diff --git a/llvm/test/CodeGen/X86/apx/invalid-ndd-encoding-with-segment-prefix.ll b/llvm/test/CodeGen/X86/apx/invalid-ndd-encoding-with-segment-prefix.ll
index 47439c41074fb7..b6d22abf969d44 100644
--- a/llvm/test/CodeGen/X86/apx/invalid-ndd-encoding-with-segment-prefix.ll
+++ b/llvm/test/CodeGen/X86/apx/invalid-ndd-encoding-with-segment-prefix.ll
@@ -1,18 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs --show-mc-encoding | FileCheck %s
- at tm_nest_level = internal thread_local global i32 0
+ at tm_intern = internal thread_local global i32 0
+ at tm_extern = external thread_local global i32
define i32 @add32mi_FS() nounwind {
; CHECK-LABEL: add32mi_FS:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: addl %ecx, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x01,0x88,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: addl %ecx, tm_intern at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x01,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_intern at TPOFF, kind: reloc_signed_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i32, ptr @tm_nest_level
+ %t = load i32, ptr @tm_intern
%add = add nsw i32 %t, 123456
ret i32 %add
}
@@ -37,11 +38,11 @@ define i64 @add64mi_FS() nounwind {
; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: addq %rcx, tm_nest_level at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x01,0x88,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: addq %rcx, tm_intern at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x01,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_intern at TPOFF, kind: reloc_signed_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i64, ptr @tm_nest_level
+ %t = load i64, ptr @tm_intern
%add = add nsw i64 %t, 123456
ret i64 %add
}
@@ -66,11 +67,11 @@ define i32 @sub32mi_FS() nounwind {
; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
; CHECK-NEXT: movl $-123456, %ecx # encoding: [0xb9,0xc0,0x1d,0xfe,0xff]
; CHECK-NEXT: # imm = 0xFFFE1DC0
-; CHECK-NEXT: addl %ecx, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x01,0x88,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: addl %ecx, tm_intern at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x01,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_intern at TPOFF, kind: reloc_signed_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i32, ptr @tm_nest_level
+ %t = load i32, ptr @tm_intern
%sub = sub nsw i32 %t, 123456
ret i32 %sub
}
@@ -95,25 +96,25 @@ define i64 @sub64mi_FS() nounwind {
; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
; CHECK-NEXT: movq $-123456, %rcx # encoding: [0x48,0xc7,0xc1,0xc0,0x1d,0xfe,0xff]
; CHECK-NEXT: # imm = 0xFFFE1DC0
-; CHECK-NEXT: addq %rcx, tm_nest_level at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x01,0x88,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: addq %rcx, tm_intern at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x01,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_intern at TPOFF, kind: reloc_signed_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i64, ptr @tm_nest_level
+ %t = load i64, ptr @tm_intern
%sub = sub nsw i64 %t, 123456
ret i64 %sub
}
-define i64 @sub64mi_GS() {
-; CHECK-LABEL: sub64mi_GS:
+define i64 @sub64mi_FS2() {
+; CHECK-LABEL: sub64mi_FS2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq $-123456, %rax # encoding: [0x48,0xc7,0xc0,0xc0,0x1d,0xfe,0xff]
; CHECK-NEXT: # imm = 0xFFFE1DC0
-; CHECK-NEXT: addq %rax, %gs:255, %rax # encoding: [0x65,0x62,0xf4,0xfc,0x18,0x01,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: addq %rax, %fs:255, %rax # encoding: [0x64,0x62,0xf4,0xfc,0x18,0x01,0x04,0x25,0xff,0x00,0x00,0x00]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
- %a= inttoptr i64 255 to ptr addrspace(256)
- %t = load i64, ptr addrspace(256) %a
+ %a= inttoptr i64 255 to ptr addrspace(257)
+ %t = load i64, ptr addrspace(257) %a
%sub = sub nsw i64 %t, 123456
ret i64 %sub
}
@@ -124,11 +125,11 @@ define i32 @or32mi_FS() nounwind {
; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: orl %ecx, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x09,0x88,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: orl %ecx, tm_intern at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x09,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_intern at TPOFF, kind: reloc_signed_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i32, ptr @tm_nest_level
+ %t = load i32, ptr @tm_intern
%or = or i32 %t, 123456
ret i32 %or
}
@@ -153,11 +154,11 @@ define i64 @or64mi_FS() nounwind {
; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: orq %rcx, tm_nest_level at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x09,0x88,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: orq %rcx, tm_intern at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x09,0x88,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 6, value: tm_intern at TPOFF, kind: reloc_signed_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i64, ptr @tm_nest_level
+ %t = load i64, ptr @tm_intern
%or = or i64 %t, 123456
ret i64 %or
}
@@ -179,14 +180,14 @@ entry:
define i32 @xor32mi_FS() nounwind {
; CHECK-LABEL: xor32mi_FS:
; CHECK: # %bb.0:
-; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
-; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: movq tm_extern at GOTTPOFF(%rip), %rax # encoding: [0x48,0x8b,0x05,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 3, value: tm_extern at GOTTPOFF-4, kind: reloc_riprel_4byte_movq_load
+; CHECK-NEXT: movq %fs:0, %rcx # encoding: [0x64,0x48,0x8b,0x0c,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: xorl $123456, (%rcx,%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x34,0x01,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: xorl %ecx, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x31,0x88,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i32, ptr @tm_nest_level
+ %t = load i32, ptr @tm_extern
%xor = xor i32 %t, 123456
ret i32 %xor
}
@@ -208,28 +209,28 @@ entry:
define i64 @xor64mi_FS() nounwind {
; CHECK-LABEL: xor64mi_FS:
; CHECK: # %bb.0:
-; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
-; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: movq tm_extern at GOTTPOFF(%rip), %rax # encoding: [0x48,0x8b,0x05,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 3, value: tm_extern at GOTTPOFF-4, kind: reloc_riprel_4byte_movq_load
+; CHECK-NEXT: movq %fs:0, %rcx # encoding: [0x64,0x48,0x8b,0x0c,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: xorq $123456, (%rcx,%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x34,0x01,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: xorq %rcx, tm_nest_level at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x31,0x88,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i64, ptr @tm_nest_level
+ %t = load i64, ptr @tm_extern
%xor = xor i64 %t, 123456
ret i64 %xor
}
-define i64 @xor64mi_GS() {
-; CHECK-LABEL: xor64mi_GS:
+define i64 @xor64mi_FS2() {
+; CHECK-LABEL: xor64mi_FS2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $123456, %eax # encoding: [0xb8,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: xorq %rax, %gs:255, %rax # encoding: [0x65,0x62,0xf4,0xfc,0x18,0x31,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: xorq %rax, %fs:255, %rax # encoding: [0x64,0x62,0xf4,0xfc,0x18,0x31,0x04,0x25,0xff,0x00,0x00,0x00]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
- %a= inttoptr i64 255 to ptr addrspace(256)
- %t = load i64, ptr addrspace(256) %a
+ %a= inttoptr i64 255 to ptr addrspace(257)
+ %t = load i64, ptr addrspace(257) %a
%xor = xor i64 %t, 123456
ret i64 %xor
}
@@ -237,14 +238,14 @@ entry:
define i32 @and32mi_FS() nounwind {
; CHECK-LABEL: and32mi_FS:
; CHECK: # %bb.0:
-; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
-; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: movq tm_extern at GOTTPOFF(%rip), %rax # encoding: [0x48,0x8b,0x05,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 3, value: tm_extern at GOTTPOFF-4, kind: reloc_riprel_4byte_movq_load
+; CHECK-NEXT: movq %fs:0, %rcx # encoding: [0x64,0x48,0x8b,0x0c,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: andl $123456, (%rcx,%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x24,0x01,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: andl %ecx, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x21,0x88,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i32, ptr @tm_nest_level
+ %t = load i32, ptr @tm_extern
%and = and i32 %t, 123456
ret i32 %and
}
@@ -266,28 +267,29 @@ entry:
define i64 @and64mi_FS() nounwind {
; CHECK-LABEL: and64mi_FS:
; CHECK: # %bb.0:
-; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
-; CHECK-NEXT: movq tm_nest_level at TPOFF(%rax), %rax # encoding: [0x48,0x8b,0x80,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 3, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: movq tm_extern at GOTTPOFF(%rip), %rax # encoding: [0x48,0x8b,0x05,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 3, value: tm_extern at GOTTPOFF-4, kind: reloc_riprel_4byte_movq_load
+; CHECK-NEXT: movq %fs:0, %rcx # encoding: [0x64,0x48,0x8b,0x0c,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: movq (%rcx,%rax), %rax # encoding: [0x48,0x8b,0x04,0x01]
; CHECK-NEXT: andl $123456, %eax, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe0,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i64, ptr @tm_nest_level
+ %t = load i64, ptr @tm_extern
%and = and i64 %t, 123456
ret i64 %and
}
-define i64 @and64mi_GS() {
-; CHECK-LABEL: and64mi_GS:
+define i64 @and64mi_SS() {
+; CHECK-LABEL: and64mi_SS:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq %gs:255, %rax # encoding: [0x65,0x48,0x8b,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: movq %ss:255, %rax # encoding: [0x36,0x48,0x8b,0x04,0x25,0xff,0x00,0x00,0x00]
; CHECK-NEXT: andl $123456, %eax, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe0,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
- %a= inttoptr i64 255 to ptr addrspace(256)
- %t = load i64, ptr addrspace(256) %a
+ %a= inttoptr i64 255 to ptr addrspace(258)
+ %t = load i64, ptr addrspace(258) %a
%and = and i64 %t, 123456
ret i64 %and
}
@@ -295,15 +297,15 @@ entry:
define i32 @adc32mi_FS(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: adc32mi_FS:
; CHECK: # %bb.0:
-; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
-; CHECK-NEXT: subl %edi, %esi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x29,0xfe]
-; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: movq tm_extern at GOTTPOFF(%rip), %rax # encoding: [0x48,0x8b,0x05,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 3, value: tm_extern at GOTTPOFF-4, kind: reloc_riprel_4byte_movq_load
+; CHECK-NEXT: movq %fs:0, %rcx # encoding: [0x64,0x48,0x8b,0x0c,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: subl %edi, %esi, %edx # encoding: [0x62,0xf4,0x6c,0x18,0x29,0xfe]
+; CHECK-NEXT: adcl $123456, (%rcx,%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x14,0x01,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: adcl %ecx, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x11,0x88,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i32, ptr @tm_nest_level
+ %t = load i32, ptr @tm_extern
%s = add i32 %t, 123456
%k = icmp ugt i32 %x, %y
%z = zext i1 %k to i32
@@ -332,15 +334,15 @@ entry:
define i64 @adc64mi_FS(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: adc64mi_FS:
; CHECK: # %bb.0:
-; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
-; CHECK-NEXT: subq %rdi, %rsi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x29,0xfe]
-; CHECK-NEXT: movl $123456, %ecx # encoding: [0xb9,0x40,0xe2,0x01,0x00]
+; CHECK-NEXT: movq tm_extern at GOTTPOFF(%rip), %rax # encoding: [0x48,0x8b,0x05,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 3, value: tm_extern at GOTTPOFF-4, kind: reloc_riprel_4byte_movq_load
+; CHECK-NEXT: movq %fs:0, %rcx # encoding: [0x64,0x48,0x8b,0x0c,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: subq %rdi, %rsi, %rdx # encoding: [0x62,0xf4,0xec,0x18,0x29,0xfe]
+; CHECK-NEXT: adcq $123456, (%rcx,%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x14,0x01,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: adcq %rcx, tm_nest_level at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x11,0x88,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i64, ptr @tm_nest_level
+ %t = load i64, ptr @tm_extern
%s = add i64 %t, 123456
%k = icmp ugt i64 %x, %y
%z = zext i1 %k to i64
@@ -369,15 +371,16 @@ entry:
define i32 @sbb32mi_FS(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: sbb32mi_FS:
; CHECK: # %bb.0:
-; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
-; CHECK-NEXT: subl %edi, %esi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x29,0xfe]
-; CHECK-NEXT: sbbl $0, tm_nest_level at TPOFF(%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x98,A,A,A,A,0x00,0x00,0x00,0x00]
-; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: movq tm_extern at GOTTPOFF(%rip), %rax # encoding: [0x48,0x8b,0x05,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 3, value: tm_extern at GOTTPOFF-4, kind: reloc_riprel_4byte_movq_load
+; CHECK-NEXT: movq %fs:0, %rcx # encoding: [0x64,0x48,0x8b,0x0c,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: subl %edi, %esi, %edx # encoding: [0x62,0xf4,0x6c,0x18,0x29,0xfe]
+; CHECK-NEXT: sbbl $0, (%rcx,%rax), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x1c,0x01,0x00,0x00,0x00,0x00]
; CHECK-NEXT: addl $-123456, %eax, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xc0,0xc0,0x1d,0xfe,0xff]
; CHECK-NEXT: # imm = 0xFFFE1DC0
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i32, ptr @tm_nest_level
+ %t = load i32, ptr @tm_extern
%s = sub i32 %t, 123456
%k = icmp ugt i32 %x, %y
%z = zext i1 %k to i32
@@ -407,15 +410,16 @@ entry:
define i64 @sbb64mi_FS(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: sbb64mi_FS:
; CHECK: # %bb.0:
-; CHECK-NEXT: movq %fs:0, %rax # encoding: [0x64,0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
-; CHECK-NEXT: subq %rdi, %rsi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x29,0xfe]
-; CHECK-NEXT: sbbq $0, tm_nest_level at TPOFF(%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x98,A,A,A,A,0x00,0x00,0x00,0x00]
-; CHECK-NEXT: # fixup A - offset: 6, value: tm_nest_level at TPOFF, kind: reloc_signed_4byte
+; CHECK-NEXT: movq tm_extern at GOTTPOFF(%rip), %rax # encoding: [0x48,0x8b,0x05,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 3, value: tm_extern at GOTTPOFF-4, kind: reloc_riprel_4byte_movq_load
+; CHECK-NEXT: movq %fs:0, %rcx # encoding: [0x64,0x48,0x8b,0x0c,0x25,0x00,0x00,0x00,0x00]
+; CHECK-NEXT: subq %rdi, %rsi, %rdx # encoding: [0x62,0xf4,0xec,0x18,0x29,0xfe]
+; CHECK-NEXT: sbbq $0, (%rcx,%rax), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x1c,0x01,0x00,0x00,0x00,0x00]
; CHECK-NEXT: addq $-123456, %rax, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xc0,0xc0,0x1d,0xfe,0xff]
; CHECK-NEXT: # imm = 0xFFFE1DC0
; CHECK-NEXT: retq # encoding: [0xc3]
- %t = load i64, ptr @tm_nest_level
+ %t = load i64, ptr @tm_extern
%s = sub i64 %t, 123456
%k = icmp ugt i64 %x, %y
%z = zext i1 %k to i64
@@ -423,18 +427,18 @@ define i64 @sbb64mi_FS(i64 %x, i64 %y) nounwind {
ret i64 %r
}
-define i64 @sbb64mi_GS(i64 %x, i64 %y) {
-; CHECK-LABEL: sbb64mi_GS:
+define i64 @sbb64mi_SS(i64 %x, i64 %y) {
+; CHECK-LABEL: sbb64mi_SS:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq %gs:255, %rax # encoding: [0x65,0x48,0x8b,0x04,0x25,0xff,0x00,0x00,0x00]
+; CHECK-NEXT: movq %ss:255, %rax # encoding: [0x36,0x48,0x8b,0x04,0x25,0xff,0x00,0x00,0x00]
; CHECK-NEXT: subq %rdi, %rsi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x29,0xfe]
; CHECK-NEXT: sbbq $0, %rax, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xd8,0x00,0x00,0x00,0x00]
; CHECK-NEXT: addq $-123456, %rax, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xc0,0xc0,0x1d,0xfe,0xff]
; CHECK-NEXT: # imm = 0xFFFE1DC0
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
- %a= inttoptr i64 255 to ptr addrspace(256)
- %t = load i64, ptr addrspace(256) %a
+ %a= inttoptr i64 255 to ptr addrspace(258)
+ %t = load i64, ptr addrspace(258) %a
%s = sub i64 %t, 123456
%k = icmp ugt i64 %x, %y
%z = zext i1 %k to i64
>From fbeff648a68073ba30789fb86cc1dac061faabc2 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Mon, 15 Jan 2024 23:46:13 -0800
Subject: [PATCH 6/7] restore debug change
---
llvm/lib/Target/X86/X86InstrUtils.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/X86/X86InstrUtils.td b/llvm/lib/Target/X86/X86InstrUtils.td
index d28aac4038a469..729b385b376781 100644
--- a/llvm/lib/Target/X86/X86InstrUtils.td
+++ b/llvm/lib/Target/X86/X86InstrUtils.td
@@ -1208,7 +1208,7 @@ class BinOpMIF_RF<bits<8> o, string m, X86TypeInfo t, SDNode node, Format f, Com
Sched<[WriteADC.Folded, WriteADC.ReadAfterFold]>, DefEFLAGS, UseEFLAGS, NDD<1>;
// BinOpMIF_MF - Instructions that read "[mem], imm", write "[mem]" and
// read/write EFLAGS.
-class BinOpMIF_MF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, Format f>
+class BinOpMIF_MF<bits<8> o, string m, X86TypeInfo t, SDNode node, Format f>
: BinOpMI<o, m, binop_args, t, f, (outs),
[(store (node (t.VT (load addr:$src1)),
t.ImmOperator:$src2, EFLAGS), addr:$src1), (implicit EFLAGS)]>,
>From e0b2fa67371bb928f7500a3e5f37e9308c8d61ba Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Tue, 16 Jan 2024 02:16:30 -0800
Subject: [PATCH 7/7] remove test and
---
llvm/test/CodeGen/X86/apx/and.ll | 595 -------------------------------
1 file changed, 595 deletions(-)
delete mode 100644 llvm/test/CodeGen/X86/apx/and.ll
diff --git a/llvm/test/CodeGen/X86/apx/and.ll b/llvm/test/CodeGen/X86/apx/and.ll
deleted file mode 100644
index 2a8875d094ba25..00000000000000
--- a/llvm/test/CodeGen/X86/apx/and.ll
+++ /dev/null
@@ -1,595 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s
-
-define i8 @and8rr(i8 noundef %a, i8 noundef %b) {
-; CHECK-LABEL: and8rr:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl %esi, %edi, %eax
-; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: retq
-entry:
- %and = and i8 %a, %b
- ret i8 %and
-}
-
-define i16 @and16rr(i16 noundef %a, i16 noundef %b) {
-; CHECK-LABEL: and16rr:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl %esi, %edi, %eax
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
-; CHECK-NEXT: retq
-entry:
- %and = and i16 %a, %b
- ret i16 %and
-}
-
-define i32 @and32rr(i32 noundef %a, i32 noundef %b) {
-; CHECK-LABEL: and32rr:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl %esi, %edi, %eax
-; CHECK-NEXT: retq
-entry:
- %and = and i32 %a, %b
- ret i32 %and
-}
-
-define i64 @and64rr(i64 noundef %a, i64 noundef %b) {
-; CHECK-LABEL: and64rr:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andq %rsi, %rdi, %rax
-; CHECK-NEXT: retq
-entry:
- %and = and i64 %a, %b
- ret i64 %and
-}
-
-define i8 @and8rm(i8 noundef %a, ptr %b) {
-; CHECK-LABEL: and8rm:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andb (%rsi), %dil, %al
-; CHECK-NEXT: retq
-entry:
- %t = load i8, ptr %b
- %and = and i8 %a, %t
- ret i8 %and
-}
-
-define i16 @and16rm(i16 noundef %a, ptr %b) {
-; CHECK-LABEL: and16rm:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andw (%rsi), %di, %ax
-; CHECK-NEXT: retq
-entry:
- %t = load i16, ptr %b
- %and = and i16 %a, %t
- ret i16 %and
-}
-
-define i32 @and32rm(i32 noundef %a, ptr %b) {
-; CHECK-LABEL: and32rm:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl (%rsi), %edi, %eax
-; CHECK-NEXT: retq
-entry:
- %t = load i32, ptr %b
- %and = and i32 %a, %t
- ret i32 %and
-}
-
-define i64 @and64rm(i64 noundef %a, ptr %b) {
-; CHECK-LABEL: and64rm:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andq (%rsi), %rdi, %rax
-; CHECK-NEXT: retq
-entry:
- %t = load i64, ptr %b
- %and = and i64 %a, %t
- ret i64 %and
-}
-
-define i16 @and16ri8(i16 noundef %a) {
-; CHECK-LABEL: and16ri8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $123, %edi, %eax
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
-; CHECK-NEXT: retq
-entry:
- %and = and i16 %a, 123
- ret i16 %and
-}
-
-define i32 @and32ri8(i32 noundef %a) {
-; CHECK-LABEL: and32ri8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $123, %edi, %eax
-; CHECK-NEXT: retq
-entry:
- %and = and i32 %a, 123
- ret i32 %and
-}
-
-define i64 @and64ri8(i64 noundef %a) {
-; CHECK-LABEL: and64ri8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $123, %edi, %eax
-; CHECK-NEXT: retq
-entry:
- %and = and i64 %a, 123
- ret i64 %and
-}
-
-define i8 @and8ri(i8 noundef %a) {
-; CHECK-LABEL: and8ri:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andb $123, %dil, %al
-; CHECK-NEXT: retq
-entry:
- %and = and i8 %a, 123
- ret i8 %and
-}
-
-define i16 @and16ri(i16 noundef %a) {
-; CHECK-LABEL: and16ri:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $1234, %edi, %eax # imm = 0x4D2
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
-; CHECK-NEXT: retq
-entry:
- %and = and i16 %a, 1234
- ret i16 %and
-}
-
-define i32 @and32ri(i32 noundef %a) {
-; CHECK-LABEL: and32ri:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $123456, %edi, %eax # imm = 0x1E240
-; CHECK-NEXT: retq
-entry:
- %and = and i32 %a, 123456
- ret i32 %and
-}
-
-define i64 @and64ri(i64 noundef %a) {
-; CHECK-LABEL: and64ri:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $123456, %edi, %eax # imm = 0x1E240
-; CHECK-NEXT: retq
-entry:
- %and = and i64 %a, 123456
- ret i64 %and
-}
-
-define i8 @and8mr(ptr %a, i8 noundef %b) {
-; CHECK-LABEL: and8mr:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andb %sil, (%rdi), %al
-; CHECK-NEXT: retq
-entry:
- %t= load i8, ptr %a
- %and = and i8 %t, %b
- ret i8 %and
-}
-
-define i16 @and16mr(ptr %a, i16 noundef %b) {
-; CHECK-LABEL: and16mr:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andw %si, (%rdi), %ax
-; CHECK-NEXT: retq
-entry:
- %t= load i16, ptr %a
- %and = and i16 %t, %b
- ret i16 %and
-}
-
-define i32 @and32mr(ptr %a, i32 noundef %b) {
-; CHECK-LABEL: and32mr:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl %esi, (%rdi), %eax
-; CHECK-NEXT: retq
-entry:
- %t= load i32, ptr %a
- %and = and i32 %t, %b
- ret i32 %and
-}
-
-define i64 @and64mr(ptr %a, i64 noundef %b) {
-; CHECK-LABEL: and64mr:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andq %rsi, (%rdi), %rax
-; CHECK-NEXT: retq
-entry:
- %t= load i64, ptr %a
- %and = and i64 %t, %b
- ret i64 %and
-}
-
-define i16 @and16mi8(ptr %a) {
-; CHECK-LABEL: and16mi8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movzwl (%rdi), %eax
-; CHECK-NEXT: andl $123, %eax, %eax
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
-; CHECK-NEXT: retq
-entry:
- %t= load i16, ptr %a
- %and = and i16 %t, 123
- ret i16 %and
-}
-
-define i32 @and32mi8(ptr %a) {
-; CHECK-LABEL: and32mi8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $123, (%rdi), %eax
-; CHECK-NEXT: retq
-entry:
- %t= load i32, ptr %a
- %and = and i32 %t, 123
- ret i32 %and
-}
-
-define i64 @and64mi8(ptr %a) {
-; CHECK-LABEL: and64mi8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq (%rdi), %rax
-; CHECK-NEXT: andl $123, %eax, %eax
-; CHECK-NEXT: retq
-entry:
- %t= load i64, ptr %a
- %and = and i64 %t, 123
- ret i64 %and
-}
-
-define i8 @and8mi(ptr %a) {
-; CHECK-LABEL: and8mi:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andb $123, (%rdi), %al
-; CHECK-NEXT: retq
-entry:
- %t= load i8, ptr %a
- %and = and i8 %t, 123
- ret i8 %and
-}
-
-define i16 @and16mi(ptr %a) {
-; CHECK-LABEL: and16mi:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movzwl (%rdi), %eax
-; CHECK-NEXT: andl $1234, %eax, %eax # imm = 0x4D2
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
-; CHECK-NEXT: retq
-entry:
- %t= load i16, ptr %a
- %and = and i16 %t, 1234
- ret i16 %and
-}
-
-define i32 @and32mi(ptr %a) {
-; CHECK-LABEL: and32mi:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $123456, (%rdi), %eax # imm = 0x1E240
-; CHECK-NEXT: retq
-entry:
- %t= load i32, ptr %a
- %and = and i32 %t, 123456
- ret i32 %and
-}
-
-define i64 @and64mi(ptr %a) {
-; CHECK-LABEL: and64mi:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movq (%rdi), %rax
-; CHECK-NEXT: andl $123456, %eax, %eax # imm = 0x1E240
-; CHECK-NEXT: retq
-entry:
- %t= load i64, ptr %a
- %and = and i64 %t, 123456
- ret i64 %and
-}
-
- at d64 = dso_local global i64 0
-
-define i1 @andflag8rr(i8 %a, i8 %b) {
-; CHECK-LABEL: andflag8rr:
-; CHECK: # %bb.0:
-; CHECK-NEXT: notb %sil, %al
-; CHECK-NEXT: andb %al, %dil, %cl
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movb %cl, d64(%rip)
-; CHECK-NEXT: retq
- %xor = xor i8 %b, -1
- %v0 = and i8 %a, %xor ; 0xff << 50
- %v1 = icmp eq i8 %v0, 0
- store i8 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag16rr(i16 %a, i16 %b) {
-; CHECK-LABEL: andflag16rr:
-; CHECK: # %bb.0:
-; CHECK-NEXT: notl %esi, %eax
-; CHECK-NEXT: andw %ax, %di, %cx
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movw %cx, d64(%rip)
-; CHECK-NEXT: retq
- %xor = xor i16 %b, -1
- %v0 = and i16 %a, %xor ; 0xff << 50
- %v1 = icmp eq i16 %v0, 0
- store i16 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag32rr(i32 %a, i32 %b) {
-; CHECK-LABEL: andflag32rr:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andl %esi, %edi, %ecx
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movl %ecx, d64(%rip)
-; CHECK-NEXT: retq
- %v0 = and i32 %a, %b ; 0xff << 50
- %v1 = icmp eq i32 %v0, 0
- store i32 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag64rr(i64 %a, i64 %b) {
-; CHECK-LABEL: andflag64rr:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andq %rsi, %rdi, %rcx
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movq %rcx, d64(%rip)
-; CHECK-NEXT: retq
- %v0 = and i64 %a, %b ; 0xff << 50
- %v1 = icmp eq i64 %v0, 0
- store i64 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag8rm(ptr %ptr, i8 %b) {
-; CHECK-LABEL: andflag8rm:
-; CHECK: # %bb.0:
-; CHECK-NEXT: notb %sil, %al
-; CHECK-NEXT: andb (%rdi), %al, %cl
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movb %cl, d64(%rip)
-; CHECK-NEXT: retq
- %a = load i8, ptr %ptr
- %xor = xor i8 %b, -1
- %v0 = and i8 %a, %xor ; 0xff << 50
- %v1 = icmp eq i8 %v0, 0
- store i8 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag16rm(ptr %ptr, i16 %b) {
-; CHECK-LABEL: andflag16rm:
-; CHECK: # %bb.0:
-; CHECK-NEXT: notl %esi, %eax
-; CHECK-NEXT: andw (%rdi), %ax, %cx
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movw %cx, d64(%rip)
-; CHECK-NEXT: retq
- %a = load i16, ptr %ptr
- %xor = xor i16 %b, -1
- %v0 = and i16 %a, %xor ; 0xff << 50
- %v1 = icmp eq i16 %v0, 0
- store i16 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag32rm(ptr %ptr, i32 %b) {
-; CHECK-LABEL: andflag32rm:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andl (%rdi), %esi, %ecx
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movl %ecx, d64(%rip)
-; CHECK-NEXT: retq
- %a = load i32, ptr %ptr
- %v0 = and i32 %a, %b ; 0xff << 50
- %v1 = icmp eq i32 %v0, 0
- store i32 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag64rm(ptr %ptr, i64 %b) {
-; CHECK-LABEL: andflag64rm:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andq (%rdi), %rsi, %rcx
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movq %rcx, d64(%rip)
-; CHECK-NEXT: retq
- %a = load i64, ptr %ptr
- %v0 = and i64 %a, %b ; 0xff << 50
- %v1 = icmp eq i64 %v0, 0
- store i64 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag8ri(i8 %a) {
-; CHECK-LABEL: andflag8ri:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andb $-124, %dil, %cl
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movb %cl, d64(%rip)
-; CHECK-NEXT: retq
- %xor = xor i8 123, -1
- %v0 = and i8 %a, %xor ; 0xff << 50
- %v1 = icmp eq i8 %v0, 0
- store i8 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag16ri(i16 %a) {
-; CHECK-LABEL: andflag16ri:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andw $-1235, %di, %cx # imm = 0xFB2D
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movw %cx, d64(%rip)
-; CHECK-NEXT: retq
- %xor = xor i16 1234, -1
- %v0 = and i16 %a, %xor ; 0xff << 50
- %v1 = icmp eq i16 %v0, 0
- store i16 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag32ri(i32 %a) {
-; CHECK-LABEL: andflag32ri:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andl $123456, %edi, %ecx # imm = 0x1E240
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movl %ecx, d64(%rip)
-; CHECK-NEXT: retq
- %v0 = and i32 %a, 123456 ; 0xff << 50
- %v1 = icmp eq i32 %v0, 0
- store i32 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag64ri(i64 %a) {
-; CHECK-LABEL: andflag64ri:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andq $123456, %rdi, %rcx # imm = 0x1E240
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movq %rcx, d64(%rip)
-; CHECK-NEXT: retq
- %v0 = and i64 %a, 123456 ; 0xff << 50
- %v1 = icmp eq i64 %v0, 0
- store i64 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag16ri8(i16 %a) {
-; CHECK-LABEL: andflag16ri8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andw $-124, %di, %cx
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movw %cx, d64(%rip)
-; CHECK-NEXT: retq
- %xor = xor i16 123, -1
- %v0 = and i16 %a, %xor ; 0xff << 50
- %v1 = icmp eq i16 %v0, 0
- store i16 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag32ri8(i32 %a) {
-; CHECK-LABEL: andflag32ri8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andl $123, %edi, %ecx
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movl %ecx, d64(%rip)
-; CHECK-NEXT: retq
- %v0 = and i32 %a, 123 ; 0xff << 50
- %v1 = icmp eq i32 %v0, 0
- store i32 %v0, ptr @d64
- ret i1 %v1
-}
-
-define i1 @andflag64ri8(i64 %a) {
-; CHECK-LABEL: andflag64ri8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: andq $123, %rdi, %rcx
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: movq %rcx, d64(%rip)
-; CHECK-NEXT: retq
- %v0 = and i64 %a, 123 ; 0xff << 50
- %v1 = icmp eq i64 %v0, 0
- store i64 %v0, ptr @d64
- ret i1 %v1
-}
-
-define void @and8mr_legacy(ptr %a, i8 noundef %b) {
-; CHECK-LABEL: and8mr_legacy:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andb %sil, (%rdi)
-; CHECK-NEXT: retq
-entry:
- %t= load i8, ptr %a
- %and = and i8 %t, %b
- store i8 %and, ptr %a
- ret void
-}
-
-define void @and16mr_legacy(ptr %a, i16 noundef %b) {
-; CHECK-LABEL: and16mr_legacy:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andw %si, (%rdi)
-; CHECK-NEXT: retq
-entry:
- %t= load i16, ptr %a
- %and = and i16 %t, %b
- store i16 %and, ptr %a
- ret void
-}
-
-define void @and32mr_legacy(ptr %a, i32 noundef %b) {
-; CHECK-LABEL: and32mr_legacy:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl %esi, (%rdi)
-; CHECK-NEXT: retq
-entry:
- %t= load i32, ptr %a
- %and = and i32 %t, %b
- store i32 %and, ptr %a
- ret void
-}
-
-define void @and64mr_legacy(ptr %a, i64 noundef %b) {
-; CHECK-LABEL: and64mr_legacy:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andq %rsi, (%rdi)
-; CHECK-NEXT: retq
-entry:
- %t= load i64, ptr %a
- %and = and i64 %t, %b
- store i64 %and, ptr %a
- ret void
-}
-
-define void @and8mi_legacy(ptr %a) {
-; CHECK-LABEL: and8mi_legacy:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andb $123, (%rdi)
-; CHECK-NEXT: retq
-entry:
- %t= load i8, ptr %a
- %and = and i8 %t, 123
- store i8 %and, ptr %a
- ret void
-}
-
-define void @and16mi_legacy(ptr %a) {
-; CHECK-LABEL: and16mi_legacy:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andw $1234, (%rdi) # imm = 0x4D2
-; CHECK-NEXT: retq
-entry:
- %t= load i16, ptr %a
- %and = and i16 %t, 1234
- store i16 %and, ptr %a
- ret void
-}
-
-define void @and32mi_legacy(ptr %a) {
-; CHECK-LABEL: and32mi_legacy:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $123456, (%rdi) # imm = 0x1E240
-; CHECK-NEXT: retq
-entry:
- %t= load i32, ptr %a
- %and = and i32 %t, 123456
- store i32 %and, ptr %a
- ret void
-}
-
-define void @and64mi_legacy(ptr %a) {
-; CHECK-LABEL: and64mi_legacy:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andq $123456, (%rdi) # imm = 0x1E240
-; CHECK-NEXT: retq
-entry:
- %t= load i64, ptr %a
- %and = and i64 %t, 123456
- store i64 %and, ptr %a
- ret void
-}
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