[llvm] cd1d344 - [RISCV] Don't check haveNoCommonBitsSet in RISCVGatherScatterLowering

[Luke Lau via llvm-commits]

Author: Luke Lau
Date: 2024-01-15T14:09:52+07:00
New Revision: cd1d3445d8a53ef4d667908f0539eda37345defa

URL: https://github.com/llvm/llvm-project/commit/cd1d3445d8a53ef4d667908f0539eda37345defa
DIFF: https://github.com/llvm/llvm-project/commit/cd1d3445d8a53ef4d667908f0539eda37345defa.diff

LOG: [RISCV] Don't check haveNoCommonBitsSet in RISCVGatherScatterLowering

If an or instruction has no common bits set in its operands, InstCombine will
set the disjoint flag. This means we shouldn't need to compute it ourselves
anymore in RISCVGatherScatterLowering, and can just rely on said flag being
set.
Originally split out from #77800

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
index cd438e153068e5..1dcb83a6078ed7 100644
--- a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
@@ -250,8 +250,7 @@ bool RISCVGatherScatterLowering::matchStridedRecurrence(Value *Index, Loop *L,
     return false;
   case Instruction::Or:
     // We need to be able to treat Or as Add.
-    if (!haveNoCommonBitsSet(BO->getOperand(0), BO->getOperand(1), *DL) &&
-        !cast<PossiblyDisjointInst>(BO)->isDisjoint())
+    if (!cast<PossiblyDisjointInst>(BO)->isDisjoint())
       return false;
     break;
   case Instruction::Add: