[llvm] [RISCV] Add scheduler model for sifive-p450. (PR #77989)

[Wang Pengcheng via llvm-commits]

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@@ -36,6 +36,7 @@ include "GISel/RISCVRegisterBanks.td"
 
 include "RISCVSchedRocket.td"
 include "RISCVSchedSiFive7.td"
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wangpc-pp wrote:

One question I should have asked before (not for this patch): Can we separate SiFive7 model into two files or two models (scalar scheduling and RVV scheduling)? I know the microarchitecture of X280 inherits from SiFive7, but there are some different designs I see from current scheduling model, which makes X280 and SiFive7 independent enough.

Maybe we can make scalar parts a multiclass and reuse it in X280 scheduling model.
cc @michaelmaitland 

https://github.com/llvm/llvm-project/pull/77989