[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension. (PR #76785)

via llvm-commits llvm-commits at lists.llvm.org
Sun Jan 14 06:37:31 PST 2024


https://github.com/sun-jacobi edited https://github.com/llvm/llvm-project/pull/76785


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