[llvm] [X86][CodeGen] Support lowering for NDD ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT/INC/DEC/IMUL (PR #77564)

Shengchen Kan via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 10 20:15:24 PST 2024

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https://github.com/KanRobert closed https://github.com/llvm/llvm-project/pull/77564

Previous message: [llvm] [X86][CodeGen] Support lowering for NDD ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT/INC/DEC/IMUL (PR #77564)
Next message: [llvm] [AArch64] MI Scheduler: create more LDP/STP pairs (PR #77565)
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