[llvm] [AArch64] MI Scheduler: create more LDP/STP pairs (PR #77565)

[Florian Hahn via llvm-commits]

fhahn wrote:

> We can't combine the the load in line [5] into the load on [1]: regisister q1 is
> used in between.

Just because the register is used in between doesn't necessarily prevent AArch64LoadStoreOptimizer.cpp from combining loads/stores I think, it supports renaming registers in some cases when a different register can be picked.

https://github.com/llvm/llvm-project/pull/77565