[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

[Nemanja Ivanovic via llvm-commits]

================
@@ -179,6 +180,11 @@ Assembly Support
 Supported
   Fully supported by the compiler.  This includes everything in Assembly Support, along with - if relevant - C language intrinsics for the instructions and pattern matching by the compiler to recognize idiomatic patterns which can be lowered to the associated instructions.
 
+.. _riscv-rve-note:
+
+``E``
+  Support of RV32E/RV64E and ilp32e/lp64e ABIs are experimental. To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass variadic arguments and set stack alignment to 4-bytes for types with length of 2*XLEN.
----------------
nemanjai wrote:

Use of `and` in the second sentence is ambiguous. Given statements A and B:
A: we use aligned registers to pass variadic arguments
B: we set the stack alignment to 4 bytes for types with length 2*XLEN
- we don't (A and B) == we don't A nor B
- we don't A and we do B
I think it would be clearer as:
```
To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass
variadic arguments. Furthermore, we set the stack alignment to 4 bytes for types with length of 2*XLEN.
```

https://github.com/llvm/llvm-project/pull/76777