[llvm] [IR] Add intrinsics to represent complex multiply and divide operations (PR #68742)

[Simon Pilgrim via llvm-commits]

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@@ -770,6 +770,7 @@ def assertsext : SDNode<"ISD::AssertSext", SDT_assert>;
 def assertzext : SDNode<"ISD::AssertZext", SDT_assert>;
 def assertalign : SDNode<"ISD::AssertAlign", SDT_assert>;
 
+def COMPLEX_FMUL : SDNode<"ISD::COMPLEX_FMUL", SDTFPBinOp, [SDNPCommutative]>;
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RKSimon wrote:

(style) lowercase for tablegen operator - `complex_fmul`

https://github.com/llvm/llvm-project/pull/68742