[llvm] [CodeGen][MachinePipeliner] Limit register pressure when scheduling (PR #74807)

[Ryotaro KASUGA via llvm-commits]

kasuga-fj wrote:

Thank you for your review!

> So is the issue caused by some loops failing to match MachinePipeliner's expectations and then being skipped by it?

Yes. However, we are working on resolving this issue and have recently been able to increase the number of programs to which MachinePipeliner can be applied. We've not yet confirmed the details of the results, but we may be able to present improvements in other benchmarks in the near future.

Once we have the results, I will ask someone familiar with this part to review the patch.

https://github.com/llvm/llvm-project/pull/74807