[llvm] [JITLink][AArch32] Add TableGen Backend for Instr Encodings (PR #76996)

[Stefan Gränitz via llvm-commits]

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@@ -212,19 +272,18 @@ template <> struct FixupInfo<Arm_Call> : public FixupInfoArmBranch {
   static constexpr uint32_t BitBlx = 0x10000000;
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weliveindetail wrote:

Looks like we could infer this as:
```
BitBLX = InstrTable[BLXi] & ~InstrTable[BL] == 0xfa000000 & 0x14000000 == 0x10000000
```

Opcode and OpcodeMask don't match exactly what we have. They seem to include the condition mask and H bit. Is there a way to get this info from TableGen? And if so, can we integrate it without adding another `InstrInfo` entry for each line in the generated `.inc`?

Otherwise, we will have to do some adjustments in the implementation. In general, I'd be happy to follow whatever TableGen can give us.

https://github.com/llvm/llvm-project/pull/76996