[llvm] [RISCV] Emit <ISA> together with mapping symbols for functions (PR #77292)
Andreu Carminati via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 8 04:18:22 PST 2024
https://github.com/andcarminati updated https://github.com/llvm/llvm-project/pull/77292
>From 131f3a8d6da82116b460680adfb439602d109b96 Mon Sep 17 00:00:00 2001
From: Andreu Carminati <andreu.carminati at hightec-rt.com>
Date: Wed, 3 Jan 2024 17:43:29 +0100
Subject: [PATCH 1/2] [RISCV] Emit <ISA> together with mapping symbols for
functions
Emit in case of divergence against the base ISA. This will help
disassembling when we have functions with additional features.
---
.../RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 24 +++++++-
.../RISCV/MCTargetDesc/RISCVELFStreamer.h | 10 +++-
.../RISCV/MCTargetDesc/RISCVTargetStreamer.h | 1 +
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 2 +-
.../RISCV/emit-features-mapping-symbols.ll | 57 +++++++++++++++++++
5 files changed, 88 insertions(+), 6 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/emit-features-mapping-symbols.ll
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index 9db5148208b3ec..f01a97a04131bf 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -137,14 +137,30 @@ void RISCVELFStreamer::emitDataMappingSymbol() {
LastEMS = EMS_Data;
}
-void RISCVELFStreamer::emitInstructionsMappingSymbol() {
+void RISCVELFStreamer::emitInstructionsMappingSymbol(
+ const MCSubtargetInfo &STI) {
if (LastEMS == EMS_Instructions)
return;
- emitMappingSymbol("$x");
+
+ std::string ISA = "";
+ // Compare the base MCSubtargetInfo with current MCSubtargetInfo,
+ // and emit ISA when they are different.
+ if (Subtarget->getFeatureBits() != STI.getFeatureBits()) {
+ auto ParseResult = RISCVFeatures::parseFeatureBits(
+ STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());
+ if (!ParseResult) {
+ report_fatal_error(ParseResult.takeError());
+ }
+ auto &ISAInfo = *ParseResult;
+ ISA = ISAInfo->toString();
+ }
+
+ emitMappingSymbol("$x" + ISA);
LastEMS = EMS_Instructions;
}
void RISCVELFStreamer::emitMappingSymbol(StringRef Name) {
+
auto *Symbol = cast<MCSymbolELF>(getContext().getOrCreateSymbol(
Name + "." + Twine(MappingSymbolCounter++)));
emitLabel(Symbol);
@@ -165,7 +181,7 @@ void RISCVELFStreamer::changeSection(MCSection *Section,
void RISCVELFStreamer::emitInstruction(const MCInst &Inst,
const MCSubtargetInfo &STI) {
- emitInstructionsMappingSymbol();
+ emitInstructionsMappingSymbol(STI);
MCELFStreamer::emitInstruction(Inst, STI);
}
@@ -186,6 +202,8 @@ void RISCVELFStreamer::emitValueImpl(const MCExpr *Value, unsigned Size,
MCELFStreamer::emitValueImpl(Value, Size, Loc);
}
+void RISCVELFStreamer::startFunction() { LastEMS = EMS_None; }
+
namespace llvm {
MCELFStreamer *createRISCVELFStreamer(MCContext &C,
std::unique_ptr<MCAsmBackend> MAB,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index a6f54bf67b5d2b..e178b4a855aede 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -11,13 +11,14 @@
#include "RISCVTargetStreamer.h"
#include "llvm/MC/MCELFStreamer.h"
+#include "llvm/MC/MCContext.h"
using namespace llvm;
class RISCVELFStreamer : public MCELFStreamer {
void reset() override;
void emitDataMappingSymbol();
- void emitInstructionsMappingSymbol();
+ void emitInstructionsMappingSymbol(const MCSubtargetInfo &STI);
void emitMappingSymbol(StringRef Name);
enum ElfMappingSymbol { EMS_None, EMS_Instructions, EMS_Data };
@@ -25,18 +26,22 @@ class RISCVELFStreamer : public MCELFStreamer {
int64_t MappingSymbolCounter = 0;
DenseMap<const MCSection *, ElfMappingSymbol> LastMappingSymbols;
ElfMappingSymbol LastEMS = EMS_None;
+ const MCSubtargetInfo *Subtarget;
public:
RISCVELFStreamer(MCContext &C, std::unique_ptr<MCAsmBackend> MAB,
std::unique_ptr<MCObjectWriter> MOW,
std::unique_ptr<MCCodeEmitter> MCE)
- : MCELFStreamer(C, std::move(MAB), std::move(MOW), std::move(MCE)) {}
+ : MCELFStreamer(C, std::move(MAB), std::move(MOW), std::move(MCE)),
+ Subtarget(C.getSubtargetInfo()) {}
void changeSection(MCSection *Section, const MCExpr *Subsection) override;
void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
void emitBytes(StringRef Data) override;
void emitFill(const MCExpr &NumBytes, uint64_t FillValue, SMLoc Loc) override;
void emitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) override;
+
+ void startFunction();
};
namespace llvm {
@@ -71,6 +76,7 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
void finish() override;
+ void startFunction() override {getStreamer().startFunction();}
};
MCELFStreamer *createRISCVELFStreamer(MCContext &C,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index 070e72fb157ae9..c21ada33cea39c 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -58,6 +58,7 @@ class RISCVTargetStreamer : public MCTargetStreamer {
void emitTargetAttributes(const MCSubtargetInfo &STI, bool EmitStackAlign);
void setTargetABI(RISCVABI::ABI ABI);
RISCVABI::ABI getTargetABI() const { return TargetABI; }
+ virtual void startFunction() {return;}
};
// This part is for ascii assembly output
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 0fd514fa87cd2f..5e78edd0ec3c56 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -369,7 +369,7 @@ bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
bool EmittedOptionArch = emitDirectiveOptionArch();
-
+ RTS.startFunction();
SetupMachineFunction(MF);
emitFunctionBody();
diff --git a/llvm/test/CodeGen/RISCV/emit-features-mapping-symbols.ll b/llvm/test/CodeGen/RISCV/emit-features-mapping-symbols.ll
new file mode 100644
index 00000000000000..f70f3c25afd01f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/emit-features-mapping-symbols.ll
@@ -0,0 +1,57 @@
+; RUN: llc -filetype=obj -mtriple=riscv32 < %s -o %t
+; RUN: llvm-readelf -s %t | FileCheck %s --check-prefixes=SEC
+
+; SEC: [[#%x,]]: [[#%x,]] 0 NOTYPE LOCAL DEFAULT 2 $xrv32i2p1_f2p2_d2p2_c2p0_zicsr2p0.0
+; SEC: [[#%x,]]: [[#%x,]] 0 NOTYPE LOCAL DEFAULT 2 $xrv32i2p1_f2p2_d2p2_zicsr2p0.1
+; SEC: [[#%x,]]: [[#%x,]] 0 NOTYPE LOCAL DEFAULT 2 $xrv32i2p1_a2p1_f2p2_d2p2_c2p0_zicsr2p0.2
+; SEC: [[#%x,]]: [[#%x,]] 0 NOTYPE LOCAL DEFAULT 2 $xrv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0.3
+; SEC: [[#%x,]]: [[#%x,]] 0 NOTYPE LOCAL DEFAULT 2 $xrv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0.4
+; SEC: [[#%x,]]: [[#%x,]] 0 NOTYPE LOCAL DEFAULT 2 $x.5
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
+target triple = "riscv32-unknown-unknown"
+
+; Function Attrs: nounwind
+define dso_local void @testAttr0() #0 {
+entry:
+ ret void
+}
+
+; Function Attrs: nounwind
+define dso_local void @testAttr1() #1 {
+entry:
+ ret void
+}
+
+; Function Attrs: nounwind
+define dso_local void @testAttr2() #2 {
+entry:
+ ret void
+}
+
+; Function Attrs: nounwind
+define dso_local void @testAttr3() #3 {
+entry:
+ ret void
+}
+
+; Function Attrs: nounwind
+define dso_local void @testAttr4() #4 {
+entry:
+ ret void
+}
+
+; Function Attrs: nounwind
+define dso_local void @testAttrDefault() {
+entry:
+ ret void
+}
+
+attributes #0 = { nounwind "target-cpu"="generic-rv32" "target-features"="+32bit,+c,+d" }
+attributes #1 = { nounwind "target-cpu"="generic-rv32" "target-features"="+32bit,+d" }
+attributes #2 = { nounwind "target-cpu"="generic-rv32" "target-features"="+32bit,+a,+c,+d" }
+attributes #3 = { nounwind "target-cpu"="generic-rv32" "target-features"="+32bit,+a,+c,+d,+f,+m,+zicsr" }
+attributes #4 = { nounwind "target-cpu"="generic-rv32" "target-features"="+32bit,+a,+c,+d,+f,+m,+v" }
+
+
+
>From 69a62246fb5f3499145ada605295141b687e2b0c Mon Sep 17 00:00:00 2001
From: Andreu Carminati <andreu.carminati at hightec-rt.com>
Date: Mon, 8 Jan 2024 11:45:41 +0100
Subject: [PATCH 2/2] Format code
---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h | 4 ++--
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index e178b4a855aede..a39282a427df61 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -10,8 +10,8 @@
#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVELFSTREAMER_H
#include "RISCVTargetStreamer.h"
-#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCELFStreamer.h"
using namespace llvm;
@@ -76,7 +76,7 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
void finish() override;
- void startFunction() override {getStreamer().startFunction();}
+ void startFunction() override { getStreamer().startFunction(); }
};
MCELFStreamer *createRISCVELFStreamer(MCContext &C,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index c21ada33cea39c..68a33a8613723a 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -58,7 +58,7 @@ class RISCVTargetStreamer : public MCTargetStreamer {
void emitTargetAttributes(const MCSubtargetInfo &STI, bool EmitStackAlign);
void setTargetABI(RISCVABI::ABI ABI);
RISCVABI::ABI getTargetABI() const { return TargetABI; }
- virtual void startFunction() {return;}
+ virtual void startFunction() { return; }
};
// This part is for ascii assembly output
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