[llvm] [X86][MC] Support encoding/decoding for APX variant MUL/IMUL/DIV/IDIV instructions (PR #76919)

[Phoebe Wang via llvm-commits]

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@@ -8,8 +8,40 @@
 
 def TruePredicate : Predicate<"true">;
 
+// Intel x86 instructions have three separate encoding spaces: legacy, VEX, and
+// EVEX. Not all X86 instructions are extended for EGPR. The following is an
+// overview of which instructions are extended and how we implement them.
+//
+// * Legacy space
+//   All instructions in legacy maps 0 and 1 that have explicit GPR or memory
+//   operands can use the REX2 prefix to access the EGPR, except XSAVE*/XRSTOR.
+//
+// * EVEX space
+//   All instructions in the EVEX space can access the EGPR in their
+//   register/memory operands.
+//
+// For the above intructions, the only difference in encoding is reflected in
+// the REX2/EVEX prefix when EGPR is used, i.e. the opcode and opcode name are
+// unchanged. We don’t add new entries in TD, and instead we extend GPR with
+// R16-R31 and make them allocatable only when the feature EGPR is available.
+//
+// Besides, some instructions in legacy space with map 2/3 and VEX space are
+// promoted into EVEX space. Encoding space changes and opcode, opcode map may
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phoebewang wrote:

Encoding space changes after the promotion, opcode and opcode map may change too sometimes.

https://github.com/llvm/llvm-project/pull/76919