[llvm] [CodeGen][MachinePipeliner] Limit register pressure when scheduling (PR #74807)

[Ryotaro Kasuga via llvm-commits]

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@@ -2044,6 +2457,16 @@ bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) {
     // If a schedule is found, check if it is a valid schedule too.
     if (scheduleFound)
       scheduleFound = Schedule.isValidSchedule(this);
+
+    // If a schedule found and the option is enabled, check if the schedule
+    // might generate additional register spill/fill
+    if (scheduleFound && LimitRegPressure) {
+      std::vector<MachineInstr *> OrderedInsts;
+      DenseMap<MachineInstr *, unsigned> Stages;
+      computeScheduledInsts(this, Schedule, OrderedInsts, Stages);
+      scheduleFound = !HRPDetector->detect(OrderedInsts, Stages,
+                                           Schedule.getMaxStageCount());
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kasuga-fj wrote:

It seems better. Thanks.

https://github.com/llvm/llvm-project/pull/74807