[llvm] [RISCV][llvm-mca] Use correct LMUL and SEW for strided loads and stores (PR #76869)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,427 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e8, mf4, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e8, mf2, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e8, m1, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e8, m2, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+
+vsetvli zero, zero, e8, m4, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+
+vsetvli zero, zero, e8, m8, tu, mu
+vlse8.v  v1, (a1), a2
+
+vsetvli zero, zero, e16, mf8, tu, mu
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topperc wrote:

The most concise version is probably this table https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc#type-system

The derivation is from this text in the V spec

> Implementations must support fractional LMUL settings for LMUL ≥ SEWLMUL1MIN/SEWLMUL1MAX, where SEWLMUL1MIN is the narrowest supported SEW value at LMUL=1 and SEWLMUL1MAX is the widest supported SEW value at LMUL=1. An attempt to set an unsupported SEW and LMUL con guration sets the vill bit in vtype.

>For a given supported fractional LMUL setting, implementations must support SEW settings between SEWLMUL1MIN and LMUL * SEWLMUL1MAX, inclusive.

https://github.com/llvm/llvm-project/pull/76869