[llvm] [LLVM][AArch64][tblgen]: Match clamp pattern (PR #75529)

[Paul Walker via llvm-commits]

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@@ -316,6 +316,32 @@ def AArch64ssra : PatFrags<(ops node:$op1, node:$op2, node:$op3),
                            [(int_aarch64_sve_ssra node:$op1, node:$op2, node:$op3),
                             (add node:$op1, (AArch64asr_p (SVEAnyPredicate), node:$op2, (SVEShiftSplatImmR (i32 node:$op3))))]>;
 
+// Replace pattern min(max(v1,v2),v3) by clamp
+def AArch64sclamp : PatFrags<(ops node:$Zd, node:$Zn, node:$Zm),
+                              [(int_aarch64_sve_sclamp node:$Zd, node:$Zn, node:$Zm),
+                              (AArch64smin_p (SVEAllActive),
+                                  (AArch64smax_p (SVEAllActive), node:$Zd, node:$Zn),
+                                  node:$Zm)
+                               ]>;
+def AArch64uclamp : PatFrags<(ops node:$Zd, node:$Zn, node:$Zm),
+                              [(int_aarch64_sve_uclamp node:$Zd, node:$Zn, node:$Zm),
+                               (AArch64umin_p (SVEAllActive),
+                                  (AArch64umax_p (SVEAllActive), node:$Zd, node:$Zn),
+                                  node:$Zm)
+                              ]>;
+def AArch64fclamp : PatFrags<(ops node:$Zd, node:$Zn, node:$Zm),
+                              [(int_aarch64_sve_fclamp node:$Zd, node:$Zn, node:$Zm),
+                              (AArch64fminnm_p (SVEAllActive),
+                                  (AArch64fmaxnm_p (SVEAllActive), node:$Zd, node:$Zn),
+                               node:$Zm)
+                               ]>;
+def AArch64bfclamp : PatFrags<(ops node:$Zd, node:$Zn, node:$Zm),
+                              [(int_aarch64_sve_fclamp node:$Zd, node:$Zn, node:$Zm),
+                              (int_aarch64_sve_fminnm (nxv8i1 (SVEAllActive)),
+                                  (nxv8bf16 (int_aarch64_sve_fmaxnm (nxv8i1 (SVEAllActive)), node:$Zd, node:$Zn)),
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paulwalker-arm wrote:

Whilst not wrong these should be `int_aarch64_sve_fminnm_u` and `int_aarch64_sve_fmaxnm_u` because at the IR level we have inst combines (see `AArch64TTIImpl::instCombineIntrinsic`) that canonicalise most intrinsics that take an all active predicate to their `_u` form to reduce duplication. And thus for the real world use cases these bfloat patterns will not fire.

https://github.com/llvm/llvm-project/pull/75529