[llvm] 9d45579 - [InstCombine] Don't treat undef as poison in demanded element simplification
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 19 03:26:56 PST 2023
Author: Nikita Popov
Date: 2023-12-19T12:26:48+01:00
New Revision: 9d4557920f1008b64300928c4696bf22e923f71f
URL: https://github.com/llvm/llvm-project/commit/9d4557920f1008b64300928c4696bf22e923f71f
DIFF: https://github.com/llvm/llvm-project/commit/9d4557920f1008b64300928c4696bf22e923f71f.diff
LOG: [InstCombine] Don't treat undef as poison in demanded element simplification
We can only set PoisonElts if the element is poison, not if it is
undef.
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
llvm/test/Transforms/InstCombine/X86/clmulqdq.ll
llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
llvm/test/Transforms/InstCombine/X86/x86-avx512.ll
llvm/test/Transforms/InstCombine/X86/x86-pshufb.ll
llvm/test/Transforms/InstCombine/broadcast.ll
llvm/test/Transforms/InstCombine/extractelement.ll
llvm/test/Transforms/InstCombine/inselt-binop.ll
llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
llvm/test/Transforms/InstCombine/pr38984.ll
llvm/test/Transforms/InstCombine/shuffle_select.ll
llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
llvm/test/Transforms/InstCombine/sub-of-negatible.ll
llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
llvm/test/Transforms/InstCombine/vec_gep_scalar_arg.ll
llvm/test/Transforms/InstCombine/vec_shuffle.ll
llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
llvm/test/Transforms/InstCombine/vector-casts.ll
llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
llvm/test/Transforms/SLPVectorizer/X86/hadd.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 5dcd7598c2a50b..48b97ca4696680 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -1345,15 +1345,15 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
APInt EltMask(APInt::getAllOnes(VWidth));
assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!");
- if (DemandedElts.isZero()) { // If nothing is demanded, provide poison.
+ if (match(V, m_Poison())) {
+ // If the entire vector is poison, just return this info.
PoisonElts = EltMask;
- return !isa<PoisonValue>(V) ? PoisonValue::get(V->getType()) : nullptr;
+ return nullptr;
}
- if (match(V, m_Undef())) {
- // If the entire vector is undef or poison, just return this info.
+ if (DemandedElts.isZero()) { // If nothing is demanded, provide poison.
PoisonElts = EltMask;
- return nullptr;
+ return PoisonValue::get(V->getType());
}
PoisonElts = 0;
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
index 53300e0c9771a9..b2fd8e453aaf6a 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
@@ -4872,7 +4872,7 @@ define amdgpu_ps float @extract_elt0_dmask_0111_image_sample_1d_v4f32_f32(float
define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
; CHECK-LABEL: @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32(
; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float [[S:%.*]], <8 x i32> [[SAMPLER:%.*]], <4 x i32> [[RSRC:%.*]], i1 false, i32 0, i32 0)
-; CHECK-NEXT: [[SHUF:%.*]] = insertelement <2 x float> poison, float [[DATA]], i64 0
+; CHECK-NEXT: [[SHUF:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[DATA]], i64 0
; CHECK-NEXT: ret <2 x float> [[SHUF]]
;
%data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
@@ -4913,7 +4913,7 @@ define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0101_image_sample_1d_v4f32
define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32(
; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float [[S:%.*]], <8 x i32> [[SAMPLER:%.*]], <4 x i32> [[RSRC:%.*]], i1 false, i32 0, i32 0)
-; CHECK-NEXT: [[SHUF:%.*]] = insertelement <3 x float> poison, float [[DATA]], i64 0
+; CHECK-NEXT: [[SHUF:%.*]] = insertelement <3 x float> <float poison, float undef, float undef>, float [[DATA]], i64 0
; CHECK-NEXT: ret <3 x float> [[SHUF]]
;
%data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
index ce809a5676b82f..1bb53bc483f0a6 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
@@ -4871,7 +4871,7 @@ define amdgpu_ps float @extract_elt0_dmask_0111_image_sample_1d_v4f32_f32(float
define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
; CHECK-LABEL: @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32(
; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float [[S:%.*]], <8 x i32> [[SAMPLER:%.*]], <4 x i32> [[RSRC:%.*]], i1 false, i32 0, i32 0)
-; CHECK-NEXT: [[SHUF:%.*]] = insertelement <2 x float> poison, float [[DATA]], i64 0
+; CHECK-NEXT: [[SHUF:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[DATA]], i64 0
; CHECK-NEXT: ret <2 x float> [[SHUF]]
;
%data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
@@ -4912,7 +4912,7 @@ define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0101_image_sample_1d_v4f32
define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32(
; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float [[S:%.*]], <8 x i32> [[SAMPLER:%.*]], <4 x i32> [[RSRC:%.*]], i1 false, i32 0, i32 0)
-; CHECK-NEXT: [[SHUF:%.*]] = insertelement <3 x float> poison, float [[DATA]], i64 0
+; CHECK-NEXT: [[SHUF:%.*]] = insertelement <3 x float> <float poison, float undef, float undef>, float [[DATA]], i64 0
; CHECK-NEXT: ret <3 x float> [[SHUF]]
;
%data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
diff --git a/llvm/test/Transforms/InstCombine/X86/clmulqdq.ll b/llvm/test/Transforms/InstCombine/X86/clmulqdq.ll
index 763b79c9e58151..00affe13f484fb 100644
--- a/llvm/test/Transforms/InstCombine/X86/clmulqdq.ll
+++ b/llvm/test/Transforms/InstCombine/X86/clmulqdq.ll
@@ -51,7 +51,8 @@ define <2 x i64> @test_demanded_elts_pclmulqdq_17(<2 x i64> %a0, <2 x i64> %a1)
define <2 x i64> @test_demanded_elts_pclmulqdq_undef_0() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_0(
-; CHECK-NEXT: ret <2 x i64> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 poison>, <2 x i64> <i64 undef, i64 poison>, i8 0)
+; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 1>, <2 x i64> <i64 undef, i64 1>, i8 0)
ret <2 x i64> %1
@@ -59,7 +60,8 @@ define <2 x i64> @test_demanded_elts_pclmulqdq_undef_0() {
define <2 x i64> @test_demanded_elts_pclmulqdq_undef_1() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_1(
-; CHECK-NEXT: ret <2 x i64> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 poison, i64 undef>, <2 x i64> <i64 undef, i64 poison>, i8 1)
+; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 1, i64 undef>, <2 x i64> <i64 undef, i64 1>, i8 1)
ret <2 x i64> %1
@@ -67,7 +69,8 @@ define <2 x i64> @test_demanded_elts_pclmulqdq_undef_1() {
define <2 x i64> @test_demanded_elts_pclmulqdq_undef_16() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_16(
-; CHECK-NEXT: ret <2 x i64> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 poison>, <2 x i64> <i64 poison, i64 undef>, i8 16)
+; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 1>, <2 x i64> <i64 1, i64 undef>, i8 16)
ret <2 x i64> %1
@@ -75,12 +78,45 @@ define <2 x i64> @test_demanded_elts_pclmulqdq_undef_16() {
define <2 x i64> @test_demanded_elts_pclmulqdq_undef_17() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_17(
-; CHECK-NEXT: ret <2 x i64> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 poison, i64 undef>, <2 x i64> <i64 poison, i64 undef>, i8 17)
+; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 1, i64 undef>, <2 x i64> <i64 1, i64 undef>, i8 17)
ret <2 x i64> %1
}
+define <2 x i64> @test_demanded_elts_pclmulqdq_poison_0() {
+; CHECK-LABEL: @test_demanded_elts_pclmulqdq_poison_0(
+; CHECK-NEXT: ret <2 x i64> zeroinitializer
+;
+ %1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 poison, i64 1>, <2 x i64> <i64 poison, i64 1>, i8 0)
+ ret <2 x i64> %1
+}
+
+define <2 x i64> @test_demanded_elts_pclmulqdq_poison_1() {
+; CHECK-LABEL: @test_demanded_elts_pclmulqdq_poison_1(
+; CHECK-NEXT: ret <2 x i64> zeroinitializer
+;
+ %1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 1, i64 poison>, <2 x i64> <i64 poison, i64 1>, i8 1)
+ ret <2 x i64> %1
+}
+
+define <2 x i64> @test_demanded_elts_pclmulqdq_poison_16() {
+; CHECK-LABEL: @test_demanded_elts_pclmulqdq_poison_16(
+; CHECK-NEXT: ret <2 x i64> zeroinitializer
+;
+ %1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 poison, i64 1>, <2 x i64> <i64 1, i64 poison>, i8 16)
+ ret <2 x i64> %1
+}
+
+define <2 x i64> @test_demanded_elts_pclmulqdq_poison_17() {
+; CHECK-LABEL: @test_demanded_elts_pclmulqdq_poison_17(
+; CHECK-NEXT: ret <2 x i64> zeroinitializer
+;
+ %1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 1, i64 poison>, <2 x i64> <i64 1, i64 poison>, i8 17)
+ ret <2 x i64> %1
+}
+
define <4 x i64> @test_demanded_elts_pclmulqdq_256_0(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_0(
; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> [[A0:%.*]], <4 x i64> [[A1:%.*]], i8 0)
@@ -135,7 +171,8 @@ define <4 x i64> @test_demanded_elts_pclmulqdq_256_17(<4 x i64> %a0, <4 x i64> %
define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_0() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_0(
-; CHECK-NEXT: ret <4 x i64> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 poison, i64 undef, i64 poison>, <4 x i64> <i64 undef, i64 poison, i64 undef, i64 poison>, i8 0)
+; CHECK-NEXT: ret <4 x i64> [[TMP1]]
;
%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, <4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, i8 0)
ret <4 x i64> %1
@@ -143,7 +180,8 @@ define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_0() {
define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_1() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_1(
-; CHECK-NEXT: ret <4 x i64> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 poison, i64 undef, i64 poison, i64 undef>, <4 x i64> <i64 undef, i64 poison, i64 undef, i64 poison>, i8 1)
+; CHECK-NEXT: ret <4 x i64> [[TMP1]]
;
%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, <4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, i8 1)
ret <4 x i64> %1
@@ -151,7 +189,8 @@ define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_1() {
define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_16() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_16(
-; CHECK-NEXT: ret <4 x i64> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 poison, i64 undef, i64 poison>, <4 x i64> <i64 poison, i64 undef, i64 poison, i64 undef>, i8 16)
+; CHECK-NEXT: ret <4 x i64> [[TMP1]]
;
%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, <4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, i8 16)
ret <4 x i64> %1
@@ -159,12 +198,45 @@ define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_16() {
define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_17() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_17(
-; CHECK-NEXT: ret <4 x i64> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 poison, i64 undef, i64 poison, i64 undef>, <4 x i64> <i64 poison, i64 undef, i64 poison, i64 undef>, i8 17)
+; CHECK-NEXT: ret <4 x i64> [[TMP1]]
;
%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, <4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, i8 17)
ret <4 x i64> %1
}
+define <4 x i64> @test_demanded_elts_pclmulqdq_256_poison_0() {
+; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_poison_0(
+; CHECK-NEXT: ret <4 x i64> zeroinitializer
+;
+ %1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 poison, i64 1, i64 poison, i64 1>, <4 x i64> <i64 poison, i64 1, i64 poison, i64 1>, i8 0)
+ ret <4 x i64> %1
+}
+
+define <4 x i64> @test_demanded_elts_pclmulqdq_256_poison_1() {
+; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_poison_1(
+; CHECK-NEXT: ret <4 x i64> zeroinitializer
+;
+ %1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 1, i64 poison, i64 1, i64 poison>, <4 x i64> <i64 poison, i64 1, i64 poison, i64 1>, i8 1)
+ ret <4 x i64> %1
+}
+
+define <4 x i64> @test_demanded_elts_pclmulqdq_256_poison_16() {
+; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_poison_16(
+; CHECK-NEXT: ret <4 x i64> zeroinitializer
+;
+ %1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 poison, i64 1, i64 poison, i64 1>, <4 x i64> <i64 1, i64 poison, i64 1, i64 poison>, i8 16)
+ ret <4 x i64> %1
+}
+
+define <4 x i64> @test_demanded_elts_pclmulqdq_256_poison_17() {
+; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_poison_17(
+; CHECK-NEXT: ret <4 x i64> zeroinitializer
+;
+ %1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 1, i64 poison, i64 1, i64 poison>, <4 x i64> <i64 1, i64 poison, i64 1, i64 poison>, i8 17)
+ ret <4 x i64> %1
+}
+
define <8 x i64> @test_demanded_elts_pclmulqdq_512_0(<8 x i64> %a0, <8 x i64> %a1) {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_0(
; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> [[A0:%.*]], <8 x i64> [[A1:%.*]], i8 0)
@@ -235,7 +307,8 @@ define <8 x i64> @test_demanded_elts_pclmulqdq_512_17(<8 x i64> %a0, <8 x i64> %
define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_0() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_0(
-; CHECK-NEXT: ret <8 x i64> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison>, <8 x i64> <i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison>, i8 0)
+; CHECK-NEXT: ret <8 x i64> [[TMP1]]
;
%1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, <8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, i8 0)
ret <8 x i64> %1
@@ -243,7 +316,8 @@ define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_0() {
define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_1() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_1(
-; CHECK-NEXT: ret <8 x i64> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef>, <8 x i64> <i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison>, i8 1)
+; CHECK-NEXT: ret <8 x i64> [[TMP1]]
;
%1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, <8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, i8 1)
ret <8 x i64> %1
@@ -251,7 +325,8 @@ define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_1() {
define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_16() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_16(
-; CHECK-NEXT: ret <8 x i64> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison>, <8 x i64> <i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef>, i8 16)
+; CHECK-NEXT: ret <8 x i64> [[TMP1]]
;
%1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, <8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, i8 16)
ret <8 x i64> %1
@@ -259,8 +334,41 @@ define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_16() {
define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_17() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_17(
-; CHECK-NEXT: ret <8 x i64> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef>, <8 x i64> <i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef>, i8 17)
+; CHECK-NEXT: ret <8 x i64> [[TMP1]]
;
%1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, <8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, i8 17)
ret <8 x i64> %1
}
+
+define <8 x i64> @test_demanded_elts_pclmulqdq_512_poison_0() {
+; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_poison_0(
+; CHECK-NEXT: ret <8 x i64> zeroinitializer
+;
+ %1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1>, <8 x i64> <i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1>, i8 0)
+ ret <8 x i64> %1
+}
+
+define <8 x i64> @test_demanded_elts_pclmulqdq_512_poison_1() {
+; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_poison_1(
+; CHECK-NEXT: ret <8 x i64> zeroinitializer
+;
+ %1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison>, <8 x i64> <i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1>, i8 1)
+ ret <8 x i64> %1
+}
+
+define <8 x i64> @test_demanded_elts_pclmulqdq_512_poison_16() {
+; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_poison_16(
+; CHECK-NEXT: ret <8 x i64> zeroinitializer
+;
+ %1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1>, <8 x i64> <i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison>, i8 16)
+ ret <8 x i64> %1
+}
+
+define <8 x i64> @test_demanded_elts_pclmulqdq_512_poison_17() {
+; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_poison_17(
+; CHECK-NEXT: ret <8 x i64> zeroinitializer
+;
+ %1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison>, <8 x i64> <i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison>, i8 17)
+ ret <8 x i64> %1
+}
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll b/llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
index b27c94667d56da..9b990480709c97 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
@@ -23,7 +23,7 @@ define <4 x float> @test_add_ss(<4 x float> %a, <4 x float> %b) {
define <4 x float> @test_add_ss_round(<4 x float> %a, <4 x float> %b) {
;
; CHECK-LABEL: @test_add_ss_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -103,7 +103,7 @@ define <2 x double> @test_add_sd(<2 x double> %a, <2 x double> %b) {
define <2 x double> @test_add_sd_round(<2 x double> %a, <2 x double> %b) {
;
; CHECK-LABEL: @test_add_sd_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -175,7 +175,7 @@ define <4 x float> @test_sub_ss(<4 x float> %a, <4 x float> %b) {
define <4 x float> @test_sub_ss_round(<4 x float> %a, <4 x float> %b) {
;
; CHECK-LABEL: @test_sub_ss_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -255,7 +255,7 @@ define <2 x double> @test_sub_sd(<2 x double> %a, <2 x double> %b) {
define <2 x double> @test_sub_sd_round(<2 x double> %a, <2 x double> %b) {
;
; CHECK-LABEL: @test_sub_sd_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -327,7 +327,7 @@ define <4 x float> @test_mul_ss(<4 x float> %a, <4 x float> %b) {
define <4 x float> @test_mul_ss_round(<4 x float> %a, <4 x float> %b) {
;
; CHECK-LABEL: @test_mul_ss_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -407,7 +407,7 @@ define <2 x double> @test_mul_sd(<2 x double> %a, <2 x double> %b) {
define <2 x double> @test_mul_sd_round(<2 x double> %a, <2 x double> %b) {
;
; CHECK-LABEL: @test_mul_sd_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -479,7 +479,7 @@ define <4 x float> @test_div_ss(<4 x float> %a, <4 x float> %b) {
define <4 x float> @test_div_ss_round(<4 x float> %a, <4 x float> %b) {
;
; CHECK-LABEL: @test_div_ss_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -559,7 +559,7 @@ define <2 x double> @test_div_sd(<2 x double> %a, <2 x double> %b) {
define <2 x double> @test_div_sd_round(<2 x double> %a, <2 x double> %b) {
;
; CHECK-LABEL: @test_div_sd_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -615,7 +615,7 @@ declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>,
define <4 x float> @test_max_ss(<4 x float> %a, <4 x float> %b) {
;
; CHECK-LABEL: @test_max_ss(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 4)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -661,7 +661,7 @@ declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x doubl
define <2 x double> @test_max_sd(<2 x double> %a, <2 x double> %b) {
;
; CHECK-LABEL: @test_max_sd(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 4)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -699,7 +699,7 @@ declare <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float>, <4 x float>,
define <4 x float> @test_min_ss(<4 x float> %a, <4 x float> %b) {
;
; CHECK-LABEL: @test_min_ss(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 4)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -745,7 +745,7 @@ declare <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double>, <2 x doubl
define <2 x double> @test_min_sd(<2 x double> %a, <2 x double> %b) {
;
; CHECK-LABEL: @test_min_sd(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 4)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-avx512.ll b/llvm/test/Transforms/InstCombine/X86/x86-avx512.ll
index ea806a89679c57..c10c922f664324 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-avx512.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-avx512.ll
@@ -23,7 +23,7 @@ define <4 x float> @test_add_ss(<4 x float> %a, <4 x float> %b) {
define <4 x float> @test_add_ss_round(<4 x float> %a, <4 x float> %b) {
;
; CHECK-LABEL: @test_add_ss_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -103,7 +103,7 @@ define <2 x double> @test_add_sd(<2 x double> %a, <2 x double> %b) {
define <2 x double> @test_add_sd_round(<2 x double> %a, <2 x double> %b) {
;
; CHECK-LABEL: @test_add_sd_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -175,7 +175,7 @@ define <4 x float> @test_sub_ss(<4 x float> %a, <4 x float> %b) {
define <4 x float> @test_sub_ss_round(<4 x float> %a, <4 x float> %b) {
;
; CHECK-LABEL: @test_sub_ss_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -255,7 +255,7 @@ define <2 x double> @test_sub_sd(<2 x double> %a, <2 x double> %b) {
define <2 x double> @test_sub_sd_round(<2 x double> %a, <2 x double> %b) {
;
; CHECK-LABEL: @test_sub_sd_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -327,7 +327,7 @@ define <4 x float> @test_mul_ss(<4 x float> %a, <4 x float> %b) {
define <4 x float> @test_mul_ss_round(<4 x float> %a, <4 x float> %b) {
;
; CHECK-LABEL: @test_mul_ss_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -407,7 +407,7 @@ define <2 x double> @test_mul_sd(<2 x double> %a, <2 x double> %b) {
define <2 x double> @test_mul_sd_round(<2 x double> %a, <2 x double> %b) {
;
; CHECK-LABEL: @test_mul_sd_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -479,7 +479,7 @@ define <4 x float> @test_div_ss(<4 x float> %a, <4 x float> %b) {
define <4 x float> @test_div_ss_round(<4 x float> %a, <4 x float> %b) {
;
; CHECK-LABEL: @test_div_ss_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -559,7 +559,7 @@ define <2 x double> @test_div_sd(<2 x double> %a, <2 x double> %b) {
define <2 x double> @test_div_sd_round(<2 x double> %a, <2 x double> %b) {
;
; CHECK-LABEL: @test_div_sd_round(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -615,7 +615,7 @@ declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>,
define <4 x float> @test_max_ss(<4 x float> %a, <4 x float> %b) {
;
; CHECK-LABEL: @test_max_ss(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 4)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -661,7 +661,7 @@ declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x doubl
define <2 x double> @test_max_sd(<2 x double> %a, <2 x double> %b) {
;
; CHECK-LABEL: @test_max_sd(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 4)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -699,7 +699,7 @@ declare <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float>, <4 x float>,
define <4 x float> @test_min_ss(<4 x float> %a, <4 x float> %b) {
;
; CHECK-LABEL: @test_min_ss(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 4)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -745,7 +745,7 @@ declare <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double>, <2 x doubl
define <2 x double> @test_min_sd(<2 x double> %a, <2 x double> %b) {
;
; CHECK-LABEL: @test_min_sd(
-; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 4)
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-pshufb.ll b/llvm/test/Transforms/InstCombine/X86/x86-pshufb.ll
index 9fde3237737ecc..cd90696eafac6f 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-pshufb.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-pshufb.ll
@@ -446,7 +446,7 @@ define <64 x i8> @fold_with_undef_elts_avx512(<64 x i8> %InVec) {
define <16 x i8> @fold_with_allundef_elts(<16 x i8> %InVec) {
; CHECK-LABEL: @fold_with_allundef_elts(
-; CHECK-NEXT: ret <16 x i8> undef
+; CHECK-NEXT: ret <16 x i8> poison
;
%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> undef)
ret <16 x i8> %1
@@ -454,7 +454,7 @@ define <16 x i8> @fold_with_allundef_elts(<16 x i8> %InVec) {
define <32 x i8> @fold_with_allundef_elts_avx2(<32 x i8> %InVec) {
; CHECK-LABEL: @fold_with_allundef_elts_avx2(
-; CHECK-NEXT: ret <32 x i8> undef
+; CHECK-NEXT: ret <32 x i8> poison
;
%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> undef)
ret <32 x i8> %1
@@ -462,7 +462,7 @@ define <32 x i8> @fold_with_allundef_elts_avx2(<32 x i8> %InVec) {
define <64 x i8> @fold_with_allundef_elts_avx512(<64 x i8> %InVec) {
; CHECK-LABEL: @fold_with_allundef_elts_avx512(
-; CHECK-NEXT: ret <64 x i8> undef
+; CHECK-NEXT: ret <64 x i8> poison
;
%1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> undef)
ret <64 x i8> %1
diff --git a/llvm/test/Transforms/InstCombine/broadcast.ll b/llvm/test/Transforms/InstCombine/broadcast.ll
index c70b975a312ad5..ffc5508092b4c8 100644
--- a/llvm/test/Transforms/InstCombine/broadcast.ll
+++ b/llvm/test/Transforms/InstCombine/broadcast.ll
@@ -57,7 +57,7 @@ define <4 x float> @good4(float %arg) {
define <4 x float> @good5(float %v) {
; CHECK-LABEL: @good5(
-; CHECK-NEXT: [[INS1:%.*]] = insertelement <4 x float> undef, float [[V:%.*]], i64 0
+; CHECK-NEXT: [[INS1:%.*]] = insertelement <4 x float> <float poison, float undef, float undef, float undef>, float [[V:%.*]], i64 0
; CHECK-NEXT: [[A1:%.*]] = fadd <4 x float> [[INS1]], [[INS1]]
; CHECK-NEXT: [[INS4:%.*]] = shufflevector <4 x float> [[INS1]], <4 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[RES:%.*]] = fadd <4 x float> [[A1]], [[INS4]]
@@ -76,7 +76,7 @@ define <4 x float> @good5(float %v) {
define <4 x float> @splat_undef1(float %arg) {
; CHECK-LABEL: @splat_undef1(
-; CHECK-NEXT: [[T4:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i64 1
+; CHECK-NEXT: [[T4:%.*]] = insertelement <4 x float> <float undef, float poison, float poison, float poison>, float [[ARG:%.*]], i64 1
; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T4]], float [[ARG]], i64 2
; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i64 3
; CHECK-NEXT: ret <4 x float> [[T6]]
@@ -92,7 +92,7 @@ define <4 x float> @splat_undef1(float %arg) {
define <4 x float> @splat_undef2(float %arg) {
; CHECK-LABEL: @splat_undef2(
-; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i64 0
+; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> <float poison, float undef, float poison, float poison>, float [[ARG:%.*]], i64 0
; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T]], float [[ARG]], i64 2
; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i64 3
; CHECK-NEXT: ret <4 x float> [[T6]]
@@ -132,7 +132,7 @@ define <1 x float> @bad4(float %arg) {
define <4 x float> @splat_undef3(float %arg) {
; CHECK-LABEL: @splat_undef3(
-; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i64 0
+; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> <float poison, float poison, float undef, float undef>, float [[ARG:%.*]], i64 0
; CHECK-NEXT: [[T4:%.*]] = insertelement <4 x float> [[T]], float [[ARG]], i64 1
; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T4]], float [[ARG]], i64 2
; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i64 3
@@ -149,7 +149,7 @@ define <4 x float> @splat_undef3(float %arg) {
define <4 x float> @bad6(float %arg, i32 %k) {
; CHECK-LABEL: @bad6(
-; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i64 0
+; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> <float poison, float poison, float undef, float poison>, float [[ARG:%.*]], i64 0
; CHECK-NEXT: [[T4:%.*]] = insertelement <4 x float> [[T]], float [[ARG]], i64 1
; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T4]], float [[ARG]], i32 [[K:%.*]]
; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i64 3
@@ -164,7 +164,7 @@ define <4 x float> @bad6(float %arg, i32 %k) {
define <4 x float> @bad7(float %v) {
; CHECK-LABEL: @bad7(
-; CHECK-NEXT: [[INS1:%.*]] = insertelement <4 x float> undef, float [[V:%.*]], i64 1
+; CHECK-NEXT: [[INS1:%.*]] = insertelement <4 x float> <float undef, float poison, float undef, float undef>, float [[V:%.*]], i64 1
; CHECK-NEXT: [[A1:%.*]] = fadd <4 x float> [[INS1]], [[INS1]]
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[INS1]], float [[V]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[V]], i64 2
diff --git a/llvm/test/Transforms/InstCombine/extractelement.ll b/llvm/test/Transforms/InstCombine/extractelement.ll
index 3d94106d7f8885..bc5dd060a540ae 100644
--- a/llvm/test/Transforms/InstCombine/extractelement.ll
+++ b/llvm/test/Transforms/InstCombine/extractelement.ll
@@ -145,14 +145,14 @@ declare void @use(<8 x i8>)
define i8 @bitcasted_inselt_wide_source_uses(i32 %x) {
; ANYLE-LABEL: @bitcasted_inselt_wide_source_uses(
-; ANYLE-NEXT: [[I:%.*]] = insertelement <2 x i32> undef, i32 [[X:%.*]], i64 0
+; ANYLE-NEXT: [[I:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[X:%.*]], i64 0
; ANYLE-NEXT: [[B:%.*]] = bitcast <2 x i32> [[I]] to <8 x i8>
; ANYLE-NEXT: call void @use(<8 x i8> [[B]])
; ANYLE-NEXT: [[R:%.*]] = extractelement <8 x i8> [[B]], i64 3
; ANYLE-NEXT: ret i8 [[R]]
;
; ANYBE-LABEL: @bitcasted_inselt_wide_source_uses(
-; ANYBE-NEXT: [[I:%.*]] = insertelement <2 x i32> undef, i32 [[X:%.*]], i64 0
+; ANYBE-NEXT: [[I:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[X:%.*]], i64 0
; ANYBE-NEXT: [[B:%.*]] = bitcast <2 x i32> [[I]] to <8 x i8>
; ANYBE-NEXT: call void @use(<8 x i8> [[B]])
; ANYBE-NEXT: [[R:%.*]] = trunc i32 [[X]] to i8
@@ -188,7 +188,7 @@ declare void @use_v8f32(<8 x float>)
define float @bitcasted_inselt_to_FP_uses(i128 %x) {
; ANY-LABEL: @bitcasted_inselt_to_FP_uses(
-; ANY-NEXT: [[I:%.*]] = insertelement <2 x i128> undef, i128 [[X:%.*]], i64 0
+; ANY-NEXT: [[I:%.*]] = insertelement <2 x i128> <i128 poison, i128 undef>, i128 [[X:%.*]], i64 0
; ANY-NEXT: call void @use_v2i128(<2 x i128> [[I]])
; ANY-NEXT: [[B:%.*]] = bitcast <2 x i128> [[I]] to <8 x float>
; ANY-NEXT: [[R:%.*]] = extractelement <8 x float> [[B]], i64 1
@@ -203,7 +203,7 @@ define float @bitcasted_inselt_to_FP_uses(i128 %x) {
define float @bitcasted_inselt_to_FP_uses2(i128 %x) {
; ANY-LABEL: @bitcasted_inselt_to_FP_uses2(
-; ANY-NEXT: [[I:%.*]] = insertelement <2 x i128> undef, i128 [[X:%.*]], i64 0
+; ANY-NEXT: [[I:%.*]] = insertelement <2 x i128> <i128 poison, i128 undef>, i128 [[X:%.*]], i64 0
; ANY-NEXT: [[B:%.*]] = bitcast <2 x i128> [[I]] to <8 x float>
; ANY-NEXT: call void @use_v8f32(<8 x float> [[B]])
; ANY-NEXT: [[R:%.*]] = extractelement <8 x float> [[B]], i64 1
@@ -239,7 +239,7 @@ declare void @use_v8i16(<8 x i16>)
define i16 @bitcasted_inselt_from_FP_uses(double %x) {
; ANY-LABEL: @bitcasted_inselt_from_FP_uses(
-; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> undef, double [[X:%.*]], i64 0
+; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[X:%.*]], i64 0
; ANY-NEXT: call void @use_v2f64(<2 x double> [[I]])
; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <8 x i16>
; ANY-NEXT: [[R:%.*]] = extractelement <8 x i16> [[B]], i64 1
@@ -254,7 +254,7 @@ define i16 @bitcasted_inselt_from_FP_uses(double %x) {
define i16 @bitcasted_inselt_from_FP_uses2(double %x) {
; ANY-LABEL: @bitcasted_inselt_from_FP_uses2(
-; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> undef, double [[X:%.*]], i64 0
+; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[X:%.*]], i64 0
; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <8 x i16>
; ANY-NEXT: call void @use_v8i16(<8 x i16> [[B]])
; ANY-NEXT: [[R:%.*]] = extractelement <8 x i16> [[B]], i64 1
@@ -282,7 +282,7 @@ define float @bitcasted_inselt_to_and_from_FP(double %x) {
define float @bitcasted_inselt_to_and_from_FP_uses(double %x) {
; ANY-LABEL: @bitcasted_inselt_to_and_from_FP_uses(
-; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> undef, double [[X:%.*]], i64 0
+; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[X:%.*]], i64 0
; ANY-NEXT: call void @use_v2f64(<2 x double> [[I]])
; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <4 x float>
; ANY-NEXT: [[R:%.*]] = extractelement <4 x float> [[B]], i64 1
@@ -299,7 +299,7 @@ declare void @use_v4f32(<4 x float>)
define float @bitcasted_inselt_to_and_from_FP_uses2(double %x) {
; ANY-LABEL: @bitcasted_inselt_to_and_from_FP_uses2(
-; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> undef, double [[X:%.*]], i64 0
+; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[X:%.*]], i64 0
; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <4 x float>
; ANY-NEXT: call void @use_v4f32(<4 x float> [[B]])
; ANY-NEXT: [[R:%.*]] = extractelement <4 x float> [[B]], i64 1
diff --git a/llvm/test/Transforms/InstCombine/inselt-binop.ll b/llvm/test/Transforms/InstCombine/inselt-binop.ll
index 6592a59acb9060..dc362a0207b378 100644
--- a/llvm/test/Transforms/InstCombine/inselt-binop.ll
+++ b/llvm/test/Transforms/InstCombine/inselt-binop.ll
@@ -3,7 +3,7 @@
define <2 x i8> @add_constant(i8 %x) {
; CHECK-LABEL: @add_constant(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 undef>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -14,7 +14,7 @@ define <2 x i8> @add_constant(i8 %x) {
define <2 x i8> @add_constant_not_undef_lane(i8 %x) {
; CHECK-LABEL: @add_constant_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 -42>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -27,7 +27,7 @@ define <2 x i8> @add_constant_not_undef_lane(i8 %x) {
define <2 x i8> @sub_constant_op0(i8 %x) {
; CHECK-LABEL: @sub_constant_op0(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = sub nuw nsw <2 x i8> <i8 undef, i8 -42>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -38,7 +38,7 @@ define <2 x i8> @sub_constant_op0(i8 %x) {
define <2 x i8> @sub_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @sub_constant_op0_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = sub nuw <2 x i8> <i8 42, i8 -42>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -49,7 +49,7 @@ define <2 x i8> @sub_constant_op0_not_undef_lane(i8 %x) {
define <2 x i8> @sub_constant_op1(i8 %x) {
; CHECK-LABEL: @sub_constant_op1(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 -42, i8 undef>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -60,7 +60,7 @@ define <2 x i8> @sub_constant_op1(i8 %x) {
define <2 x i8> @sub_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @sub_constant_op1_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 -42, i8 42>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -71,7 +71,7 @@ define <2 x i8> @sub_constant_op1_not_undef_lane(i8 %x) {
define <3 x i8> @mul_constant(i8 %x) {
; CHECK-LABEL: @mul_constant(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <3 x i8> undef, i8 [[X:%.*]], i64 2
+; CHECK-NEXT: [[INS:%.*]] = insertelement <3 x i8> <i8 undef, i8 undef, i8 poison>, i8 [[X:%.*]], i64 2
; CHECK-NEXT: [[BO:%.*]] = mul <3 x i8> [[INS]], <i8 undef, i8 undef, i8 -42>
; CHECK-NEXT: ret <3 x i8> [[BO]]
;
@@ -82,7 +82,7 @@ define <3 x i8> @mul_constant(i8 %x) {
define <3 x i8> @mul_constant_not_undef_lane(i8 %x) {
; CHECK-LABEL: @mul_constant_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <3 x i8> undef, i8 [[X:%.*]], i64 2
+; CHECK-NEXT: [[INS:%.*]] = insertelement <3 x i8> <i8 undef, i8 undef, i8 poison>, i8 [[X:%.*]], i64 2
; CHECK-NEXT: [[BO:%.*]] = mul <3 x i8> [[INS]], <i8 42, i8 undef, i8 -42>
; CHECK-NEXT: ret <3 x i8> [[BO]]
;
@@ -93,7 +93,7 @@ define <3 x i8> @mul_constant_not_undef_lane(i8 %x) {
define <2 x i8> @shl_constant_op0(i8 %x) {
; CHECK-LABEL: @shl_constant_op0(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = shl <2 x i8> <i8 undef, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -104,7 +104,7 @@ define <2 x i8> @shl_constant_op0(i8 %x) {
define <2 x i8> @shl_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @shl_constant_op0_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = shl <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -115,7 +115,7 @@ define <2 x i8> @shl_constant_op0_not_undef_lane(i8 %x) {
define <2 x i8> @shl_constant_op1(i8 %x) {
; CHECK-LABEL: @shl_constant_op1(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = shl nuw <2 x i8> [[INS]], <i8 5, i8 undef>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -126,7 +126,7 @@ define <2 x i8> @shl_constant_op1(i8 %x) {
define <2 x i8> @shl_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @shl_constant_op1_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = shl nuw <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -137,7 +137,7 @@ define <2 x i8> @shl_constant_op1_not_undef_lane(i8 %x) {
define <2 x i8> @ashr_constant_op0(i8 %x) {
; CHECK-LABEL: @ashr_constant_op0(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = ashr exact <2 x i8> <i8 undef, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -148,7 +148,7 @@ define <2 x i8> @ashr_constant_op0(i8 %x) {
define <2 x i8> @ashr_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @ashr_constant_op0_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = lshr exact <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -159,7 +159,7 @@ define <2 x i8> @ashr_constant_op0_not_undef_lane(i8 %x) {
define <2 x i8> @ashr_constant_op1(i8 %x) {
; CHECK-LABEL: @ashr_constant_op1(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = ashr <2 x i8> [[INS]], <i8 5, i8 undef>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -170,7 +170,7 @@ define <2 x i8> @ashr_constant_op1(i8 %x) {
define <2 x i8> @ashr_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @ashr_constant_op1_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = ashr <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -181,7 +181,7 @@ define <2 x i8> @ashr_constant_op1_not_undef_lane(i8 %x) {
define <2 x i8> @lshr_constant_op0(i8 %x) {
; CHECK-LABEL: @lshr_constant_op0(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = lshr <2 x i8> <i8 5, i8 undef>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -192,7 +192,7 @@ define <2 x i8> @lshr_constant_op0(i8 %x) {
define <2 x i8> @lshr_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @lshr_constant_op0_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = lshr <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -203,7 +203,7 @@ define <2 x i8> @lshr_constant_op0_not_undef_lane(i8 %x) {
define <2 x i8> @lshr_constant_op1(i8 %x) {
; CHECK-LABEL: @lshr_constant_op1(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = lshr exact <2 x i8> [[INS]], <i8 undef, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -214,7 +214,7 @@ define <2 x i8> @lshr_constant_op1(i8 %x) {
define <2 x i8> @lshr_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @lshr_constant_op1_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = lshr exact <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -225,7 +225,7 @@ define <2 x i8> @lshr_constant_op1_not_undef_lane(i8 %x) {
define <2 x i8> @urem_constant_op0(i8 %x) {
; CHECK-LABEL: @urem_constant_op0(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = urem <2 x i8> <i8 5, i8 undef>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -236,7 +236,7 @@ define <2 x i8> @urem_constant_op0(i8 %x) {
define <2 x i8> @urem_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @urem_constant_op0_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = urem <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -256,7 +256,7 @@ define <2 x i8> @urem_constant_op1(i8 %x) {
define <2 x i8> @urem_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @urem_constant_op1_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = urem <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -267,7 +267,7 @@ define <2 x i8> @urem_constant_op1_not_undef_lane(i8 %x) {
define <2 x i8> @srem_constant_op0(i8 %x) {
; CHECK-LABEL: @srem_constant_op0(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = srem <2 x i8> <i8 5, i8 undef>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -278,7 +278,7 @@ define <2 x i8> @srem_constant_op0(i8 %x) {
define <2 x i8> @srem_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @srem_constant_op0_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = srem <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -298,7 +298,7 @@ define <2 x i8> @srem_constant_op1(i8 %x) {
define <2 x i8> @srem_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @srem_constant_op1_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = srem <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -309,7 +309,7 @@ define <2 x i8> @srem_constant_op1_not_undef_lane(i8 %x) {
define <2 x i8> @udiv_constant_op0(i8 %x) {
; CHECK-LABEL: @udiv_constant_op0(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = udiv exact <2 x i8> <i8 5, i8 undef>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -320,7 +320,7 @@ define <2 x i8> @udiv_constant_op0(i8 %x) {
define <2 x i8> @udiv_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @udiv_constant_op0_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = udiv exact <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -340,7 +340,7 @@ define <2 x i8> @udiv_constant_op1(i8 %x) {
define <2 x i8> @udiv_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @udiv_constant_op1_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = udiv <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -351,7 +351,7 @@ define <2 x i8> @udiv_constant_op1_not_undef_lane(i8 %x) {
define <2 x i8> @sdiv_constant_op0(i8 %x) {
; CHECK-LABEL: @sdiv_constant_op0(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = sdiv <2 x i8> <i8 5, i8 undef>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -362,7 +362,7 @@ define <2 x i8> @sdiv_constant_op0(i8 %x) {
define <2 x i8> @sdiv_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @sdiv_constant_op0_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = sdiv <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -382,7 +382,7 @@ define <2 x i8> @sdiv_constant_op1(i8 %x) {
define <2 x i8> @sdiv_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @sdiv_constant_op1_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = sdiv exact <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -393,7 +393,7 @@ define <2 x i8> @sdiv_constant_op1_not_undef_lane(i8 %x) {
define <2 x i8> @and_constant(i8 %x) {
; CHECK-LABEL: @and_constant(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = and <2 x i8> [[INS]], <i8 42, i8 undef>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -404,7 +404,7 @@ define <2 x i8> @and_constant(i8 %x) {
define <2 x i8> @and_constant_not_undef_lane(i8 %x) {
; CHECK-LABEL: @and_constant_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = and <2 x i8> [[INS]], <i8 42, i8 -42>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -415,7 +415,7 @@ define <2 x i8> @and_constant_not_undef_lane(i8 %x) {
define <2 x i8> @or_constant(i8 %x) {
; CHECK-LABEL: @or_constant(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = or <2 x i8> [[INS]], <i8 undef, i8 -42>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -426,7 +426,7 @@ define <2 x i8> @or_constant(i8 %x) {
define <2 x i8> @or_constant_not_undef_lane(i8 %x) {
; CHECK-LABEL: @or_constant_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = or <2 x i8> [[INS]], <i8 42, i8 -42>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -437,7 +437,7 @@ define <2 x i8> @or_constant_not_undef_lane(i8 %x) {
define <2 x i8> @xor_constant(i8 %x) {
; CHECK-LABEL: @xor_constant(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = xor <2 x i8> [[INS]], <i8 42, i8 undef>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -448,7 +448,7 @@ define <2 x i8> @xor_constant(i8 %x) {
define <2 x i8> @xor_constant_not_undef_lane(i8 %x) {
; CHECK-LABEL: @xor_constant_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = xor <2 x i8> [[INS]], <i8 42, i8 -42>
; CHECK-NEXT: ret <2 x i8> [[BO]]
;
@@ -459,7 +459,7 @@ define <2 x i8> @xor_constant_not_undef_lane(i8 %x) {
define <2 x float> @fadd_constant(float %x) {
; CHECK-LABEL: @fadd_constant(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fadd <2 x float> [[INS]], <float 4.200000e+01, float undef>
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -470,7 +470,7 @@ define <2 x float> @fadd_constant(float %x) {
define <2 x float> @fadd_constant_not_undef_lane(float %x) {
; CHECK-LABEL: @fadd_constant_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = fadd <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -481,7 +481,7 @@ define <2 x float> @fadd_constant_not_undef_lane(float %x) {
define <2 x float> @fsub_constant_op0(float %x) {
; CHECK-LABEL: @fsub_constant_op0(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fsub fast <2 x float> <float 4.200000e+01, float undef>, [[INS]]
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -492,7 +492,7 @@ define <2 x float> @fsub_constant_op0(float %x) {
define <2 x float> @fsub_constant_op0_not_undef_lane(float %x) {
; CHECK-LABEL: @fsub_constant_op0_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = fsub nsz <2 x float> <float 4.200000e+01, float -4.200000e+01>, [[INS]]
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -503,7 +503,7 @@ define <2 x float> @fsub_constant_op0_not_undef_lane(float %x) {
define <2 x float> @fsub_constant_op1(float %x) {
; CHECK-LABEL: @fsub_constant_op1(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = fadd <2 x float> [[INS]], <float undef, float -4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -514,7 +514,7 @@ define <2 x float> @fsub_constant_op1(float %x) {
define <2 x float> @fsub_constant_op1_not_undef_lane(float %x) {
; CHECK-LABEL: @fsub_constant_op1_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fadd <2 x float> [[INS]], <float -4.200000e+01, float 4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -525,7 +525,7 @@ define <2 x float> @fsub_constant_op1_not_undef_lane(float %x) {
define <2 x float> @fmul_constant(float %x) {
; CHECK-LABEL: @fmul_constant(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fmul reassoc <2 x float> [[INS]], <float 4.200000e+01, float undef>
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -536,7 +536,7 @@ define <2 x float> @fmul_constant(float %x) {
define <2 x float> @fmul_constant_not_undef_lane(float %x) {
; CHECK-LABEL: @fmul_constant_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = fmul <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -547,7 +547,7 @@ define <2 x float> @fmul_constant_not_undef_lane(float %x) {
define <2 x float> @fdiv_constant_op0(float %x) {
; CHECK-LABEL: @fdiv_constant_op0(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = fdiv nnan <2 x float> <float undef, float 4.200000e+01>, [[INS]]
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -558,7 +558,7 @@ define <2 x float> @fdiv_constant_op0(float %x) {
define <2 x float> @fdiv_constant_op0_not_undef_lane(float %x) {
; CHECK-LABEL: @fdiv_constant_op0_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fdiv ninf <2 x float> <float 4.200000e+01, float -4.200000e+01>, [[INS]]
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -569,7 +569,7 @@ define <2 x float> @fdiv_constant_op0_not_undef_lane(float %x) {
define <2 x float> @fdiv_constant_op1(float %x) {
; CHECK-LABEL: @fdiv_constant_op1(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fdiv <2 x float> [[INS]], <float 4.200000e+01, float undef>
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -580,7 +580,7 @@ define <2 x float> @fdiv_constant_op1(float %x) {
define <2 x float> @fdiv_constant_op1_not_undef_lane(float %x) {
; CHECK-LABEL: @fdiv_constant_op1_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fdiv <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -591,7 +591,7 @@ define <2 x float> @fdiv_constant_op1_not_undef_lane(float %x) {
define <2 x float> @frem_constant_op0(float %x) {
; CHECK-LABEL: @frem_constant_op0(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = frem fast <2 x float> <float 4.200000e+01, float undef>, [[INS]]
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -602,7 +602,7 @@ define <2 x float> @frem_constant_op0(float %x) {
define <2 x float> @frem_constant_op0_not_undef_lane(float %x) {
; CHECK-LABEL: @frem_constant_op0_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = frem <2 x float> <float 4.200000e+01, float -4.200000e+01>, [[INS]]
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -613,7 +613,7 @@ define <2 x float> @frem_constant_op0_not_undef_lane(float %x) {
define <2 x float> @frem_constant_op1(float %x) {
; CHECK-LABEL: @frem_constant_op1(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = frem ninf <2 x float> [[INS]], <float undef, float 4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]]
;
@@ -624,7 +624,7 @@ define <2 x float> @frem_constant_op1(float %x) {
define <2 x float> @frem_constant_op1_not_undef_lane(float %x) {
; CHECK-LABEL: @frem_constant_op1_not_undef_lane(
-; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0
+; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = frem nnan <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]]
;
diff --git a/llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll b/llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
index 5034f44b6a6f95..c87e2e8596c62d 100644
--- a/llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
+++ b/llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
@@ -290,7 +290,7 @@ define <4 x float> @collectShuffleElts(<2 x float> %x, float %y) {
; CHECK-LABEL: @collectShuffleElts(
; CHECK-NEXT: [[X0:%.*]] = extractelement <2 x float> [[X:%.*]], i64 0
; CHECK-NEXT: [[X1:%.*]] = extractelement <2 x float> [[X]], i64 1
-; CHECK-NEXT: [[V1:%.*]] = insertelement <4 x float> undef, float [[X0]], i64 1
+; CHECK-NEXT: [[V1:%.*]] = insertelement <4 x float> <float undef, float poison, float poison, float poison>, float [[X0]], i64 1
; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x float> [[V1]], float [[X1]], i64 2
; CHECK-NEXT: [[V3:%.*]] = insertelement <4 x float> [[V2]], float [[Y:%.*]], i64 3
; CHECK-NEXT: ret <4 x float> [[V3]]
@@ -462,7 +462,7 @@ define <5 x i7> @insert_nonzero_index_splat_widen(i7 %x) {
define <4 x float> @insert_nonzero_index_splat_extra_use(float %x) {
; CHECK-LABEL: @insert_nonzero_index_splat_extra_use(
-; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i64 2
+; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> <float undef, float undef, float poison, float undef>, float [[X:%.*]], i64 2
; CHECK-NEXT: call void @use(<4 x float> [[XV]])
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 poison, i32 2, i32 2, i32 poison>
; CHECK-NEXT: ret <4 x float> [[SPLAT]]
@@ -490,7 +490,7 @@ define <4 x float> @insert_nonzero_index_splat_wrong_base(float %x, <4 x float>
define <4 x float> @insert_nonzero_index_splat_wrong_index(float %x, i32 %index) {
; CHECK-LABEL: @insert_nonzero_index_splat_wrong_index(
-; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i32 [[INDEX:%.*]]
+; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> <float poison, float undef, float poison, float poison>, float [[X:%.*]], i32 [[INDEX:%.*]]
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 poison, i32 1, i32 1, i32 poison>
; CHECK-NEXT: ret <4 x float> [[SPLAT]]
;
@@ -513,7 +513,7 @@ define <4 x float> @insert_in_splat(float %x) {
define <4 x float> @insert_in_splat_extra_uses(float %x) {
; CHECK-LABEL: @insert_in_splat_extra_uses(
-; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i64 0
+; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> <float poison, float undef, float undef, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: call void @use(<4 x float> [[XV]])
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 poison>
; CHECK-NEXT: call void @use(<4 x float> [[SPLAT]])
diff --git a/llvm/test/Transforms/InstCombine/pr38984.ll b/llvm/test/Transforms/InstCombine/pr38984.ll
index af1d05a4654f78..c148765fce59f3 100644
--- a/llvm/test/Transforms/InstCombine/pr38984.ll
+++ b/llvm/test/Transforms/InstCombine/pr38984.ll
@@ -25,7 +25,7 @@ define <4 x i1> @PR38984_2() {
; CHECK-LABEL: @PR38984_2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @offsets, align 2
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> undef, i16 [[TMP0]], i64 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> <i16 undef, i16 undef, i16 undef, i16 poison>, i16 [[TMP0]], i64 3
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i16, ptr getelementptr inbounds ([21 x i16], ptr @a, i16 1, i16 0), <4 x i16> [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i16, ptr null, <4 x i16> [[TMP1]]
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <4 x ptr> [[TMP2]], [[TMP3]]
diff --git a/llvm/test/Transforms/InstCombine/shuffle_select.ll b/llvm/test/Transforms/InstCombine/shuffle_select.ll
index 12bf09f8aeb765..a1b0d782b554f9 100644
--- a/llvm/test/Transforms/InstCombine/shuffle_select.ll
+++ b/llvm/test/Transforms/InstCombine/shuffle_select.ll
@@ -1521,7 +1521,7 @@ define <4 x i8> @or_add_2_vars(<4 x i8> %v, <4 x i8> %v1) {
define <4 x i32> @PR41419(<4 x i32> %v) {
; CHECK-LABEL: @PR41419(
-; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[V:%.*]], <4 x i32> poison, <4 x i32> <i32 poison, i32 poison, i32 2, i32 poison>
+; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[V:%.*]], <4 x i32> <i32 undef, i32 undef, i32 poison, i32 undef>, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
; CHECK-NEXT: ret <4 x i32> [[S]]
;
%s = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
diff --git a/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll b/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
index 457300a25e769d..1699418dcc28b3 100644
--- a/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
+++ b/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
@@ -26,7 +26,7 @@ define i16 @test_srem_orig(i16 %a, i1 %cmp) {
; "evaluateInDifferentElementOrder".
define <2 x i16> @test_srem(i16 %a, i1 %cmp) {
; CHECK-LABEL: @test_srem(
-; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> undef, i16 [[A:%.*]], i64 0
+; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> <i16 poison, i16 undef>, i16 [[A:%.*]], i64 0
; CHECK-NEXT: [[T1:%.*]] = srem <2 x i16> [[SPLATINSERT]], <i16 2, i16 1>
; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> poison, <2 x i32> <i32 poison, i32 0>
; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]]
@@ -41,7 +41,7 @@ define <2 x i16> @test_srem(i16 %a, i1 %cmp) {
define <2 x i16> @test_urem(i16 %a, i1 %cmp) {
; CHECK-LABEL: @test_urem(
-; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> undef, i16 [[A:%.*]], i64 0
+; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> <i16 poison, i16 undef>, i16 [[A:%.*]], i64 0
; CHECK-NEXT: [[T1:%.*]] = urem <2 x i16> [[SPLATINSERT]], <i16 3, i16 1>
; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> poison, <2 x i32> <i32 poison, i32 0>
; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]]
@@ -56,7 +56,7 @@ define <2 x i16> @test_urem(i16 %a, i1 %cmp) {
define <2 x i16> @test_sdiv(i16 %a, i1 %cmp) {
; CHECK-LABEL: @test_sdiv(
-; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> undef, i16 [[A:%.*]], i64 0
+; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> <i16 poison, i16 undef>, i16 [[A:%.*]], i64 0
; CHECK-NEXT: [[T1:%.*]] = sdiv <2 x i16> [[SPLATINSERT]], <i16 2, i16 1>
; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> poison, <2 x i32> <i32 poison, i32 0>
; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]]
@@ -71,7 +71,7 @@ define <2 x i16> @test_sdiv(i16 %a, i1 %cmp) {
define <2 x i16> @test_udiv(i16 %a, i1 %cmp) {
; CHECK-LABEL: @test_udiv(
-; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> undef, i16 [[A:%.*]], i64 0
+; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> <i16 poison, i16 undef>, i16 [[A:%.*]], i64 0
; CHECK-NEXT: [[T1:%.*]] = udiv <2 x i16> [[SPLATINSERT]], <i16 3, i16 1>
; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> poison, <2 x i32> <i32 poison, i32 0>
; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]]
diff --git a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll
index 790d551e5b1de1..f2a28c0dd02b39 100644
--- a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll
+++ b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll
@@ -843,8 +843,8 @@ define <2 x i4> @negate_shufflevector_oneinput_reverse(<2 x i4> %x, <2 x i4> %y)
define <2 x i4> @negate_shufflevector_oneinput_second_lane_is_undef(<2 x i4> %x, <2 x i4> %y) {
; CHECK-LABEL: @negate_shufflevector_oneinput_second_lane_is_undef(
; CHECK-NEXT: [[T0_NEG:%.*]] = shl <2 x i4> <i4 6, i4 -5>, [[X:%.*]]
-; CHECK-NEXT: [[T1_NEG:%.*]] = shufflevector <2 x i4> [[T0_NEG]], <2 x i4> poison, <2 x i32> <i32 0, i32 poison>
-; CHECK-NEXT: [[T2:%.*]] = add <2 x i4> [[T1_NEG]], [[Y:%.*]]
+; CHECK-NEXT: [[T11_NEG:%.*]] = insertelement <2 x i4> [[T0_NEG]], i4 undef, i64 1
+; CHECK-NEXT: [[T2:%.*]] = add <2 x i4> [[T11_NEG]], [[Y:%.*]]
; CHECK-NEXT: ret <2 x i4> [[T2]]
;
%t0 = shl <2 x i4> <i4 -6, i4 5>, %x
diff --git a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
index 576af85b5ee275..c84d39c5aa9dd2 100644
--- a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
+++ b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
@@ -148,7 +148,7 @@ define <2 x i64> @PR24922(<2 x i64> %v) {
define <4 x float> @inselt_shuf_no_demand(float %a1, float %a2, float %a3) {
; CHECK-LABEL: @inselt_shuf_no_demand(
-; CHECK-NEXT: ret <4 x float> undef
+; CHECK-NEXT: ret <4 x float> <float undef, float poison, float poison, float poison>
;
%out1 = insertelement <4 x float> undef, float %a1, i32 1
%out12 = insertelement <4 x float> %out1, float %a2, i32 2
@@ -161,7 +161,7 @@ define <4 x float> @inselt_shuf_no_demand(float %a1, float %a2, float %a3) {
define <4 x float> @inselt_shuf_no_demand_commute(float %a1, float %a2, float %a3) {
; CHECK-LABEL: @inselt_shuf_no_demand_commute(
-; CHECK-NEXT: ret <4 x float> undef
+; CHECK-NEXT: ret <4 x float> <float undef, float poison, float poison, float poison>
;
%out1 = insertelement <4 x float> undef, float %a1, i32 1
%out12 = insertelement <4 x float> %out1, float %a2, i32 2
@@ -192,7 +192,7 @@ define <4 x i32> @inselt_shuf_no_demand_multiuse(i32 %a0, i32 %a1, <4 x i32> %b)
define <4 x float> @inselt_shuf_no_demand_bogus_insert_index_in_chain(float %a1, float %a2, float %a3, i32 %variable_index) {
; CHECK-LABEL: @inselt_shuf_no_demand_bogus_insert_index_in_chain(
-; CHECK-NEXT: [[OUT12:%.*]] = insertelement <4 x float> undef, float [[A2:%.*]], i32 [[VARIABLE_INDEX:%.*]]
+; CHECK-NEXT: [[OUT12:%.*]] = insertelement <4 x float> <float undef, float poison, float poison, float poison>, float [[A2:%.*]], i32 [[VARIABLE_INDEX:%.*]]
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x float> [[OUT12]], <4 x float> poison, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x float> [[SHUFFLE]]
;
@@ -617,8 +617,8 @@ define ptr @gep_splat_both(ptr %base, i64 %idx) {
define <2 x ptr> @gep_all_lanes_undef(ptr %base, i64 %idx) {;
; CHECK-LABEL: @gep_all_lanes_undef(
-; CHECK-NEXT: [[BASEVEC:%.*]] = insertelement <2 x ptr> undef, ptr [[BASE:%.*]], i64 0
-; CHECK-NEXT: [[IDXVEC:%.*]] = insertelement <2 x i64> undef, i64 [[IDX:%.*]], i64 1
+; CHECK-NEXT: [[BASEVEC:%.*]] = insertelement <2 x ptr> <ptr poison, ptr undef>, ptr [[BASE:%.*]], i64 0
+; CHECK-NEXT: [[IDXVEC:%.*]] = insertelement <2 x i64> <i64 undef, i64 poison>, i64 [[IDX:%.*]], i64 1
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, <2 x ptr> [[BASEVEC]], <2 x i64> [[IDXVEC]]
; CHECK-NEXT: ret <2 x ptr> [[GEP]]
;
@@ -780,7 +780,7 @@ define <4 x float> @ins_of_ext_twice(<4 x float> %x, float %y) {
define <4 x float> @ins_of_ext_wrong_demand(<4 x float> %x, float %y) {
; CHECK-LABEL: @ins_of_ext_wrong_demand(
; CHECK-NEXT: [[E0:%.*]] = extractelement <4 x float> [[X:%.*]], i64 0
-; CHECK-NEXT: [[I0:%.*]] = insertelement <4 x float> undef, float [[E0]], i64 0
+; CHECK-NEXT: [[I0:%.*]] = insertelement <4 x float> <float poison, float poison, float poison, float undef>, float [[E0]], i64 0
; CHECK-NEXT: [[I1:%.*]] = insertelement <4 x float> [[I0]], float [[Y:%.*]], i64 1
; CHECK-NEXT: [[I2:%.*]] = insertelement <4 x float> [[I1]], float [[Y]], i64 2
; CHECK-NEXT: ret <4 x float> [[I2]]
diff --git a/llvm/test/Transforms/InstCombine/vec_gep_scalar_arg.ll b/llvm/test/Transforms/InstCombine/vec_gep_scalar_arg.ll
index 69149720c93358..4e4fa7defa8cfc 100644
--- a/llvm/test/Transforms/InstCombine/vec_gep_scalar_arg.ll
+++ b/llvm/test/Transforms/InstCombine/vec_gep_scalar_arg.ll
@@ -4,7 +4,7 @@
define <4 x ptr> @PR41270(ptr %x) {
; CHECK-LABEL: @PR41270(
; CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds [4 x i16], ptr [[X:%.*]], i64 0, i64 3
-; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x ptr> undef, ptr [[T3]], i64 0
+; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x ptr> <ptr poison, ptr undef, ptr undef, ptr undef>, ptr [[T3]], i64 0
; CHECK-NEXT: ret <4 x ptr> [[INS2]]
;
%ins = insertelement <4 x ptr> undef, ptr %x, i32 0
diff --git a/llvm/test/Transforms/InstCombine/vec_shuffle.ll b/llvm/test/Transforms/InstCombine/vec_shuffle.ll
index 8eff837d6e1a3f..250a175ad0ebe3 100644
--- a/llvm/test/Transforms/InstCombine/vec_shuffle.ll
+++ b/llvm/test/Transforms/InstCombine/vec_shuffle.ll
@@ -81,7 +81,7 @@ define float @testvscale6(<vscale x 4 x float> %X) {
define <4 x float> @test7(<4 x float> %x) {
; CHECK-LABEL: @test7(
-; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float poison, float poison, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
; CHECK-NEXT: ret <4 x float> [[R]]
;
%r = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> < i32 0, i32 1, i32 6, i32 7 >
diff --git a/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
index 67ef3876375372..cf1b72fbcf3e1e 100644
--- a/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
@@ -294,7 +294,7 @@ define <8 x i32> @pr24458(<8 x float> %n) {
define <3 x i16> @trunc_inselt_undef(i32 %x) {
; CHECK-LABEL: @trunc_inselt_undef(
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i16
-; CHECK-NEXT: [[TRUNC:%.*]] = insertelement <3 x i16> undef, i16 [[TMP1]], i64 1
+; CHECK-NEXT: [[TRUNC:%.*]] = insertelement <3 x i16> <i16 undef, i16 poison, i16 undef>, i16 [[TMP1]], i64 1
; CHECK-NEXT: ret <3 x i16> [[TRUNC]]
;
%vec = insertelement <3 x i32> poison, i32 %x, i32 1
diff --git a/llvm/test/Transforms/InstCombine/vector-casts.ll b/llvm/test/Transforms/InstCombine/vector-casts.ll
index 21e0818fa001e6..281fc5f6011ea7 100644
--- a/llvm/test/Transforms/InstCombine/vector-casts.ll
+++ b/llvm/test/Transforms/InstCombine/vector-casts.ll
@@ -294,7 +294,7 @@ define <8 x i32> @pr24458(<8 x float> %n) {
define <3 x i16> @trunc_inselt_undef(i32 %x) {
; CHECK-LABEL: @trunc_inselt_undef(
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i16
-; CHECK-NEXT: [[TRUNC:%.*]] = insertelement <3 x i16> undef, i16 [[TMP1]], i64 1
+; CHECK-NEXT: [[TRUNC:%.*]] = insertelement <3 x i16> <i16 undef, i16 poison, i16 undef>, i16 [[TMP1]], i64 1
; CHECK-NEXT: ret <3 x i16> [[TRUNC]]
;
%vec = insertelement <3 x i32> undef, i32 %x, i32 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
index e690b041416b38..0b17e19e4fadd8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
@@ -389,7 +389,7 @@ define <8 x i32> @sdiv_v8i32_undefs(<8 x i32> %a) {
; SSE-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4
; SSE-NEXT: [[AB6:%.*]] = sdiv i32 [[A6]], 8
; SSE-NEXT: [[AB7:%.*]] = sdiv i32 [[A7]], 16
-; SSE-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, i32 [[AB1]], i64 1
+; SSE-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i64 1
; SSE-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i64 2
; SSE-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i64 3
; SSE-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB5]], i64 5
@@ -410,7 +410,7 @@ define <8 x i32> @sdiv_v8i32_undefs(<8 x i32> %a) {
; SLM-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4
; SLM-NEXT: [[AB6:%.*]] = sdiv i32 [[A6]], 8
; SLM-NEXT: [[AB7:%.*]] = sdiv i32 [[A7]], 16
-; SLM-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, i32 [[AB1]], i64 1
+; SLM-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i64 1
; SLM-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i64 2
; SLM-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i64 3
; SLM-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB5]], i64 5
@@ -431,7 +431,7 @@ define <8 x i32> @sdiv_v8i32_undefs(<8 x i32> %a) {
; AVX1-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4
; AVX1-NEXT: [[AB6:%.*]] = sdiv i32 [[A6]], 8
; AVX1-NEXT: [[AB7:%.*]] = sdiv i32 [[A7]], 16
-; AVX1-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, i32 [[AB1]], i64 1
+; AVX1-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i64 1
; AVX1-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i64 2
; AVX1-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i64 3
; AVX1-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB5]], i64 5
@@ -448,12 +448,12 @@ define <8 x i32> @sdiv_v8i32_undefs(<8 x i32> %a) {
; AVX2-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4
; AVX2-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <2 x i32> <i32 6, i32 7>
; AVX2-NEXT: [[TMP4:%.*]] = sdiv <2 x i32> [[TMP3]], <i32 8, i32 16>
-; AVX2-NEXT: [[R1:%.*]] = insertelement <8 x i32> poison, i32 [[AB1]], i64 1
+; AVX2-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i64 1
; AVX2-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX2-NEXT: [[R32:%.*]] = shufflevector <8 x i32> [[R1]], <8 x i32> [[TMP5]], <8 x i32> <i32 poison, i32 1, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison>
+; AVX2-NEXT: [[R32:%.*]] = shufflevector <8 x i32> [[R1]], <8 x i32> [[TMP5]], <8 x i32> <i32 poison, i32 1, i32 8, i32 9, i32 4, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R32]], i32 [[AB5]], i64 5
; AVX2-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX2-NEXT: [[R71:%.*]] = shufflevector <8 x i32> [[R5]], <8 x i32> [[TMP6]], <8 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 8, i32 9>
+; AVX2-NEXT: [[R71:%.*]] = shufflevector <8 x i32> [[R5]], <8 x i32> [[TMP6]], <8 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
; AVX2-NEXT: ret <8 x i32> [[R71]]
;
; AVX512-LABEL: @sdiv_v8i32_undefs(
@@ -465,12 +465,12 @@ define <8 x i32> @sdiv_v8i32_undefs(<8 x i32> %a) {
; AVX512-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4
; AVX512-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <2 x i32> <i32 6, i32 7>
; AVX512-NEXT: [[TMP4:%.*]] = sdiv <2 x i32> [[TMP3]], <i32 8, i32 16>
-; AVX512-NEXT: [[R1:%.*]] = insertelement <8 x i32> poison, i32 [[AB1]], i64 1
+; AVX512-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i64 1
; AVX512-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[R32:%.*]] = shufflevector <8 x i32> [[R1]], <8 x i32> [[TMP5]], <8 x i32> <i32 poison, i32 1, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison>
+; AVX512-NEXT: [[R32:%.*]] = shufflevector <8 x i32> [[R1]], <8 x i32> [[TMP5]], <8 x i32> <i32 poison, i32 1, i32 8, i32 9, i32 4, i32 poison, i32 poison, i32 poison>
; AVX512-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R32]], i32 [[AB5]], i64 5
; AVX512-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX512-NEXT: [[R71:%.*]] = shufflevector <8 x i32> [[R5]], <8 x i32> [[TMP6]], <8 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 8, i32 9>
+; AVX512-NEXT: [[R71:%.*]] = shufflevector <8 x i32> [[R5]], <8 x i32> [[TMP6]], <8 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
; AVX512-NEXT: ret <8 x i32> [[R71]]
;
%a0 = extractelement <8 x i32> %a, i32 0
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/hadd.ll b/llvm/test/Transforms/SLPVectorizer/X86/hadd.ll
index 1dcabb7aafc46b..31e3e6aa0a833d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/hadd.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/hadd.ll
@@ -220,7 +220,7 @@ define <4 x double> @test_v4f64_partial_swizzle(<4 x double> %a, <4 x double> %b
; SSE-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> <i32 1, i32 5>
; SSE-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]]
; SSE-NEXT: [[R3:%.*]] = fadd double [[B2]], [[B3]]
-; SSE-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 poison, i32 1, i32 poison>
+; SSE-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> <double undef, double poison>, <4 x i32> <i32 0, i32 2, i32 1, i32 poison>
; SSE-NEXT: [[R03:%.*]] = insertelement <4 x double> [[TMP4]], double [[R3]], i64 3
; SSE-NEXT: ret <4 x double> [[R03]]
;
@@ -231,7 +231,7 @@ define <4 x double> @test_v4f64_partial_swizzle(<4 x double> %a, <4 x double> %b
; SLM-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> <i32 1, i32 5>
; SLM-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]]
; SLM-NEXT: [[R3:%.*]] = fadd double [[B2]], [[B3]]
-; SLM-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 poison, i32 1, i32 poison>
+; SLM-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> <double undef, double poison>, <4 x i32> <i32 0, i32 2, i32 1, i32 poison>
; SLM-NEXT: [[R03:%.*]] = insertelement <4 x double> [[TMP4]], double [[R3]], i64 3
; SLM-NEXT: ret <4 x double> [[R03]]
;
@@ -242,9 +242,9 @@ define <4 x double> @test_v4f64_partial_swizzle(<4 x double> %a, <4 x double> %b
; AVX1-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[B:%.*]], <4 x double> poison, <2 x i32> <i32 1, i32 2>
; AVX1-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <2 x i32> <i32 0, i32 3>
; AVX1-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]]
-; AVX1-NEXT: [[R00:%.*]] = insertelement <4 x double> poison, double [[R0]], i64 0
+; AVX1-NEXT: [[R00:%.*]] = insertelement <4 x double> <double poison, double undef, double poison, double poison>, double [[R0]], i64 0
; AVX1-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
-; AVX1-NEXT: [[R031:%.*]] = shufflevector <4 x double> [[R00]], <4 x double> [[TMP4]], <4 x i32> <i32 0, i32 poison, i32 4, i32 5>
+; AVX1-NEXT: [[R031:%.*]] = shufflevector <4 x double> [[R00]], <4 x double> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; AVX1-NEXT: ret <4 x double> [[R031]]
;
; AVX2-LABEL: @test_v4f64_partial_swizzle(
@@ -254,9 +254,9 @@ define <4 x double> @test_v4f64_partial_swizzle(<4 x double> %a, <4 x double> %b
; AVX2-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[B:%.*]], <4 x double> poison, <2 x i32> <i32 1, i32 2>
; AVX2-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <2 x i32> <i32 0, i32 3>
; AVX2-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]]
-; AVX2-NEXT: [[R00:%.*]] = insertelement <4 x double> poison, double [[R0]], i64 0
+; AVX2-NEXT: [[R00:%.*]] = insertelement <4 x double> <double poison, double undef, double poison, double poison>, double [[R0]], i64 0
; AVX2-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
-; AVX2-NEXT: [[R031:%.*]] = shufflevector <4 x double> [[R00]], <4 x double> [[TMP4]], <4 x i32> <i32 0, i32 poison, i32 4, i32 5>
+; AVX2-NEXT: [[R031:%.*]] = shufflevector <4 x double> [[R00]], <4 x double> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; AVX2-NEXT: ret <4 x double> [[R031]]
;
; AVX512-LABEL: @test_v4f64_partial_swizzle(
@@ -266,7 +266,7 @@ define <4 x double> @test_v4f64_partial_swizzle(<4 x double> %a, <4 x double> %b
; AVX512-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> <i32 1, i32 5>
; AVX512-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]]
; AVX512-NEXT: [[R3:%.*]] = fadd double [[B2]], [[B3]]
-; AVX512-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 poison, i32 1, i32 poison>
+; AVX512-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> <double undef, double poison>, <4 x i32> <i32 0, i32 2, i32 1, i32 poison>
; AVX512-NEXT: [[R03:%.*]] = insertelement <4 x double> [[TMP4]], double [[R3]], i64 3
; AVX512-NEXT: ret <4 x double> [[R03]]
;
More information about the llvm-commits
mailing list