[llvm] [SelectionDAG] Add space-optimized forms of OPC_EmitRegister (PR #73291)

[Wang Pengcheng via llvm-commits]

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/73291

>From b3a726e3c024bb5c2a54eaf1d2363b4f7e1b55de Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Fri, 24 Nov 2023 15:06:04 +0800
Subject: [PATCH] [SelectionDAG] Add space-optimized forms of OPC_EmitRegister

The followed byte of `OPC_EmitRegister` is a MVT type, which is
usually i32 or i64.

We add `OPC_EmitRegisterI32` and `OPC_EmitRegisterI64` so that we
can reduce one byte.

Overall this reduces the llc binary size with all in-tree targets by
about 10K.
---
 llvm/include/llvm/CodeGen/SelectionDAGISel.h  |  2 ++
 .../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 22 ++++++++++---
 llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 33 ++++++++++++-------
 3 files changed, 41 insertions(+), 16 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index c604e7eaa0887e..40046e0a8dec9a 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -223,6 +223,8 @@ class SelectionDAGISel : public MachineFunctionPass {
     // Space-optimized forms that implicitly encode integer VT.
     OPC_EmitStringInteger32,
     OPC_EmitRegister,
+    OPC_EmitRegisterI32,
+    OPC_EmitRegisterI64,
     OPC_EmitRegister2,
     OPC_EmitConvertToTarget,
     OPC_EmitConvertToTarget0,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index af49ef17a3f2dd..3dc6e4bbcf46ba 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3612,12 +3612,24 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
           CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch), VT), nullptr));
       continue;
     }
-    case OPC_EmitRegister: {
-      MVT::SimpleValueType VT =
-          static_cast<MVT::SimpleValueType>(MatcherTable[MatcherIndex++]);
+    case OPC_EmitRegister:
+    case OPC_EmitRegisterI32:
+    case OPC_EmitRegisterI64: {
+      MVT::SimpleValueType VT;
+      switch (Opcode) {
+      case OPC_EmitRegisterI32:
+        VT = MVT::i32;
+        break;
+      case OPC_EmitRegisterI64:
+        VT = MVT::i64;
+        break;
+      default:
+        VT = static_cast<MVT::SimpleValueType>(MatcherTable[MatcherIndex++]);
+        break;
+      }
       unsigned RegNo = MatcherTable[MatcherIndex++];
-      RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
-                              CurDAG->getRegister(RegNo, VT), nullptr));
+      RecordedNodes.push_back(std::pair<SDValue, SDNode *>(
+          CurDAG->getRegister(RegNo, VT), nullptr));
       continue;
     }
     case OPC_EmitRegister2: {
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 94799267e89609..6fd5698e7372e4 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -737,24 +737,35 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
   case Matcher::EmitRegister: {
     const EmitRegisterMatcher *Matcher = cast<EmitRegisterMatcher>(N);
     const CodeGenRegister *Reg = Matcher->getReg();
+    MVT::SimpleValueType VT = Matcher->getVT();
     // If the enum value of the register is larger than one byte can handle,
     // use EmitRegister2.
     if (Reg && Reg->EnumValue > 255) {
-      OS << "OPC_EmitRegister2, " << getEnumName(Matcher->getVT()) << ", ";
+      OS << "OPC_EmitRegister2, " << getEnumName(VT) << ", ";
       OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
       return 4;
+    }
+    unsigned OpBytes;
+    switch (VT) {
+    case MVT::i32:
+    case MVT::i64:
+      OpBytes = 1;
+      OS << "OPC_EmitRegisterI" << MVT(VT).getSizeInBits() << ", ";
+      break;
+    default:
+      OpBytes = 2;
+      OS << "OPC_EmitRegister, " << getEnumName(VT) << ", ";
+      break;
+    }
+    if (Reg) {
+      OS << getQualifiedName(Reg->TheDef) << ",\n";
     } else {
-      OS << "OPC_EmitRegister, " << getEnumName(Matcher->getVT()) << ", ";
-      if (Reg) {
-        OS << getQualifiedName(Reg->TheDef) << ",\n";
-      } else {
-        OS << "0 ";
-        if (!OmitComments)
-          OS << "/*zero_reg*/";
-        OS << ",\n";
-      }
-      return 3;
+      OS << "0 ";
+      if (!OmitComments)
+        OS << "/*zero_reg*/";
+      OS << ",\n";
     }
+    return OpBytes + 1;
   }
 
   case Matcher::EmitConvertToTarget: {