[llvm] [LoongArch] Allow delayed decision for ADD/SUB relocations (PR #72960)

[Jinyang He via llvm-commits]

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@@ -190,6 +218,56 @@ bool LoongArchAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
   return true;
 }
 
+bool LoongArchAsmBackend::handleAddSubRelocations(const MCAsmLayout &Layout,
+                                                  const MCFragment &F,
+                                                  const MCFixup &Fixup,
+                                                  const MCValue &Target,
+                                                  uint64_t &FixedValue) const {
+  std::pair<MCFixupKind, MCFixupKind> FK;
+  uint64_t FixedValueA, FixedValueB;
+  const MCSection &SecA = Target.getSymA()->getSymbol().getSection();
+  const MCSection &SecB = Target.getSymB()->getSymbol().getSection();
+
+  // We need record relocation if SecA != SecB. Usually SecB is same as the
+  // section of Fixup, which will be record the relocation as PCRel. If SecB
+  // is not same as the section of Fixup, it will report error. Just return
+  // false and then this work can be finished by handleFixup.
+  if (&SecA != &SecB)
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MQ-mengqing wrote:

Yes. I find the original version, 5904e12bfae8 , which avoided representing difference across sections when the difference is not PCRel. It solved lots of PCRel problems at that time. However, today we have the ADD/SUB relocation types. Non-PCRel representing difference across sections should be implemented in assembly stage. We should do more works in the static link stage. Some other place also should be changed if we remove this. So I think it is beyond this commit and should be submitted separately later.

https://github.com/llvm/llvm-project/pull/72960