[llvm] [SystemZ] Test improvements for atomic load/store instructions (NFC). (PR #75630)
Jonas Paulsson via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 18 10:34:05 PST 2023
https://github.com/JonPsson1 updated https://github.com/llvm/llvm-project/pull/75630
>From bf1124dd4dffedc607b3736dcf3a57d5aa2b08ee Mon Sep 17 00:00:00 2001
From: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: Fri, 15 Dec 2023 10:18:29 -0600
Subject: [PATCH 1/2] [SystemZ] Test improvements for atomic load/store
instructions (NFC).
Make sure to test atomic load and store instructions with and w/out natural
alignment.
---
llvm/test/CodeGen/SystemZ/atomic-load-02.ll | 28 ++++++-
llvm/test/CodeGen/SystemZ/atomic-load-03.ll | 28 ++++++-
llvm/test/CodeGen/SystemZ/atomic-load-04.ll | 28 ++++++-
llvm/test/CodeGen/SystemZ/atomic-load-05.ll | 63 ++++++++++++++--
llvm/test/CodeGen/SystemZ/atomic-load-06.ll | 55 ++++++++++++--
llvm/test/CodeGen/SystemZ/atomic-load-07.ll | 28 ++++++-
llvm/test/CodeGen/SystemZ/atomic-load-08.ll | 73 ++++++++++++++----
llvm/test/CodeGen/SystemZ/atomic-store-02.ll | 35 +++++++--
llvm/test/CodeGen/SystemZ/atomic-store-03.ll | 35 +++++++--
llvm/test/CodeGen/SystemZ/atomic-store-04.ll | 35 +++++++--
llvm/test/CodeGen/SystemZ/atomic-store-05.ll | 79 +++++++++++++++++---
llvm/test/CodeGen/SystemZ/atomic-store-06.ll | 57 ++++++++++++--
llvm/test/CodeGen/SystemZ/atomic-store-07.ll | 52 ++++++++++++-
llvm/test/CodeGen/SystemZ/atomic-store-08.ll | 70 ++++++++++++++---
14 files changed, 578 insertions(+), 88 deletions(-)
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-02.ll b/llvm/test/CodeGen/SystemZ/atomic-load-02.ll
index f152cbacd4012d..32037242f585cd 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-02.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-02.ll
@@ -1,11 +1,33 @@
-; Test 16-bit atomic loads.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test 16-bit atomic loads. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i16 @f1(ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: lh %r2, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lh %r2, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load atomic i16, ptr %src seq_cst, align 2
ret i16 %val
}
+
+define i16 @f2(ptr %src) {
+; CHECK-LABEL: f2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: lgr %r3, %r2
+; CHECK-NEXT: la %r4, 166(%r15)
+; CHECK-NEXT: lghi %r2, 2
+; CHECK-NEXT: lhi %r5, 5
+; CHECK-NEXT: brasl %r14, __atomic_load at PLT
+; CHECK-NEXT: lh %r2, 166(%r15)
+; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+ %val = load atomic i16, ptr %src seq_cst, align 1
+ ret i16 %val
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-03.ll b/llvm/test/CodeGen/SystemZ/atomic-load-03.ll
index 350f8e8e18195c..4675a55cdb2b35 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-03.ll
@@ -1,11 +1,33 @@
-; Test 32-bit atomic loads.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test 32-bit atomic loads. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i32 @f1(ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: l %r2, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: l %r2, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load atomic i32, ptr %src seq_cst, align 4
ret i32 %val
}
+
+define i32 @f2(ptr %src) {
+; CHECK-LABEL: f2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: lgr %r3, %r2
+; CHECK-NEXT: la %r4, 164(%r15)
+; CHECK-NEXT: lghi %r2, 4
+; CHECK-NEXT: lhi %r5, 5
+; CHECK-NEXT: brasl %r14, __atomic_load at PLT
+; CHECK-NEXT: l %r2, 164(%r15)
+; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+ %val = load atomic i32, ptr %src seq_cst, align 2
+ ret i32 %val
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-04.ll b/llvm/test/CodeGen/SystemZ/atomic-load-04.ll
index 9ed1c2b1a597cb..c55adf890dc0cc 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-04.ll
@@ -1,11 +1,33 @@
-; Test 64-bit atomic loads.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test 64-bit atomic loads. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i64 @f1(ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: lg %r2, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lg %r2, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load atomic i64, ptr %src seq_cst, align 8
ret i64 %val
}
+
+define i64 @f2(ptr %src) {
+; CHECK-LABEL: f2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: lgr %r3, %r2
+; CHECK-NEXT: la %r4, 160(%r15)
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: lhi %r5, 5
+; CHECK-NEXT: brasl %r14, __atomic_load at PLT
+; CHECK-NEXT: lg %r2, 160(%r15)
+; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+ %val = load atomic i64, ptr %src seq_cst, align 4
+ ret i64 %val
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-05.ll b/llvm/test/CodeGen/SystemZ/atomic-load-05.ll
index 979f1e684e89ac..fbbd2b1cbabe58 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-05.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-05.ll
@@ -1,14 +1,65 @@
-; Test 128-bit atomic loads.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test 128-bit atomic loads. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s --check-prefix=Z13
define i128 @f1(ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: lpq %r0, 0(%r3)
-; CHECK-DAG: stg %r1, 8(%r2)
-; CHECK-DAG: stg %r0, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lpq %r0, 0(%r3)
+; CHECK-NEXT: stg %r1, 8(%r2)
+; CHECK-NEXT: stg %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+;
+; Z13-LABEL: f1:
+; Z13: # %bb.0:
+; Z13-NEXT: lpq %r0, 0(%r3)
+; Z13-NEXT: stg %r1, 8(%r2)
+; Z13-NEXT: stg %r0, 0(%r2)
+; Z13-NEXT: br %r14
%val = load atomic i128, ptr %src seq_cst, align 16
ret i128 %val
}
+
+define i128 @f2(ptr %src) {
+; CHECK-LABEL: f2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -176
+; CHECK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-NEXT: lgr %r13, %r2
+; CHECK-NEXT: la %r4, 160(%r15)
+; CHECK-NEXT: lghi %r2, 16
+; CHECK-NEXT: lhi %r5, 5
+; CHECK-NEXT: brasl %r14, __atomic_load at PLT
+; CHECK-NEXT: lg %r0, 168(%r15)
+; CHECK-NEXT: lg %r1, 160(%r15)
+; CHECK-NEXT: stg %r0, 8(%r13)
+; CHECK-NEXT: stg %r1, 0(%r13)
+; CHECK-NEXT: lmg %r13, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+;
+; Z13-LABEL: f2:
+; Z13: # %bb.0:
+; Z13-NEXT: stmg %r13, %r15, 104(%r15)
+; Z13-NEXT: .cfi_offset %r13, -56
+; Z13-NEXT: .cfi_offset %r14, -48
+; Z13-NEXT: .cfi_offset %r15, -40
+; Z13-NEXT: aghi %r15, -176
+; Z13-NEXT: .cfi_def_cfa_offset 336
+; Z13-NEXT: lgr %r13, %r2
+; Z13-NEXT: la %r4, 160(%r15)
+; Z13-NEXT: lghi %r2, 16
+; Z13-NEXT: lhi %r5, 5
+; Z13-NEXT: brasl %r14, __atomic_load at PLT
+; Z13-NEXT: vl %v0, 160(%r15), 3
+; Z13-NEXT: vst %v0, 0(%r13), 3
+; Z13-NEXT: lmg %r13, %r15, 280(%r15)
+; Z13-NEXT: br %r14
+ %val = load atomic i128, ptr %src seq_cst, align 8
+ ret i128 %val
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-06.ll b/llvm/test/CodeGen/SystemZ/atomic-load-06.ll
index c9c5504520345c..deb21b3fc4b462 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-06.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-06.ll
@@ -1,13 +1,58 @@
-; Test float atomic loads.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test float atomic loads. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s --check-prefix=Z14
define float @f1(ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: lgf [[R:%r[0-9]+]], 0(%r2)
-; CHECK: sllg [[R]], [[R]], 32
-; CHECK: ldgr %f0, [[R]]
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lgf %r0, 0(%r2)
+; CHECK-NEXT: sllg %r0, %r0, 32
+; CHECK-NEXT: ldgr %f0, %r0
+; CHECK-NEXT: # kill: def $f0s killed $f0s killed $f0d
+; CHECK-NEXT: br %r14
+;
+; Z14-LABEL: f1:
+; Z14: # %bb.0:
+; Z14-NEXT: lde %f0, 0(%r2)
+; Z14-NEXT: br %r14
%val = load atomic float, ptr %src seq_cst, align 4
ret float %val
}
+
+define float @f2(ptr %src) {
+; CHECK-LABEL: f2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: lgr %r3, %r2
+; CHECK-NEXT: la %r4, 164(%r15)
+; CHECK-NEXT: lghi %r2, 4
+; CHECK-NEXT: lhi %r5, 5
+; CHECK-NEXT: brasl %r14, __atomic_load at PLT
+; CHECK-NEXT: le %f0, 164(%r15)
+; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+;
+; Z14-LABEL: f2:
+; Z14: # %bb.0:
+; Z14-NEXT: stmg %r14, %r15, 112(%r15)
+; Z14-NEXT: .cfi_offset %r14, -48
+; Z14-NEXT: .cfi_offset %r15, -40
+; Z14-NEXT: aghi %r15, -168
+; Z14-NEXT: .cfi_def_cfa_offset 328
+; Z14-NEXT: lgr %r3, %r2
+; Z14-NEXT: la %r4, 164(%r15)
+; Z14-NEXT: lghi %r2, 4
+; Z14-NEXT: lhi %r5, 5
+; Z14-NEXT: brasl %r14, __atomic_load at PLT
+; Z14-NEXT: lde %f0, 164(%r15)
+; Z14-NEXT: lmg %r14, %r15, 280(%r15)
+; Z14-NEXT: br %r14
+ %val = load atomic float, ptr %src seq_cst, align 2
+ ret float %val
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-07.ll b/llvm/test/CodeGen/SystemZ/atomic-load-07.ll
index d183cb6af3d20d..a02ed751e487d9 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-07.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-07.ll
@@ -1,11 +1,33 @@
-; Test double atomic loads.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test double atomic loads. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define double @f1(ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: ld %f0, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: ld %f0, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load atomic double, ptr %src seq_cst, align 8
ret double %val
}
+
+define double @f2(ptr %src) {
+; CHECK-LABEL: f2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: lgr %r3, %r2
+; CHECK-NEXT: la %r4, 160(%r15)
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: lhi %r5, 5
+; CHECK-NEXT: brasl %r14, __atomic_load at PLT
+; CHECK-NEXT: ld %f0, 160(%r15)
+; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+ %val = load atomic double, ptr %src seq_cst, align 4
+ ret double %val
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-08.ll b/llvm/test/CodeGen/SystemZ/atomic-load-08.ll
index 069d2168e19af7..588b81512c16bf 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-08.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-08.ll
@@ -1,19 +1,66 @@
-; Test long double atomic loads. Expect a libcall.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test long double atomic loads. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s --check-prefix=Z14
-define void @f1(ptr %ret, ptr %src) {
-; CHECK-LABEL: f1:
-; CHECK: lgr [[RET:%r[0-9]+]], %r2
-; CHECK: la %r4, 160(%r15)
-; CHECK: lghi %r2, 16
-; CHECK: lhi %r5, 5
-; CHECK: brasl %r14, __atomic_load at PLT
-; CHECK: ld [[FL:%f[0-9]+]], 160(%r15)
-; CHECK: ld [[FH:%f[0-9]+]], 168(%r15)
-; CHECK: std [[FL]], 0([[RET]])
-; CHECK: std [[FH]], 8([[RET]])
-; CHECK: br %r14
+define void @fun1(ptr %ret, ptr %src) {
+; CHECK-LABEL: fun1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lpq %r0, 0(%r3)
+; CHECK-NEXT: stg %r1, 8(%r2)
+; CHECK-NEXT: stg %r0, 0(%r2)
+; CHECK-NEXT: br %r14
+;
+; Z14-LABEL: fun1:
+; Z14: # %bb.0:
+; Z14-NEXT: lpq %r0, 0(%r3)
+; Z14-NEXT: stg %r1, 8(%r2)
+; Z14-NEXT: stg %r0, 0(%r2)
+; Z14-NEXT: br %r14
+ %val = load atomic fp128, ptr %src seq_cst, align 16
+ store fp128 %val, ptr %ret, align 8
+ ret void
+}
+
+define void @fun2(ptr %ret, ptr %src) {
+; CHECK-LABEL: fun2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -176
+; CHECK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-NEXT: lgr %r13, %r2
+; CHECK-NEXT: la %r4, 160(%r15)
+; CHECK-NEXT: lghi %r2, 16
+; CHECK-NEXT: lhi %r5, 5
+; CHECK-NEXT: brasl %r14, __atomic_load at PLT
+; CHECK-NEXT: ld %f0, 160(%r15)
+; CHECK-NEXT: ld %f2, 168(%r15)
+; CHECK-NEXT: std %f0, 0(%r13)
+; CHECK-NEXT: std %f2, 8(%r13)
+; CHECK-NEXT: lmg %r13, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+;
+; Z14-LABEL: fun2:
+; Z14: # %bb.0:
+; Z14-NEXT: stmg %r13, %r15, 104(%r15)
+; Z14-NEXT: .cfi_offset %r13, -56
+; Z14-NEXT: .cfi_offset %r14, -48
+; Z14-NEXT: .cfi_offset %r15, -40
+; Z14-NEXT: aghi %r15, -176
+; Z14-NEXT: .cfi_def_cfa_offset 336
+; Z14-NEXT: lgr %r13, %r2
+; Z14-NEXT: la %r4, 160(%r15)
+; Z14-NEXT: lghi %r2, 16
+; Z14-NEXT: lhi %r5, 5
+; Z14-NEXT: brasl %r14, __atomic_load at PLT
+; Z14-NEXT: vl %v0, 160(%r15), 3
+; Z14-NEXT: vst %v0, 0(%r13), 3
+; Z14-NEXT: lmg %r13, %r15, 280(%r15)
+; Z14-NEXT: br %r14
%val = load atomic fp128, ptr %src seq_cst, align 8
store fp128 %val, ptr %ret, align 8
ret void
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-02.ll b/llvm/test/CodeGen/SystemZ/atomic-store-02.ll
index 35785b293325f4..08e3114e03c514 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-02.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-02.ll
@@ -1,21 +1,42 @@
-; Test 16-bit atomic stores.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test 16-bit atomic stores. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i16 %val, ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: sth %r2, 0(%r3)
-; CHECK: bcr 1{{[45]}}, %r0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sth %r2, 0(%r3)
+; CHECK-NEXT: bcr 15, %r0
+; CHECK-NEXT: br %r14
store atomic i16 %val, ptr %src seq_cst, align 2
ret void
}
define void @f2(i16 %val, ptr %src) {
; CHECK-LABEL: f2:
-; CHECK: sth %r2, 0(%r3)
-; CHECK-NOT: bcr 1{{[45]}}, %r0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sth %r2, 0(%r3)
+; CHECK-NEXT: br %r14
store atomic i16 %val, ptr %src monotonic, align 2
ret void
}
+
+define void @f3(i16 %val, ptr %src) {
+; CHECK-LABEL: f3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: sth %r2, 166(%r15)
+; CHECK-NEXT: la %r4, 166(%r15)
+; CHECK-NEXT: lghi %r2, 2
+; CHECK-NEXT: lhi %r5, 5
+; CHECK-NEXT: brasl %r14, __atomic_store at PLT
+; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+ store atomic i16 %val, ptr %src seq_cst, align 1
+ ret void
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-03.ll b/llvm/test/CodeGen/SystemZ/atomic-store-03.ll
index f75f203acea235..2716c00fea74cf 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-03.ll
@@ -1,21 +1,42 @@
-; Test 32-bit atomic stores.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test 32-bit atomic stores. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i32 %val, ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: st %r2, 0(%r3)
-; CHECK: bcr 1{{[45]}}, %r0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %r2, 0(%r3)
+; CHECK-NEXT: bcr 15, %r0
+; CHECK-NEXT: br %r14
store atomic i32 %val, ptr %src seq_cst, align 4
ret void
}
define void @f2(i32 %val, ptr %src) {
; CHECK-LABEL: f2:
-; CHECK: st %r2, 0(%r3)
-; CHECK-NOT: bcr 1{{[45]}}, %r0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %r2, 0(%r3)
+; CHECK-NEXT: br %r14
store atomic i32 %val, ptr %src monotonic, align 4
ret void
}
+
+define void @f3(i32 %val, ptr %src) {
+; CHECK-LABEL: f3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: st %r2, 164(%r15)
+; CHECK-NEXT: la %r4, 164(%r15)
+; CHECK-NEXT: lghi %r2, 4
+; CHECK-NEXT: lhi %r5, 0
+; CHECK-NEXT: brasl %r14, __atomic_store at PLT
+; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+ store atomic i32 %val, ptr %src monotonic, align 2
+ ret void
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-04.ll b/llvm/test/CodeGen/SystemZ/atomic-store-04.ll
index b28153ac4a9ba4..609758d31cb5c8 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-04.ll
@@ -1,21 +1,42 @@
-; Test 64-bit atomic stores.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test 64-bit atomic stores. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i64 %val, ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: stg %r2, 0(%r3)
-; CHECK: bcr 1{{[45]}}, %r0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: stg %r2, 0(%r3)
+; CHECK-NEXT: bcr 15, %r0
+; CHECK-NEXT: br %r14
store atomic i64 %val, ptr %src seq_cst, align 8
ret void
}
define void @f2(i64 %val, ptr %src) {
; CHECK-LABEL: f2:
-; CHECK: stg %r2, 0(%r3)
-; CHECK-NOT: bcr 1{{[45]}}, %r0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: stg %r2, 0(%r3)
+; CHECK-NEXT: br %r14
store atomic i64 %val, ptr %src monotonic, align 8
ret void
}
+
+define void @f3(i64 %val, ptr %src) {
+; CHECK-LABEL: f3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: stg %r2, 160(%r15)
+; CHECK-NEXT: la %r4, 160(%r15)
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: lhi %r5, 0
+; CHECK-NEXT: brasl %r14, __atomic_store at PLT
+; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+ store atomic i64 %val, ptr %src monotonic, align 4
+ ret void
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-05.ll b/llvm/test/CodeGen/SystemZ/atomic-store-05.ll
index dad7d9527b8487..9c422d86b7101b 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-05.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-05.ll
@@ -1,26 +1,81 @@
-; Test 128-bit atomic stores.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test 128-bit atomic stores. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s --check-prefix=Z13
define void @f1(i128 %val, ptr %src) {
; CHECK-LABEL: f1:
-; CHECK-DAG: lg %r1, 8(%r2)
-; CHECK-DAG: lg %r0, 0(%r2)
-; CHECK: stpq %r0, 0(%r3)
-; CHECK: bcr 1{{[45]}}, %r0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lg %r1, 8(%r2)
+; CHECK-NEXT: lg %r0, 0(%r2)
+; CHECK-NEXT: stpq %r0, 0(%r3)
+; CHECK-NEXT: bcr 15, %r0
+; CHECK-NEXT: br %r14
+;
+; Z13-LABEL: f1:
+; Z13: # %bb.0:
+; Z13-NEXT: lg %r1, 8(%r2)
+; Z13-NEXT: lg %r0, 0(%r2)
+; Z13-NEXT: stpq %r0, 0(%r3)
+; Z13-NEXT: bcr 14, %r0
+; Z13-NEXT: br %r14
store atomic i128 %val, ptr %src seq_cst, align 16
ret void
}
define void @f2(i128 %val, ptr %src) {
; CHECK-LABEL: f2:
-; CHECK-DAG: lg %r1, 8(%r2)
-; CHECK-DAG: lg %r0, 0(%r2)
-; CHECK: stpq %r0, 0(%r3)
-; CHECK-NOT: bcr 1{{[45]}}, %r0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lg %r1, 8(%r2)
+; CHECK-NEXT: lg %r0, 0(%r2)
+; CHECK-NEXT: stpq %r0, 0(%r3)
+; CHECK-NEXT: br %r14
+;
+; Z13-LABEL: f2:
+; Z13: # %bb.0:
+; Z13-NEXT: lg %r1, 8(%r2)
+; Z13-NEXT: lg %r0, 0(%r2)
+; Z13-NEXT: stpq %r0, 0(%r3)
+; Z13-NEXT: br %r14
store atomic i128 %val, ptr %src monotonic, align 16
ret void
}
+
+define void @f3(i128 %val, ptr %src) {
+; CHECK-LABEL: f3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -176
+; CHECK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-NEXT: lg %r0, 8(%r2)
+; CHECK-NEXT: lg %r1, 0(%r2)
+; CHECK-NEXT: stg %r0, 168(%r15)
+; CHECK-NEXT: stg %r1, 160(%r15)
+; CHECK-NEXT: la %r4, 160(%r15)
+; CHECK-NEXT: lghi %r2, 16
+; CHECK-NEXT: lhi %r5, 0
+; CHECK-NEXT: brasl %r14, __atomic_store at PLT
+; CHECK-NEXT: lmg %r14, %r15, 288(%r15)
+; CHECK-NEXT: br %r14
+;
+; Z13-LABEL: f3:
+; Z13: # %bb.0:
+; Z13-NEXT: stmg %r14, %r15, 112(%r15)
+; Z13-NEXT: .cfi_offset %r14, -48
+; Z13-NEXT: .cfi_offset %r15, -40
+; Z13-NEXT: aghi %r15, -176
+; Z13-NEXT: .cfi_def_cfa_offset 336
+; Z13-NEXT: vl %v0, 0(%r2), 3
+; Z13-NEXT: la %r4, 160(%r15)
+; Z13-NEXT: lghi %r2, 16
+; Z13-NEXT: lhi %r5, 0
+; Z13-NEXT: vst %v0, 160(%r15), 3
+; Z13-NEXT: brasl %r14, __atomic_store at PLT
+; Z13-NEXT: lmg %r14, %r15, 288(%r15)
+; Z13-NEXT: br %r14
+ store atomic i128 %val, ptr %src monotonic, align 8
+ ret void
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-06.ll b/llvm/test/CodeGen/SystemZ/atomic-store-06.ll
index fd39793faefc8e..1f06051fbfe3fc 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-06.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-06.ll
@@ -1,13 +1,60 @@
-; Test float atomic loads.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test float atomic loads. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s --check-prefix=Z14
define void @f1(ptr %src, float %val) {
; CHECK-LABEL: f1:
-; CHECK: lgdr [[R:%r[0-9]+]], %f0
-; CHECK: srlg [[R]], [[R]], 32
-; CHECK: st [[R]], 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $f0s killed $f0s def $f0d
+; CHECK-NEXT: lgdr %r0, %f0
+; CHECK-NEXT: srlg %r0, %r0, 32
+; CHECK-NEXT: st %r0, 0(%r2)
+; CHECK-NEXT: bcr 15, %r0
+; CHECK-NEXT: br %r14
+;
+; Z14-LABEL: f1:
+; Z14: # %bb.0:
+; Z14-NEXT: ste %f0, 0(%r2)
+; Z14-NEXT: bcr 14, %r0
+; Z14-NEXT: br %r14
store atomic float %val, ptr %src seq_cst, align 4
ret void
}
+
+define void @f2(ptr %src, float %val) {
+; CHECK-LABEL: f2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: lgr %r3, %r2
+; CHECK-NEXT: ste %f0, 164(%r15)
+; CHECK-NEXT: la %r4, 164(%r15)
+; CHECK-NEXT: lghi %r2, 4
+; CHECK-NEXT: lhi %r5, 5
+; CHECK-NEXT: brasl %r14, __atomic_store at PLT
+; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+;
+; Z14-LABEL: f2:
+; Z14: # %bb.0:
+; Z14-NEXT: stmg %r14, %r15, 112(%r15)
+; Z14-NEXT: .cfi_offset %r14, -48
+; Z14-NEXT: .cfi_offset %r15, -40
+; Z14-NEXT: aghi %r15, -168
+; Z14-NEXT: .cfi_def_cfa_offset 328
+; Z14-NEXT: lgr %r3, %r2
+; Z14-NEXT: la %r4, 164(%r15)
+; Z14-NEXT: lghi %r2, 4
+; Z14-NEXT: lhi %r5, 5
+; Z14-NEXT: ste %f0, 164(%r15)
+; Z14-NEXT: brasl %r14, __atomic_store at PLT
+; Z14-NEXT: lmg %r14, %r15, 280(%r15)
+; Z14-NEXT: br %r14
+ store atomic float %val, ptr %src seq_cst, align 2
+ ret void
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-07.ll b/llvm/test/CodeGen/SystemZ/atomic-store-07.ll
index c904b738f2c576..6118fd33fd7e4b 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-07.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-07.ll
@@ -1,11 +1,57 @@
-; Test double atomic stores.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test double atomic stores. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s --check-prefix=Z14
define void @f1(ptr %dst, double %val) {
; CHECK-LABEL: f1:
-; CHECK: std %f0, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: std %f0, 0(%r2)
+; CHECK-NEXT: bcr 15, %r0
+; CHECK-NEXT: br %r14
+;
+; Z14-LABEL: f1:
+; Z14: # %bb.0:
+; Z14-NEXT: std %f0, 0(%r2)
+; Z14-NEXT: bcr 14, %r0
+; Z14-NEXT: br %r14
store atomic double %val, ptr %dst seq_cst, align 8
ret void
}
+
+define void @f2(ptr %dst, double %val) {
+; CHECK-LABEL: f2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: lgr %r3, %r2
+; CHECK-NEXT: std %f0, 160(%r15)
+; CHECK-NEXT: la %r4, 160(%r15)
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: lhi %r5, 5
+; CHECK-NEXT: brasl %r14, __atomic_store at PLT
+; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
+; CHECK-NEXT: br %r14
+;
+; Z14-LABEL: f2:
+; Z14: # %bb.0:
+; Z14-NEXT: stmg %r14, %r15, 112(%r15)
+; Z14-NEXT: .cfi_offset %r14, -48
+; Z14-NEXT: .cfi_offset %r15, -40
+; Z14-NEXT: aghi %r15, -168
+; Z14-NEXT: .cfi_def_cfa_offset 328
+; Z14-NEXT: lgr %r3, %r2
+; Z14-NEXT: la %r4, 160(%r15)
+; Z14-NEXT: lghi %r2, 8
+; Z14-NEXT: lhi %r5, 5
+; Z14-NEXT: std %f0, 160(%r15)
+; Z14-NEXT: brasl %r14, __atomic_store at PLT
+; Z14-NEXT: lmg %r14, %r15, 280(%r15)
+; Z14-NEXT: br %r14
+ store atomic double %val, ptr %dst seq_cst, align 4
+ ret void
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-08.ll b/llvm/test/CodeGen/SystemZ/atomic-store-08.ll
index b33b283e8dbd76..6eb5ba2fe6bc0f 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-08.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-08.ll
@@ -1,19 +1,67 @@
-; Test long double atomic stores. Expect a libcall.
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; Test long double atomic stores. Expect libcall without natural alignment.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s --check-prefix=Z14
define void @f1(ptr %dst, ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: ld [[FL:%f[0-9]+]], 0(%r3)
-; CHECK: ld [[FH:%f[0-9]+]], 8(%r3)
-; CHECK: lgr %r3, %r2
-; CHECK: std [[FL]], 160(%r15)
-; CHECK: std [[FH]], 168(%r15)
-; CHECK: la %r4, 160(%r15)
-; CHECK: lghi %r2, 16
-; CHECK: lhi %r5, 5
-; CHECK: brasl %r14, __atomic_store at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lg %r1, 8(%r3)
+; CHECK-NEXT: lg %r0, 0(%r3)
+; CHECK-NEXT: stpq %r0, 0(%r2)
+; CHECK-NEXT: bcr 15, %r0
+; CHECK-NEXT: br %r14
+;
+; Z14-LABEL: f1:
+; Z14: # %bb.0:
+; Z14-NEXT: lg %r1, 8(%r3)
+; Z14-NEXT: lg %r0, 0(%r3)
+; Z14-NEXT: stpq %r0, 0(%r2)
+; Z14-NEXT: bcr 14, %r0
+; Z14-NEXT: br %r14
+ %val = load fp128, ptr %src, align 8
+ store atomic fp128 %val, ptr %dst seq_cst, align 16
+ ret void
+}
+
+define void @f2(ptr %dst, ptr %src) {
+; CHECK-LABEL: f2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -176
+; CHECK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-NEXT: ld %f0, 0(%r3)
+; CHECK-NEXT: ld %f2, 8(%r3)
+; CHECK-NEXT: lgr %r3, %r2
+; CHECK-NEXT: std %f0, 160(%r15)
+; CHECK-NEXT: std %f2, 168(%r15)
+; CHECK-NEXT: la %r4, 160(%r15)
+; CHECK-NEXT: lghi %r2, 16
+; CHECK-NEXT: lhi %r5, 5
+; CHECK-NEXT: brasl %r14, __atomic_store at PLT
+; CHECK-NEXT: lmg %r14, %r15, 288(%r15)
+; CHECK-NEXT: br %r14
+;
+; Z14-LABEL: f2:
+; Z14: # %bb.0:
+; Z14-NEXT: stmg %r14, %r15, 112(%r15)
+; Z14-NEXT: .cfi_offset %r14, -48
+; Z14-NEXT: .cfi_offset %r15, -40
+; Z14-NEXT: aghi %r15, -176
+; Z14-NEXT: .cfi_def_cfa_offset 336
+; Z14-NEXT: vl %v0, 0(%r3), 3
+; Z14-NEXT: lgr %r0, %r2
+; Z14-NEXT: la %r4, 160(%r15)
+; Z14-NEXT: lghi %r2, 16
+; Z14-NEXT: lgr %r3, %r0
+; Z14-NEXT: lhi %r5, 5
+; Z14-NEXT: vst %v0, 160(%r15), 3
+; Z14-NEXT: brasl %r14, __atomic_store at PLT
+; Z14-NEXT: lmg %r14, %r15, 288(%r15)
+; Z14-NEXT: br %r14
%val = load fp128, ptr %src, align 8
store atomic fp128 %val, ptr %dst seq_cst, align 8
ret void
>From 62bb1e735e82af7026ce6a83b58c86331ac3c44c Mon Sep 17 00:00:00 2001
From: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: Mon, 18 Dec 2023 12:32:38 -0600
Subject: [PATCH 2/2] Revert but update 128-bit tests
---
llvm/test/CodeGen/SystemZ/atomic-load-02.ll | 28 +------
llvm/test/CodeGen/SystemZ/atomic-load-03.ll | 28 +------
llvm/test/CodeGen/SystemZ/atomic-load-04.ll | 28 +------
llvm/test/CodeGen/SystemZ/atomic-load-05.ll | 63 ++--------------
llvm/test/CodeGen/SystemZ/atomic-load-06.ll | 55 ++------------
llvm/test/CodeGen/SystemZ/atomic-load-07.ll | 28 +------
llvm/test/CodeGen/SystemZ/atomic-load-08.ll | 60 ++-------------
llvm/test/CodeGen/SystemZ/atomic-store-02.ll | 35 ++-------
llvm/test/CodeGen/SystemZ/atomic-store-03.ll | 35 ++-------
llvm/test/CodeGen/SystemZ/atomic-store-04.ll | 35 ++-------
llvm/test/CodeGen/SystemZ/atomic-store-05.ll | 79 +++-----------------
llvm/test/CodeGen/SystemZ/atomic-store-06.ll | 57 ++------------
llvm/test/CodeGen/SystemZ/atomic-store-07.ll | 52 +------------
llvm/test/CodeGen/SystemZ/atomic-store-08.ll | 55 +-------------
14 files changed, 73 insertions(+), 565 deletions(-)
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-02.ll b/llvm/test/CodeGen/SystemZ/atomic-load-02.ll
index 32037242f585cd..f152cbacd4012d 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-02.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-02.ll
@@ -1,33 +1,11 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test 16-bit atomic loads. Expect libcall without natural alignment.
+; Test 16-bit atomic loads.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i16 @f1(ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lh %r2, 0(%r2)
-; CHECK-NEXT: br %r14
+; CHECK: lh %r2, 0(%r2)
+; CHECK: br %r14
%val = load atomic i16, ptr %src seq_cst, align 2
ret i16 %val
}
-
-define i16 @f2(ptr %src) {
-; CHECK-LABEL: f2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -168
-; CHECK-NEXT: .cfi_def_cfa_offset 328
-; CHECK-NEXT: lgr %r3, %r2
-; CHECK-NEXT: la %r4, 166(%r15)
-; CHECK-NEXT: lghi %r2, 2
-; CHECK-NEXT: lhi %r5, 5
-; CHECK-NEXT: brasl %r14, __atomic_load at PLT
-; CHECK-NEXT: lh %r2, 166(%r15)
-; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
-; CHECK-NEXT: br %r14
- %val = load atomic i16, ptr %src seq_cst, align 1
- ret i16 %val
-}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-03.ll b/llvm/test/CodeGen/SystemZ/atomic-load-03.ll
index 4675a55cdb2b35..350f8e8e18195c 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-03.ll
@@ -1,33 +1,11 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test 32-bit atomic loads. Expect libcall without natural alignment.
+; Test 32-bit atomic loads.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i32 @f1(ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: l %r2, 0(%r2)
-; CHECK-NEXT: br %r14
+; CHECK: l %r2, 0(%r2)
+; CHECK: br %r14
%val = load atomic i32, ptr %src seq_cst, align 4
ret i32 %val
}
-
-define i32 @f2(ptr %src) {
-; CHECK-LABEL: f2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -168
-; CHECK-NEXT: .cfi_def_cfa_offset 328
-; CHECK-NEXT: lgr %r3, %r2
-; CHECK-NEXT: la %r4, 164(%r15)
-; CHECK-NEXT: lghi %r2, 4
-; CHECK-NEXT: lhi %r5, 5
-; CHECK-NEXT: brasl %r14, __atomic_load at PLT
-; CHECK-NEXT: l %r2, 164(%r15)
-; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
-; CHECK-NEXT: br %r14
- %val = load atomic i32, ptr %src seq_cst, align 2
- ret i32 %val
-}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-04.ll b/llvm/test/CodeGen/SystemZ/atomic-load-04.ll
index c55adf890dc0cc..9ed1c2b1a597cb 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-04.ll
@@ -1,33 +1,11 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test 64-bit atomic loads. Expect libcall without natural alignment.
+; Test 64-bit atomic loads.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i64 @f1(ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lg %r2, 0(%r2)
-; CHECK-NEXT: br %r14
+; CHECK: lg %r2, 0(%r2)
+; CHECK: br %r14
%val = load atomic i64, ptr %src seq_cst, align 8
ret i64 %val
}
-
-define i64 @f2(ptr %src) {
-; CHECK-LABEL: f2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -168
-; CHECK-NEXT: .cfi_def_cfa_offset 328
-; CHECK-NEXT: lgr %r3, %r2
-; CHECK-NEXT: la %r4, 160(%r15)
-; CHECK-NEXT: lghi %r2, 8
-; CHECK-NEXT: lhi %r5, 5
-; CHECK-NEXT: brasl %r14, __atomic_load at PLT
-; CHECK-NEXT: lg %r2, 160(%r15)
-; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
-; CHECK-NEXT: br %r14
- %val = load atomic i64, ptr %src seq_cst, align 4
- ret i64 %val
-}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-05.ll b/llvm/test/CodeGen/SystemZ/atomic-load-05.ll
index fbbd2b1cbabe58..0546889b040aa4 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-05.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-05.ll
@@ -1,65 +1,14 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test 128-bit atomic loads. Expect libcall without natural alignment.
+; Test 128-bit integer atomic loads.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s --check-prefix=Z13
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
define i128 @f1(ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lpq %r0, 0(%r3)
-; CHECK-NEXT: stg %r1, 8(%r2)
-; CHECK-NEXT: stg %r0, 0(%r2)
-; CHECK-NEXT: br %r14
-;
-; Z13-LABEL: f1:
-; Z13: # %bb.0:
-; Z13-NEXT: lpq %r0, 0(%r3)
-; Z13-NEXT: stg %r1, 8(%r2)
-; Z13-NEXT: stg %r0, 0(%r2)
-; Z13-NEXT: br %r14
+; CHECK: lpq %r0, 0(%r3)
+; CHECK-DAG: stg %r1, 8(%r2)
+; CHECK-DAG: stg %r0, 0(%r2)
+; CHECK: br %r14
%val = load atomic i128, ptr %src seq_cst, align 16
ret i128 %val
}
-
-define i128 @f2(ptr %src) {
-; CHECK-LABEL: f2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
-; CHECK-NEXT: .cfi_offset %r13, -56
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -176
-; CHECK-NEXT: .cfi_def_cfa_offset 336
-; CHECK-NEXT: lgr %r13, %r2
-; CHECK-NEXT: la %r4, 160(%r15)
-; CHECK-NEXT: lghi %r2, 16
-; CHECK-NEXT: lhi %r5, 5
-; CHECK-NEXT: brasl %r14, __atomic_load at PLT
-; CHECK-NEXT: lg %r0, 168(%r15)
-; CHECK-NEXT: lg %r1, 160(%r15)
-; CHECK-NEXT: stg %r0, 8(%r13)
-; CHECK-NEXT: stg %r1, 0(%r13)
-; CHECK-NEXT: lmg %r13, %r15, 280(%r15)
-; CHECK-NEXT: br %r14
-;
-; Z13-LABEL: f2:
-; Z13: # %bb.0:
-; Z13-NEXT: stmg %r13, %r15, 104(%r15)
-; Z13-NEXT: .cfi_offset %r13, -56
-; Z13-NEXT: .cfi_offset %r14, -48
-; Z13-NEXT: .cfi_offset %r15, -40
-; Z13-NEXT: aghi %r15, -176
-; Z13-NEXT: .cfi_def_cfa_offset 336
-; Z13-NEXT: lgr %r13, %r2
-; Z13-NEXT: la %r4, 160(%r15)
-; Z13-NEXT: lghi %r2, 16
-; Z13-NEXT: lhi %r5, 5
-; Z13-NEXT: brasl %r14, __atomic_load at PLT
-; Z13-NEXT: vl %v0, 160(%r15), 3
-; Z13-NEXT: vst %v0, 0(%r13), 3
-; Z13-NEXT: lmg %r13, %r15, 280(%r15)
-; Z13-NEXT: br %r14
- %val = load atomic i128, ptr %src seq_cst, align 8
- ret i128 %val
-}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-06.ll b/llvm/test/CodeGen/SystemZ/atomic-load-06.ll
index deb21b3fc4b462..c9c5504520345c 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-06.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-06.ll
@@ -1,58 +1,13 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test float atomic loads. Expect libcall without natural alignment.
+; Test float atomic loads.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s --check-prefix=Z14
define float @f1(ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lgf %r0, 0(%r2)
-; CHECK-NEXT: sllg %r0, %r0, 32
-; CHECK-NEXT: ldgr %f0, %r0
-; CHECK-NEXT: # kill: def $f0s killed $f0s killed $f0d
-; CHECK-NEXT: br %r14
-;
-; Z14-LABEL: f1:
-; Z14: # %bb.0:
-; Z14-NEXT: lde %f0, 0(%r2)
-; Z14-NEXT: br %r14
+; CHECK: lgf [[R:%r[0-9]+]], 0(%r2)
+; CHECK: sllg [[R]], [[R]], 32
+; CHECK: ldgr %f0, [[R]]
+; CHECK: br %r14
%val = load atomic float, ptr %src seq_cst, align 4
ret float %val
}
-
-define float @f2(ptr %src) {
-; CHECK-LABEL: f2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -168
-; CHECK-NEXT: .cfi_def_cfa_offset 328
-; CHECK-NEXT: lgr %r3, %r2
-; CHECK-NEXT: la %r4, 164(%r15)
-; CHECK-NEXT: lghi %r2, 4
-; CHECK-NEXT: lhi %r5, 5
-; CHECK-NEXT: brasl %r14, __atomic_load at PLT
-; CHECK-NEXT: le %f0, 164(%r15)
-; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
-; CHECK-NEXT: br %r14
-;
-; Z14-LABEL: f2:
-; Z14: # %bb.0:
-; Z14-NEXT: stmg %r14, %r15, 112(%r15)
-; Z14-NEXT: .cfi_offset %r14, -48
-; Z14-NEXT: .cfi_offset %r15, -40
-; Z14-NEXT: aghi %r15, -168
-; Z14-NEXT: .cfi_def_cfa_offset 328
-; Z14-NEXT: lgr %r3, %r2
-; Z14-NEXT: la %r4, 164(%r15)
-; Z14-NEXT: lghi %r2, 4
-; Z14-NEXT: lhi %r5, 5
-; Z14-NEXT: brasl %r14, __atomic_load at PLT
-; Z14-NEXT: lde %f0, 164(%r15)
-; Z14-NEXT: lmg %r14, %r15, 280(%r15)
-; Z14-NEXT: br %r14
- %val = load atomic float, ptr %src seq_cst, align 2
- ret float %val
-}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-07.ll b/llvm/test/CodeGen/SystemZ/atomic-load-07.ll
index a02ed751e487d9..d183cb6af3d20d 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-07.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-07.ll
@@ -1,33 +1,11 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test double atomic loads. Expect libcall without natural alignment.
+; Test double atomic loads.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define double @f1(ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: ld %f0, 0(%r2)
-; CHECK-NEXT: br %r14
+; CHECK: ld %f0, 0(%r2)
+; CHECK: br %r14
%val = load atomic double, ptr %src seq_cst, align 8
ret double %val
}
-
-define double @f2(ptr %src) {
-; CHECK-LABEL: f2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -168
-; CHECK-NEXT: .cfi_def_cfa_offset 328
-; CHECK-NEXT: lgr %r3, %r2
-; CHECK-NEXT: la %r4, 160(%r15)
-; CHECK-NEXT: lghi %r2, 8
-; CHECK-NEXT: lhi %r5, 5
-; CHECK-NEXT: brasl %r14, __atomic_load at PLT
-; CHECK-NEXT: ld %f0, 160(%r15)
-; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
-; CHECK-NEXT: br %r14
- %val = load atomic double, ptr %src seq_cst, align 4
- ret double %val
-}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-08.ll b/llvm/test/CodeGen/SystemZ/atomic-load-08.ll
index 588b81512c16bf..879f5679a783be 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-load-08.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-load-08.ll
@@ -1,67 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test long double atomic loads. Expect libcall without natural alignment.
+;
+; Test long double atomic loads. These are emitted by the Clang FE as i128
+; loads with a bitcast, and this test case gets converted into that form as
+; well by the AtomicExpand pass.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s --check-prefix=Z14
-define void @fun1(ptr %ret, ptr %src) {
-; CHECK-LABEL: fun1:
+define void @f1(ptr %ret, ptr %src) {
+; CHECK-LABEL: f1:
; CHECK: # %bb.0:
; CHECK-NEXT: lpq %r0, 0(%r3)
; CHECK-NEXT: stg %r1, 8(%r2)
; CHECK-NEXT: stg %r0, 0(%r2)
; CHECK-NEXT: br %r14
-;
-; Z14-LABEL: fun1:
-; Z14: # %bb.0:
-; Z14-NEXT: lpq %r0, 0(%r3)
-; Z14-NEXT: stg %r1, 8(%r2)
-; Z14-NEXT: stg %r0, 0(%r2)
-; Z14-NEXT: br %r14
%val = load atomic fp128, ptr %src seq_cst, align 16
store fp128 %val, ptr %ret, align 8
ret void
}
-
-define void @fun2(ptr %ret, ptr %src) {
-; CHECK-LABEL: fun2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
-; CHECK-NEXT: .cfi_offset %r13, -56
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -176
-; CHECK-NEXT: .cfi_def_cfa_offset 336
-; CHECK-NEXT: lgr %r13, %r2
-; CHECK-NEXT: la %r4, 160(%r15)
-; CHECK-NEXT: lghi %r2, 16
-; CHECK-NEXT: lhi %r5, 5
-; CHECK-NEXT: brasl %r14, __atomic_load at PLT
-; CHECK-NEXT: ld %f0, 160(%r15)
-; CHECK-NEXT: ld %f2, 168(%r15)
-; CHECK-NEXT: std %f0, 0(%r13)
-; CHECK-NEXT: std %f2, 8(%r13)
-; CHECK-NEXT: lmg %r13, %r15, 280(%r15)
-; CHECK-NEXT: br %r14
-;
-; Z14-LABEL: fun2:
-; Z14: # %bb.0:
-; Z14-NEXT: stmg %r13, %r15, 104(%r15)
-; Z14-NEXT: .cfi_offset %r13, -56
-; Z14-NEXT: .cfi_offset %r14, -48
-; Z14-NEXT: .cfi_offset %r15, -40
-; Z14-NEXT: aghi %r15, -176
-; Z14-NEXT: .cfi_def_cfa_offset 336
-; Z14-NEXT: lgr %r13, %r2
-; Z14-NEXT: la %r4, 160(%r15)
-; Z14-NEXT: lghi %r2, 16
-; Z14-NEXT: lhi %r5, 5
-; Z14-NEXT: brasl %r14, __atomic_load at PLT
-; Z14-NEXT: vl %v0, 160(%r15), 3
-; Z14-NEXT: vst %v0, 0(%r13), 3
-; Z14-NEXT: lmg %r13, %r15, 280(%r15)
-; Z14-NEXT: br %r14
- %val = load atomic fp128, ptr %src seq_cst, align 8
- store fp128 %val, ptr %ret, align 8
- ret void
-}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-02.ll b/llvm/test/CodeGen/SystemZ/atomic-store-02.ll
index 08e3114e03c514..35785b293325f4 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-02.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-02.ll
@@ -1,42 +1,21 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test 16-bit atomic stores. Expect libcall without natural alignment.
+; Test 16-bit atomic stores.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i16 %val, ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: sth %r2, 0(%r3)
-; CHECK-NEXT: bcr 15, %r0
-; CHECK-NEXT: br %r14
+; CHECK: sth %r2, 0(%r3)
+; CHECK: bcr 1{{[45]}}, %r0
+; CHECK: br %r14
store atomic i16 %val, ptr %src seq_cst, align 2
ret void
}
define void @f2(i16 %val, ptr %src) {
; CHECK-LABEL: f2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: sth %r2, 0(%r3)
-; CHECK-NEXT: br %r14
+; CHECK: sth %r2, 0(%r3)
+; CHECK-NOT: bcr 1{{[45]}}, %r0
+; CHECK: br %r14
store atomic i16 %val, ptr %src monotonic, align 2
ret void
}
-
-define void @f3(i16 %val, ptr %src) {
-; CHECK-LABEL: f3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -168
-; CHECK-NEXT: .cfi_def_cfa_offset 328
-; CHECK-NEXT: sth %r2, 166(%r15)
-; CHECK-NEXT: la %r4, 166(%r15)
-; CHECK-NEXT: lghi %r2, 2
-; CHECK-NEXT: lhi %r5, 5
-; CHECK-NEXT: brasl %r14, __atomic_store at PLT
-; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
-; CHECK-NEXT: br %r14
- store atomic i16 %val, ptr %src seq_cst, align 1
- ret void
-}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-03.ll b/llvm/test/CodeGen/SystemZ/atomic-store-03.ll
index 2716c00fea74cf..f75f203acea235 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-03.ll
@@ -1,42 +1,21 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test 32-bit atomic stores. Expect libcall without natural alignment.
+; Test 32-bit atomic stores.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i32 %val, ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: st %r2, 0(%r3)
-; CHECK-NEXT: bcr 15, %r0
-; CHECK-NEXT: br %r14
+; CHECK: st %r2, 0(%r3)
+; CHECK: bcr 1{{[45]}}, %r0
+; CHECK: br %r14
store atomic i32 %val, ptr %src seq_cst, align 4
ret void
}
define void @f2(i32 %val, ptr %src) {
; CHECK-LABEL: f2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: st %r2, 0(%r3)
-; CHECK-NEXT: br %r14
+; CHECK: st %r2, 0(%r3)
+; CHECK-NOT: bcr 1{{[45]}}, %r0
+; CHECK: br %r14
store atomic i32 %val, ptr %src monotonic, align 4
ret void
}
-
-define void @f3(i32 %val, ptr %src) {
-; CHECK-LABEL: f3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -168
-; CHECK-NEXT: .cfi_def_cfa_offset 328
-; CHECK-NEXT: st %r2, 164(%r15)
-; CHECK-NEXT: la %r4, 164(%r15)
-; CHECK-NEXT: lghi %r2, 4
-; CHECK-NEXT: lhi %r5, 0
-; CHECK-NEXT: brasl %r14, __atomic_store at PLT
-; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
-; CHECK-NEXT: br %r14
- store atomic i32 %val, ptr %src monotonic, align 2
- ret void
-}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-04.ll b/llvm/test/CodeGen/SystemZ/atomic-store-04.ll
index 609758d31cb5c8..b28153ac4a9ba4 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-04.ll
@@ -1,42 +1,21 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test 64-bit atomic stores. Expect libcall without natural alignment.
+; Test 64-bit atomic stores.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i64 %val, ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stg %r2, 0(%r3)
-; CHECK-NEXT: bcr 15, %r0
-; CHECK-NEXT: br %r14
+; CHECK: stg %r2, 0(%r3)
+; CHECK: bcr 1{{[45]}}, %r0
+; CHECK: br %r14
store atomic i64 %val, ptr %src seq_cst, align 8
ret void
}
define void @f2(i64 %val, ptr %src) {
; CHECK-LABEL: f2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stg %r2, 0(%r3)
-; CHECK-NEXT: br %r14
+; CHECK: stg %r2, 0(%r3)
+; CHECK-NOT: bcr 1{{[45]}}, %r0
+; CHECK: br %r14
store atomic i64 %val, ptr %src monotonic, align 8
ret void
}
-
-define void @f3(i64 %val, ptr %src) {
-; CHECK-LABEL: f3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -168
-; CHECK-NEXT: .cfi_def_cfa_offset 328
-; CHECK-NEXT: stg %r2, 160(%r15)
-; CHECK-NEXT: la %r4, 160(%r15)
-; CHECK-NEXT: lghi %r2, 8
-; CHECK-NEXT: lhi %r5, 0
-; CHECK-NEXT: brasl %r14, __atomic_store at PLT
-; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
-; CHECK-NEXT: br %r14
- store atomic i64 %val, ptr %src monotonic, align 4
- ret void
-}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-05.ll b/llvm/test/CodeGen/SystemZ/atomic-store-05.ll
index 9c422d86b7101b..c7b45b409972e6 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-05.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-05.ll
@@ -1,81 +1,26 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test 128-bit atomic stores. Expect libcall without natural alignment.
+; Test 128-bit integer atomic stores.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s --check-prefix=Z13
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
define void @f1(i128 %val, ptr %src) {
; CHECK-LABEL: f1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lg %r1, 8(%r2)
-; CHECK-NEXT: lg %r0, 0(%r2)
-; CHECK-NEXT: stpq %r0, 0(%r3)
-; CHECK-NEXT: bcr 15, %r0
-; CHECK-NEXT: br %r14
-;
-; Z13-LABEL: f1:
-; Z13: # %bb.0:
-; Z13-NEXT: lg %r1, 8(%r2)
-; Z13-NEXT: lg %r0, 0(%r2)
-; Z13-NEXT: stpq %r0, 0(%r3)
-; Z13-NEXT: bcr 14, %r0
-; Z13-NEXT: br %r14
+; CHECK-DAG: lg %r1, 8(%r2)
+; CHECK-DAG: lg %r0, 0(%r2)
+; CHECK: stpq %r0, 0(%r3)
+; CHECK: bcr 1{{[45]}}, %r0
+; CHECK: br %r14
store atomic i128 %val, ptr %src seq_cst, align 16
ret void
}
define void @f2(i128 %val, ptr %src) {
; CHECK-LABEL: f2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lg %r1, 8(%r2)
-; CHECK-NEXT: lg %r0, 0(%r2)
-; CHECK-NEXT: stpq %r0, 0(%r3)
-; CHECK-NEXT: br %r14
-;
-; Z13-LABEL: f2:
-; Z13: # %bb.0:
-; Z13-NEXT: lg %r1, 8(%r2)
-; Z13-NEXT: lg %r0, 0(%r2)
-; Z13-NEXT: stpq %r0, 0(%r3)
-; Z13-NEXT: br %r14
+; CHECK-DAG: lg %r1, 8(%r2)
+; CHECK-DAG: lg %r0, 0(%r2)
+; CHECK: stpq %r0, 0(%r3)
+; CHECK-NOT: bcr 1{{[45]}}, %r0
+; CHECK: br %r14
store atomic i128 %val, ptr %src monotonic, align 16
ret void
}
-
-define void @f3(i128 %val, ptr %src) {
-; CHECK-LABEL: f3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -176
-; CHECK-NEXT: .cfi_def_cfa_offset 336
-; CHECK-NEXT: lg %r0, 8(%r2)
-; CHECK-NEXT: lg %r1, 0(%r2)
-; CHECK-NEXT: stg %r0, 168(%r15)
-; CHECK-NEXT: stg %r1, 160(%r15)
-; CHECK-NEXT: la %r4, 160(%r15)
-; CHECK-NEXT: lghi %r2, 16
-; CHECK-NEXT: lhi %r5, 0
-; CHECK-NEXT: brasl %r14, __atomic_store at PLT
-; CHECK-NEXT: lmg %r14, %r15, 288(%r15)
-; CHECK-NEXT: br %r14
-;
-; Z13-LABEL: f3:
-; Z13: # %bb.0:
-; Z13-NEXT: stmg %r14, %r15, 112(%r15)
-; Z13-NEXT: .cfi_offset %r14, -48
-; Z13-NEXT: .cfi_offset %r15, -40
-; Z13-NEXT: aghi %r15, -176
-; Z13-NEXT: .cfi_def_cfa_offset 336
-; Z13-NEXT: vl %v0, 0(%r2), 3
-; Z13-NEXT: la %r4, 160(%r15)
-; Z13-NEXT: lghi %r2, 16
-; Z13-NEXT: lhi %r5, 0
-; Z13-NEXT: vst %v0, 160(%r15), 3
-; Z13-NEXT: brasl %r14, __atomic_store at PLT
-; Z13-NEXT: lmg %r14, %r15, 288(%r15)
-; Z13-NEXT: br %r14
- store atomic i128 %val, ptr %src monotonic, align 8
- ret void
-}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-06.ll b/llvm/test/CodeGen/SystemZ/atomic-store-06.ll
index 1f06051fbfe3fc..fd39793faefc8e 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-06.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-06.ll
@@ -1,60 +1,13 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test float atomic loads. Expect libcall without natural alignment.
+; Test float atomic loads.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s --check-prefix=Z14
define void @f1(ptr %src, float %val) {
; CHECK-LABEL: f1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: # kill: def $f0s killed $f0s def $f0d
-; CHECK-NEXT: lgdr %r0, %f0
-; CHECK-NEXT: srlg %r0, %r0, 32
-; CHECK-NEXT: st %r0, 0(%r2)
-; CHECK-NEXT: bcr 15, %r0
-; CHECK-NEXT: br %r14
-;
-; Z14-LABEL: f1:
-; Z14: # %bb.0:
-; Z14-NEXT: ste %f0, 0(%r2)
-; Z14-NEXT: bcr 14, %r0
-; Z14-NEXT: br %r14
+; CHECK: lgdr [[R:%r[0-9]+]], %f0
+; CHECK: srlg [[R]], [[R]], 32
+; CHECK: st [[R]], 0(%r2)
+; CHECK: br %r14
store atomic float %val, ptr %src seq_cst, align 4
ret void
}
-
-define void @f2(ptr %src, float %val) {
-; CHECK-LABEL: f2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -168
-; CHECK-NEXT: .cfi_def_cfa_offset 328
-; CHECK-NEXT: lgr %r3, %r2
-; CHECK-NEXT: ste %f0, 164(%r15)
-; CHECK-NEXT: la %r4, 164(%r15)
-; CHECK-NEXT: lghi %r2, 4
-; CHECK-NEXT: lhi %r5, 5
-; CHECK-NEXT: brasl %r14, __atomic_store at PLT
-; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
-; CHECK-NEXT: br %r14
-;
-; Z14-LABEL: f2:
-; Z14: # %bb.0:
-; Z14-NEXT: stmg %r14, %r15, 112(%r15)
-; Z14-NEXT: .cfi_offset %r14, -48
-; Z14-NEXT: .cfi_offset %r15, -40
-; Z14-NEXT: aghi %r15, -168
-; Z14-NEXT: .cfi_def_cfa_offset 328
-; Z14-NEXT: lgr %r3, %r2
-; Z14-NEXT: la %r4, 164(%r15)
-; Z14-NEXT: lghi %r2, 4
-; Z14-NEXT: lhi %r5, 5
-; Z14-NEXT: ste %f0, 164(%r15)
-; Z14-NEXT: brasl %r14, __atomic_store at PLT
-; Z14-NEXT: lmg %r14, %r15, 280(%r15)
-; Z14-NEXT: br %r14
- store atomic float %val, ptr %src seq_cst, align 2
- ret void
-}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-07.ll b/llvm/test/CodeGen/SystemZ/atomic-store-07.ll
index 6118fd33fd7e4b..c904b738f2c576 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-07.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-07.ll
@@ -1,57 +1,11 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test double atomic stores. Expect libcall without natural alignment.
+; Test double atomic stores.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s --check-prefix=Z14
define void @f1(ptr %dst, double %val) {
; CHECK-LABEL: f1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: std %f0, 0(%r2)
-; CHECK-NEXT: bcr 15, %r0
-; CHECK-NEXT: br %r14
-;
-; Z14-LABEL: f1:
-; Z14: # %bb.0:
-; Z14-NEXT: std %f0, 0(%r2)
-; Z14-NEXT: bcr 14, %r0
-; Z14-NEXT: br %r14
+; CHECK: std %f0, 0(%r2)
+; CHECK: br %r14
store atomic double %val, ptr %dst seq_cst, align 8
ret void
}
-
-define void @f2(ptr %dst, double %val) {
-; CHECK-LABEL: f2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -168
-; CHECK-NEXT: .cfi_def_cfa_offset 328
-; CHECK-NEXT: lgr %r3, %r2
-; CHECK-NEXT: std %f0, 160(%r15)
-; CHECK-NEXT: la %r4, 160(%r15)
-; CHECK-NEXT: lghi %r2, 8
-; CHECK-NEXT: lhi %r5, 5
-; CHECK-NEXT: brasl %r14, __atomic_store at PLT
-; CHECK-NEXT: lmg %r14, %r15, 280(%r15)
-; CHECK-NEXT: br %r14
-;
-; Z14-LABEL: f2:
-; Z14: # %bb.0:
-; Z14-NEXT: stmg %r14, %r15, 112(%r15)
-; Z14-NEXT: .cfi_offset %r14, -48
-; Z14-NEXT: .cfi_offset %r15, -40
-; Z14-NEXT: aghi %r15, -168
-; Z14-NEXT: .cfi_def_cfa_offset 328
-; Z14-NEXT: lgr %r3, %r2
-; Z14-NEXT: la %r4, 160(%r15)
-; Z14-NEXT: lghi %r2, 8
-; Z14-NEXT: lhi %r5, 5
-; Z14-NEXT: std %f0, 160(%r15)
-; Z14-NEXT: brasl %r14, __atomic_store at PLT
-; Z14-NEXT: lmg %r14, %r15, 280(%r15)
-; Z14-NEXT: br %r14
- store atomic double %val, ptr %dst seq_cst, align 4
- ret void
-}
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-08.ll b/llvm/test/CodeGen/SystemZ/atomic-store-08.ll
index 6eb5ba2fe6bc0f..eab3d3454f01e3 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-08.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-08.ll
@@ -1,8 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test long double atomic stores. Expect libcall without natural alignment.
+;
+; Test long double atomic stores. The atomic store is converted to i128 by
+; the AtomicExpand pass.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s --check-prefix=Z14
define void @f1(ptr %dst, ptr %src) {
; CHECK-LABEL: f1:
@@ -12,57 +13,7 @@ define void @f1(ptr %dst, ptr %src) {
; CHECK-NEXT: stpq %r0, 0(%r2)
; CHECK-NEXT: bcr 15, %r0
; CHECK-NEXT: br %r14
-;
-; Z14-LABEL: f1:
-; Z14: # %bb.0:
-; Z14-NEXT: lg %r1, 8(%r3)
-; Z14-NEXT: lg %r0, 0(%r3)
-; Z14-NEXT: stpq %r0, 0(%r2)
-; Z14-NEXT: bcr 14, %r0
-; Z14-NEXT: br %r14
%val = load fp128, ptr %src, align 8
store atomic fp128 %val, ptr %dst seq_cst, align 16
ret void
}
-
-define void @f2(ptr %dst, ptr %src) {
-; CHECK-LABEL: f2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
-; CHECK-NEXT: .cfi_offset %r14, -48
-; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: aghi %r15, -176
-; CHECK-NEXT: .cfi_def_cfa_offset 336
-; CHECK-NEXT: ld %f0, 0(%r3)
-; CHECK-NEXT: ld %f2, 8(%r3)
-; CHECK-NEXT: lgr %r3, %r2
-; CHECK-NEXT: std %f0, 160(%r15)
-; CHECK-NEXT: std %f2, 168(%r15)
-; CHECK-NEXT: la %r4, 160(%r15)
-; CHECK-NEXT: lghi %r2, 16
-; CHECK-NEXT: lhi %r5, 5
-; CHECK-NEXT: brasl %r14, __atomic_store at PLT
-; CHECK-NEXT: lmg %r14, %r15, 288(%r15)
-; CHECK-NEXT: br %r14
-;
-; Z14-LABEL: f2:
-; Z14: # %bb.0:
-; Z14-NEXT: stmg %r14, %r15, 112(%r15)
-; Z14-NEXT: .cfi_offset %r14, -48
-; Z14-NEXT: .cfi_offset %r15, -40
-; Z14-NEXT: aghi %r15, -176
-; Z14-NEXT: .cfi_def_cfa_offset 336
-; Z14-NEXT: vl %v0, 0(%r3), 3
-; Z14-NEXT: lgr %r0, %r2
-; Z14-NEXT: la %r4, 160(%r15)
-; Z14-NEXT: lghi %r2, 16
-; Z14-NEXT: lgr %r3, %r0
-; Z14-NEXT: lhi %r5, 5
-; Z14-NEXT: vst %v0, 160(%r15), 3
-; Z14-NEXT: brasl %r14, __atomic_store at PLT
-; Z14-NEXT: lmg %r14, %r15, 288(%r15)
-; Z14-NEXT: br %r14
- %val = load fp128, ptr %src, align 8
- store atomic fp128 %val, ptr %dst seq_cst, align 8
- ret void
-}
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