[llvm] GlobalISel lane masks merging (PR #73337)

[Nicolai Hähnle via llvm-commits]

================
@@ -207,9 +207,31 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
   return true;
 }
 
+bool isLaneMask(Register Reg, MachineRegisterInfo *MRI,
+                const SIRegisterInfo &TRI) {
+  if (MRI->getType(Reg) != LLT::scalar(1))
+    return false;
+  const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
+  return RC && TRI.isSGPRClass(RC);
+}
+
 bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
   const Register DefReg = I.getOperand(0).getReg();
   const LLT DefTy = MRI->getType(DefReg);
+  // Lane mask PHIs, PHI where all register operands have sgpr register class
+  // with S1 LLT, are already selected in divergence lowering pass.
+  if (I.getOpcode() == AMDGPU::PHI && isLaneMask(DefReg, MRI, TRI)) {
----------------
nhaehnle wrote:

Perhaps I should be clearer. I don't think we ever have a `PHI` here other than for lane masks. So it would be better for understanding the overall context to say something like:
```
  if (I.getOpcode() == AMDGPU::PHI) {
    assert(isLaneMask(DefReg, MRI, TRI);
    return true;
  }
```

https://github.com/llvm/llvm-project/pull/73337