[llvm] [AMDGPU] Introduce orderign parameter to atomic intrinsics and introduce new llvm.amdgcn.image.atomic.load intrinsic. (PR #73613)

[Nicolai Hähnle via llvm-commits]

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@@ -806,13 +810,15 @@ class AMDGPUImageDimIntrinsic<AMDGPUDimProfile P_,
       !if(P_.IsSample, [llvm_v4i32_ty,           // samp(SGPR)
                         llvm_i1_ty], []),        // unorm(imm)
       [llvm_i32_ty,                              // texfailctrl(imm; bit 0 = tfe, bit 1 = lwe)
-       llvm_i32_ty]),                            // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc)
+       llvm_i32_ty],                             // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc)
+      !if(!or(P_.IsAtomic, P_.IsAtomicLoad), [llvm_i32_ty], [])),       // atomic ordering
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nhaehnle wrote:

We should try to avoid breakage caused by changing the function signature of these intrinsics. How about adding the ordering to the cachepolicy field?

https://github.com/llvm/llvm-project/pull/73613