[llvm] [RISCV][GISel] Instruction select for vector G_ADD, G_SUB (PR #74114)

[Michael Maitland via llvm-commits]

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+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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michaelmaitland wrote:

I think that the test cases are the same for rv32 and rv64. Should we collapse to `rvv/add.mir` and have a run line for rv32 and a run line for rv64? 

```
# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32 %s
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64 %s

https://github.com/llvm/llvm-project/pull/74114