[llvm] d1deeae - [X86] Rename VBROADCASTF128/VBROADCASTI128 to VBROADCASTF128rm/VBROADCASTI128rm (#75040)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 11 03:52:56 PST 2023
Author: Simon Pilgrim
Date: 2023-12-11T11:52:53Z
New Revision: d1deeae0946aad2de36153f3462575813ace88fd
URL: https://github.com/llvm/llvm-project/commit/d1deeae0946aad2de36153f3462575813ace88fd
DIFF: https://github.com/llvm/llvm-project/commit/d1deeae0946aad2de36153f3462575813ace88fd.diff
LOG: [X86] Rename VBROADCASTF128/VBROADCASTI128 to VBROADCASTF128rm/VBROADCASTI128rm (#75040)
Add missing rm postfix to show these are load instructions
Added:
Modified:
llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
llvm/lib/Target/X86/X86FixupVectorConstants.cpp
llvm/lib/Target/X86/X86InstrSSE.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86ReplaceableInstrs.def
llvm/lib/Target/X86/X86SchedAlderlakeP.td
llvm/lib/Target/X86/X86SchedBroadwell.td
llvm/lib/Target/X86/X86SchedHaswell.td
llvm/lib/Target/X86/X86SchedIceLake.td
llvm/lib/Target/X86/X86SchedSapphireRapids.td
llvm/lib/Target/X86/X86SchedSkylakeClient.td
llvm/lib/Target/X86/X86SchedSkylakeServer.td
llvm/lib/Target/X86/X86ScheduleBdVer2.td
llvm/lib/Target/X86/X86ScheduleBtVer2.td
llvm/lib/Target/X86/X86ScheduleZnver1.td
llvm/lib/Target/X86/X86ScheduleZnver2.td
llvm/test/CodeGen/X86/evex-to-vex-compress.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
index ee82faebb57e6..20b37d5a99902 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
@@ -1285,8 +1285,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
Src2Name = getRegName(MI->getOperand(2).getReg());
break;
- case X86::VBROADCASTF128:
- case X86::VBROADCASTI128:
+ case X86::VBROADCASTF128rm:
+ case X86::VBROADCASTI128rm:
CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm)
CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm)
DecodeSubVectorBroadcast(4, 2, ShuffleMask);
diff --git a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
index 99e92bbcf996d..4b6038cb5938b 100644
--- a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
+++ b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
@@ -285,7 +285,7 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF,
case X86::VMOVAPSYrm:
case X86::VMOVUPDYrm:
case X86::VMOVUPSYrm:
- return ConvertToBroadcast(0, X86::VBROADCASTF128, X86::VBROADCASTSDYrm,
+ return ConvertToBroadcast(0, X86::VBROADCASTF128rm, X86::VBROADCASTSDYrm,
X86::VBROADCASTSSYrm, 0, 0, 1);
case X86::VMOVAPDZ128rm:
case X86::VMOVAPSZ128rm:
@@ -318,7 +318,7 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF,
case X86::VMOVDQAYrm:
case X86::VMOVDQUYrm:
return ConvertToBroadcast(
- 0, HasAVX2 ? X86::VBROADCASTI128 : X86::VBROADCASTF128,
+ 0, HasAVX2 ? X86::VBROADCASTI128rm : X86::VBROADCASTF128rm,
HasAVX2 ? X86::VPBROADCASTQYrm : X86::VBROADCASTSDYrm,
HasAVX2 ? X86::VPBROADCASTDYrm : X86::VBROADCASTSSYrm,
HasAVX2 ? X86::VPBROADCASTWYrm : 0, HasAVX2 ? X86::VPBROADCASTBYrm : 0,
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 34eb17af1033d..cf57fe562ed5c 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -7093,35 +7093,35 @@ def VBROADCASTSDYrr : avx2_broadcast_rr<0x19, "vbroadcastsd", VR256,
// halves of a 256-bit vector.
//
let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX2] in
-def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
- (ins i128mem:$src),
- "vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
- Sched<[WriteShuffleLd]>, VEX, VEX_L;
+def VBROADCASTI128rm : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
+ (ins i128mem:$src),
+ "vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
+ Sched<[WriteShuffleLd]>, VEX, VEX_L;
let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX],
ExeDomain = SSEPackedSingle in
-def VBROADCASTF128 : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst),
- (ins f128mem:$src),
- "vbroadcastf128\t{$src, $dst|$dst, $src}", []>,
- Sched<[SchedWriteFShuffle.XMM.Folded]>, VEX, VEX_L;
+def VBROADCASTF128rm : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst),
+ (ins f128mem:$src),
+ "vbroadcastf128\t{$src, $dst|$dst, $src}", []>,
+ Sched<[SchedWriteFShuffle.XMM.Folded]>, VEX, VEX_L;
let Predicates = [HasAVX, NoVLX] in {
def : Pat<(v4f64 (X86SubVBroadcastld128 addr:$src)),
- (VBROADCASTF128 addr:$src)>;
+ (VBROADCASTF128rm addr:$src)>;
def : Pat<(v8f32 (X86SubVBroadcastld128 addr:$src)),
- (VBROADCASTF128 addr:$src)>;
+ (VBROADCASTF128rm addr:$src)>;
// NOTE: We're using FP instructions here, but execution domain fixing can
// convert to integer when profitable.
def : Pat<(v4i64 (X86SubVBroadcastld128 addr:$src)),
- (VBROADCASTF128 addr:$src)>;
+ (VBROADCASTF128rm addr:$src)>;
def : Pat<(v8i32 (X86SubVBroadcastld128 addr:$src)),
- (VBROADCASTF128 addr:$src)>;
+ (VBROADCASTF128rm addr:$src)>;
def : Pat<(v16i16 (X86SubVBroadcastld128 addr:$src)),
- (VBROADCASTF128 addr:$src)>;
+ (VBROADCASTF128rm addr:$src)>;
def : Pat<(v16f16 (X86SubVBroadcastld128 addr:$src)),
- (VBROADCASTF128 addr:$src)>;
+ (VBROADCASTF128rm addr:$src)>;
def : Pat<(v32i8 (X86SubVBroadcastld128 addr:$src)),
- (VBROADCASTF128 addr:$src)>;
+ (VBROADCASTF128rm addr:$src)>;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index cbb0121615241..e1a67f61e7664 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1865,8 +1865,8 @@ static void addConstantComments(const MachineInstr *MI,
// For loads from a constant pool to a vector register, print the constant
// loaded.
CASE_ALL_MOV_RM()
- case X86::VBROADCASTF128:
- case X86::VBROADCASTI128:
+ case X86::VBROADCASTF128rm:
+ case X86::VBROADCASTI128rm:
case X86::VBROADCASTF32X4Z256rm:
case X86::VBROADCASTF32X4rm:
case X86::VBROADCASTF32X8rm:
@@ -1891,8 +1891,8 @@ static void addConstantComments(const MachineInstr *MI,
CASE_128_MOV_RM() NumLanes = 1; BitWidth = 128; break;
CASE_256_MOV_RM() NumLanes = 1; BitWidth = 256; break;
CASE_512_MOV_RM() NumLanes = 1; BitWidth = 512; break;
- case X86::VBROADCASTF128: NumLanes = 2; BitWidth = 128; break;
- case X86::VBROADCASTI128: NumLanes = 2; BitWidth = 128; break;
+ case X86::VBROADCASTF128rm: NumLanes = 2; BitWidth = 128; break;
+ case X86::VBROADCASTI128rm: NumLanes = 2; BitWidth = 128; break;
case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; BitWidth = 128; break;
case X86::VBROADCASTF32X4rm: NumLanes = 4; BitWidth = 128; break;
case X86::VBROADCASTF32X8rm: NumLanes = 2; BitWidth = 256; break;
diff --git a/llvm/lib/Target/X86/X86ReplaceableInstrs.def b/llvm/lib/Target/X86/X86ReplaceableInstrs.def
index 4798275c05192..e1383198d3fe9 100644
--- a/llvm/lib/Target/X86/X86ReplaceableInstrs.def
+++ b/llvm/lib/Target/X86/X86ReplaceableInstrs.def
@@ -202,7 +202,7 @@ ENTRY(VBROADCASTSSYrr, VBROADCASTSSYrr, VPBROADCASTDYrr)
ENTRY(VBROADCASTSSYrm, VBROADCASTSSYrm, VPBROADCASTDYrm)
ENTRY(VBROADCASTSDYrr, VBROADCASTSDYrr, VPBROADCASTQYrr)
ENTRY(VBROADCASTSDYrm, VBROADCASTSDYrm, VPBROADCASTQYrm)
-ENTRY(VBROADCASTF128, VBROADCASTF128, VBROADCASTI128)
+ENTRY(VBROADCASTF128rm, VBROADCASTF128rm, VBROADCASTI128rm)
ENTRY(VBLENDPSYrri, VBLENDPSYrri, VPBLENDDYrri)
ENTRY(VBLENDPSYrmi, VBLENDPSYrmi, VPBLENDDYrmi)
ENTRY(VPERMILPSYmi, VPERMILPSYmi, VPSHUFDYmi)
diff --git a/llvm/lib/Target/X86/X86SchedAlderlakeP.td b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
index 3406a28be2c29..8e3e554282648 100644
--- a/llvm/lib/Target/X86/X86SchedAlderlakeP.td
+++ b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
@@ -1328,7 +1328,7 @@ def ADLPWriteResGroup117 : SchedWriteRes<[ADLPPort02_03_11]> {
let Latency = 8;
}
def : InstRW<[ADLPWriteResGroup117], (instregex "^MMX_MOV(D|Q)64rm$",
- "^VBROADCAST(F|I)128$",
+ "^VBROADCAST(F|I)128rm$",
"^VBROADCASTS(D|S)Yrm$",
"^VMOV(D|SH|SL)DUPYrm$",
"^VPBROADCAST(D|Q)Yrm$")>;
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 8575f747b4d3b..61a8832000e2f 100644
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -946,8 +946,8 @@ def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
let ReleaseAtCycles = [1];
}
def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>;
-def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128,
- VBROADCASTI128,
+def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128rm,
+ VBROADCASTI128rm,
VBROADCASTSDYrm,
VBROADCASTSSYrm,
VMOVDDUPYrm,
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index d10d7684ac127..8795ca95c5593 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -876,8 +876,8 @@ def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> {
let NumMicroOps = 1;
let ReleaseAtCycles = [1];
}
-def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128,
- VBROADCASTI128,
+def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128rm,
+ VBROADCASTI128rm,
VBROADCASTSDYrm,
VBROADCASTSSYrm,
VMOVDDUPYrm,
diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td
index a2aa2655bca28..e27af1433d455 100644
--- a/llvm/lib/Target/X86/X86SchedIceLake.td
+++ b/llvm/lib/Target/X86/X86SchedIceLake.td
@@ -1274,8 +1274,8 @@ def ICXWriteResGroup89 : SchedWriteRes<[ICXPort23]> {
let ReleaseAtCycles = [1];
}
def: InstRW<[ICXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
-def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128,
- VBROADCASTI128,
+def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128rm,
+ VBROADCASTI128rm,
VBROADCASTSDYrm,
VBROADCASTSSYrm,
VMOVDDUPYrm,
diff --git a/llvm/lib/Target/X86/X86SchedSapphireRapids.td b/llvm/lib/Target/X86/X86SchedSapphireRapids.td
index 6a426ef4cf543..4eac53385ae54 100644
--- a/llvm/lib/Target/X86/X86SchedSapphireRapids.td
+++ b/llvm/lib/Target/X86/X86SchedSapphireRapids.td
@@ -1599,7 +1599,7 @@ def SPRWriteResGroup126 : SchedWriteRes<[SPRPort02_03_11]> {
let Latency = 8;
}
def : InstRW<[SPRWriteResGroup126], (instregex "^MMX_MOV(D|Q)64rm$",
- "^VBROADCAST(F|I)128$",
+ "^VBROADCAST(F|I)128rm$",
"^VBROADCAST(F|I)32X(2|4)Z256rm$",
"^VBROADCAST(F|I)32X(8|2Z)rm$",
"^VBROADCAST(F|I)(32|64)X4rm$",
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index 92ed491bc2961..4fa138f69fb92 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -1064,8 +1064,8 @@ def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
let ReleaseAtCycles = [1];
}
def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>;
-def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128,
- VBROADCASTI128,
+def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128rm,
+ VBROADCASTI128rm,
VBROADCASTSDYrm,
VBROADCASTSSYrm,
VMOVDDUPYrm,
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index ed22f95c83e58..8194af8a6e1db 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -1254,8 +1254,8 @@ def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
let ReleaseAtCycles = [1];
}
def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
-def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128,
- VBROADCASTI128,
+def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128rm,
+ VBROADCASTI128rm,
VBROADCASTSDYrm,
VBROADCASTSSYrm,
VMOVDDUPYrm,
diff --git a/llvm/lib/Target/X86/X86ScheduleBdVer2.td b/llvm/lib/Target/X86/X86ScheduleBdVer2.td
index aeeabba45b65e..c9749979576f2 100644
--- a/llvm/lib/Target/X86/X86ScheduleBdVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBdVer2.td
@@ -933,7 +933,7 @@ def PdWriteVBROADCASTF128 : SchedWriteRes<[PdFPU01, PdFPFMA]> {
let ReleaseAtCycles = [1, 3];
let NumMicroOps = 2;
}
-def : InstRW<[PdWriteVBROADCASTF128], (instrs VBROADCASTF128)>;
+def : InstRW<[PdWriteVBROADCASTF128], (instrs VBROADCASTF128rm)>;
defm : PdWriteResXMMPair<WriteFVarShuffle, [PdFPU1, PdFPXBR], 3>;
defm : PdWriteResYMMPair<WriteFVarShuffleY, [PdFPU1, PdFPXBR], 3, [2, 2], 2>;
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
index 8b7d501981b1e..9cba933e82b05 100644
--- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
@@ -816,7 +816,7 @@ def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
}
def : InstRW<[JWriteVBROADCASTYLd], (instrs VBROADCASTSDYrm,
VBROADCASTSSYrm,
- VBROADCASTF128)>;
+ VBROADCASTF128rm)>;
def JWriteJVZEROALL: SchedWriteRes<[]> {
let Latency = 90;
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index e39bcf807a0c0..7ee9eadf84390 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -996,8 +996,8 @@ def ZnWriteBROADCAST : SchedWriteRes<[ZnAGU, ZnFPU13]> {
let Latency = 8;
}
// VBROADCASTF128 / VBROADCASTI128.
-def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128,
- VBROADCASTI128)>;
+def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128rm,
+ VBROADCASTI128rm)>;
// EXTRACTPS.
// r32,x,i.
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver2.td b/llvm/lib/Target/X86/X86ScheduleZnver2.td
index ecaca70bb6775..c0775847798d2 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver2.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver2.td
@@ -1004,8 +1004,8 @@ def Zn2WriteBROADCAST : SchedWriteRes<[Zn2AGU, Zn2FPU13]> {
let Latency = 8;
}
// VBROADCASTF128 / VBROADCASTI128.
-def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128,
- VBROADCASTI128)>;
+def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128rm,
+ VBROADCASTI128rm)>;
// EXTRACTPS.
// r32,x,i.
diff --git a/llvm/test/CodeGen/X86/evex-to-vex-compress.mir b/llvm/test/CodeGen/X86/evex-to-vex-compress.mir
index dc19b2aa8afa5..06d3c1532c3ea 100644
--- a/llvm/test/CodeGen/X86/evex-to-vex-compress.mir
+++ b/llvm/test/CodeGen/X86/evex-to-vex-compress.mir
@@ -677,7 +677,7 @@ body: |
$ymm0 = VPMOVZXWQZ256rm $rip, 1, $noreg, 0, $noreg
; CHECK: $ymm0 = VPMOVZXWQYrr $xmm0
$ymm0 = VPMOVZXWQZ256rr $xmm0
- ; CHECK: $ymm0 = VBROADCASTF128 $rip, 1, $noreg, 0, $noreg
+ ; CHECK: $ymm0 = VBROADCASTF128rm $rip, 1, $noreg, 0, $noreg
$ymm0 = VBROADCASTF32X4Z256rm $rip, 1, $noreg, 0, $noreg
; CHECK: $ymm0 = VBROADCASTSDYrm $rip, 1, $noreg, 0, $noreg
$ymm0 = VBROADCASTF32X2Z256rm $rip, 1, $noreg, 0, $noreg
@@ -703,7 +703,7 @@ body: |
$ymm0 = VPBROADCASTWZ256rm $rip, 1, $noreg, 0, $noreg
; CHECK: $ymm0 = VPBROADCASTWYrr $xmm0
$ymm0 = VPBROADCASTWZ256rr $xmm0
- ; CHECK: $ymm0 = VBROADCASTI128 $rip, 1, $noreg, 0, $noreg
+ ; CHECK: $ymm0 = VBROADCASTI128rm $rip, 1, $noreg, 0, $noreg
$ymm0 = VBROADCASTI32X4Z256rm $rip, 1, $noreg, 0, $noreg
; CHECK: $ymm0 = VPBROADCASTQYrm $rip, 1, $noreg, 0, $noreg
$ymm0 = VBROADCASTI32X2Z256rm $rip, 1, $noreg, 0, $noreg
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