[llvm] [GISEL][RISCV] Legalize llvm.vacopy intrinsic (PR #73066)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 8 10:33:13 PST 2023
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/73066
>From 5f57b81362ff92e33a7d795c97b104b0f96a05fa Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Fri, 17 Nov 2023 09:42:48 -0800
Subject: [PATCH 1/5] [GISEL][RISCV] Legalize llvm.vacopy intrinsic
In the future, we can consider adding a G_VACOPY opcode instead of going
through the GIntrinsic for all targets. We do the approach in this patch because
that is what other targets do today.
---
llvm/docs/GlobalISel/GenericOpcode.rst | 11 +
.../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 1 +
llvm/include/llvm/Support/TargetOpcodes.def | 6 +-
llvm/include/llvm/Target/GenericOpcodes.td | 7 +
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 6 +
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 31 +
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 3 +
.../RISCV/GlobalISel/irtranslator/vacopy.ll | 28 +
.../RISCV/GlobalISel/irtranslator/vararg.ll | 1352 +++++++++++-
llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll | 1896 +++++++++++++++++
10 files changed, 3328 insertions(+), 13 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index 26ff34376fb838..34ba9ec00ab0ea 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -899,6 +899,17 @@ G_VAARG
I found no documentation for this instruction at the time of writing.
+G_VACOPY
+^^^^^^^^
+
+In a target-dependent way, it copies the source va_list element into the
+destination va_list element. This opcode is necessary because the copy may be
+arbitrarily complex.
+
+.. code-block:: none
+
+ G_VACOPY %2(p0), %3(p0)
+
Other Operations
----------------
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
index 711ba10247c34d..81ab4048cfd769 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -433,6 +433,7 @@ class LegalizerHelper {
LegalizeResult lowerMemcpyInline(MachineInstr &MI);
LegalizeResult lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
LegalizeResult lowerVAArg(MachineInstr &MI);
+ LegalizeResult lowerVACopy(MachineInstr &MI);
};
/// Helper function that creates a libcall to the given \p Name using the given
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 941c6d5f8cad8c..5c3da9e65c7406 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -454,9 +454,13 @@ HANDLE_TARGET_OPCODE(G_FCONSTANT)
/// Generic va_start instruction. Stores to its one pointer operand.
HANDLE_TARGET_OPCODE(G_VASTART)
-/// Generic va_start instruction. Stores to its one pointer operand.
+/// Generic va_arg instruction. Stores to its one pointer operand.
HANDLE_TARGET_OPCODE(G_VAARG)
+/// Generic va_copy instruction. Copies the source element into the destination
+/// element.
+HANDLE_TARGET_OPCODE(G_VACOPY)
+
// Generic sign extend
HANDLE_TARGET_OPCODE(G_SEXT)
HANDLE_TARGET_OPCODE(G_SEXT_INREG)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 9a9c09d3c20d61..3b26ab35fa509f 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -155,6 +155,13 @@ def G_VASTART : GenericInstruction {
let mayStore = true;
}
+def G_VACOPY : GenericInstruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins type0:$dest, type0:$src);
+ let hasSideEffects = true;
+ let mayStore = true;
+}
+
def G_VAARG : GenericInstruction {
let OutOperandList = (outs type0:$val);
let InOperandList = (ins type1:$list, unknown:$align);
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 14a4e72152e7c4..d1554140e9fcb6 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2076,6 +2076,12 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
ListSize, Alignment));
return true;
}
+ case Intrinsic::vacopy: {
+ Register DstList = getOrCreateVReg(*CI.getArgOperand(0));
+ Register SrcList = getOrCreateVReg(*CI.getArgOperand(1));
+ MIRBuilder.buildInstr(TargetOpcode::G_VACOPY, {}, {DstList, SrcList});
+ return true;
+ }
case Intrinsic::dbg_value: {
// This form of DBG_VALUE is target-independent.
const DbgValueInst &DI = cast<DbgValueInst>(CI);
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 37e7153be5720e..c59ad2af37da70 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3795,6 +3795,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
return lowerVectorReduction(MI);
case G_VAARG:
return lowerVAArg(MI);
+ case G_VACOPY:
+ return lowerVACopy(MI);
}
}
@@ -7939,6 +7941,35 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerVAArg(MachineInstr &MI) {
return Legalized;
}
+LegalizerHelper::LegalizeResult LegalizerHelper::lowerVACopy(MachineInstr &MI) {
+ MachineFunction &MF = *MI.getMF();
+ const DataLayout &DL = MIRBuilder.getDataLayout();
+ LLVMContext &Ctx = MF.getFunction().getContext();
+
+ Register DstLst = MI.getOperand(0).getReg();
+ LLT PtrTy = MRI.getType(DstLst);
+
+ // Load the source va_list
+ Align Alignment = Align(DL.getABITypeAlign(getTypeForLLT(PtrTy, Ctx)));
+ MachineMemOperand *LoadMMO =
+ MF.getMachineMemOperand(MachinePointerInfo::getUnknownStack(MF),
+ MachineMemOperand::MOLoad, PtrTy, Alignment);
+ Register Tmp = MRI.createGenericVirtualRegister(PtrTy);
+ Register SrcLst = MI.getOperand(1).getReg();
+ MIRBuilder.buildLoad(Tmp, SrcLst, *LoadMMO);
+
+ // Store the result in the destination va_list
+ MachineMemOperand *StoreMMO =
+ MF.getMachineMemOperand(MachinePointerInfo::getUnknownStack(MF),
+ MachineMemOperand::MOStore, PtrTy, Alignment);
+ MIRBuilder.buildStore(DstLst, Tmp, *StoreMMO);
+
+ Observer.changedInstr(MI);
+ Observer.erasingInstr(MI);
+ MI.eraseFromParent();
+ return Legalized;
+}
+
static bool shouldLowerMemFuncForSize(const MachineFunction &MF) {
// On Darwin, -Os means optimize for size without hurting performance, so
// only really optimize for size when -Oz (MinSize) is used.
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index d71a6cf0ab5a64..52018eb56ad338 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -325,6 +325,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.clampScalar(0, s32, sXLen)
.lowerForCartesianProduct({s32, sXLen, p0}, {p0});
+ // The va_list arguments must be a pointer
+ getActionDefinitionsBuilder(G_VACOPY).lowerFor({p0});
+
getLegacyLegalizerInfo().computeTables();
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
new file mode 100644
index 00000000000000..1fdd2e1cdc7650
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
+
+declare void @llvm.va_copy(ptr, ptr)
+define void @test_va_copy(ptr %dest_list, ptr %src_list) {
+ ; RV32I-LABEL: name: test_va_copy
+ ; RV32I: bb.1 (%ir-block.0):
+ ; RV32I-NEXT: liveins: $x10, $x11
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; RV32I-NEXT: G_VACOPY [[COPY]](p0), [[COPY1]]
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: test_va_copy
+ ; RV64I: bb.1 (%ir-block.0):
+ ; RV64I-NEXT: liveins: $x10, $x11
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; RV64I-NEXT: G_VACOPY [[COPY]](p0), [[COPY1]]
+ ; RV64I-NEXT: PseudoRET
+ call void @llvm.va_copy(ptr %dest_list, ptr %src_list)
+ ret void
+}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
index e03ef07b5fc0dd..42d40bb6827037 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
@@ -1,26 +1,27 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=ILP32 %s
+; RUN: | FileCheck -check-prefixes=RV32,ILP32 %s
; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -mattr=+d -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV32D-ILP32 %s
+; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32 %s
; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -mattr=+d -target-abi ilp32f \
; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV32D-ILP32F %s
+; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32F %s
; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -mattr=+d -target-abi ilp32d \
; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV32D-ILP32D %s
+; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32D %s
; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=LP64 %s
+; RUN: | FileCheck -check-prefixes=RV64,LP64 %s
; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -mattr=+d -target-abi lp64f \
; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=LP64F %s
+; RUN: | FileCheck -check-prefixes=RV64,LP64F %s
; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -mattr=+d -target-abi lp64d \
; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=LP64D %s
+; RUN: | FileCheck -check-prefixes=RV64,LP64D %s
; The same vararg calling convention is used for ilp32/ilp32f/ilp32d and for
-; lp64/lp64f/lp64d. Different CHECK lines are required for RV32D due to slight
-; codegen differences due to the way the f64 load operations are lowered.
+; lp64/lp64f/lp64d. Different CHECK lines are required due to slight
+; codegen differences due to the way the f64 load operations are lowered and
+; because the PseudoCALL specifies the calling convention.
; The nounwind attribute is omitted for some of the tests, to check that CFI
; directives are correctly generated.
@@ -29,7 +30,483 @@ declare void @llvm.va_end(ptr)
declare void @notdead(ptr)
-declare i32 @va1(ptr %fmt, ...)
+; Although frontends are recommended to not generate va_arg due to the lack of
+; support for aggregate types, we test simple cases here to ensure they are
+; lowered correctly
+
+define i32 @va1(ptr %fmt, ...) {
+ ; RV32-LABEL: name: va1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.6)
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV32-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s32) into %ir.va, align 1)
+ ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX7]](p0) :: (dereferenceable load (p0) from %ir.va)
+ ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[LOAD]], [[C]](s32)
+ ; RV32-NEXT: G_STORE [[PTR_ADD]](p0), [[FRAME_INDEX7]](p0) :: (store (p0) into %ir.va)
+ ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.argp.cur)
+ ; RV32-NEXT: $x10 = COPY [[LOAD1]](s32)
+ ; RV32-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV64-LABEL: name: va1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.6)
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.4)
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.2)
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; RV64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX6]](p0) :: (store (s64) into %fixed-stack.0)
+ ; RV64-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV64-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s64) into %ir.va, align 1)
+ ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX7]](p0) :: (dereferenceable load (p0) from %ir.va, align 4)
+ ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[LOAD]], [[C]](s64)
+ ; RV64-NEXT: G_STORE [[PTR_ADD]](p0), [[FRAME_INDEX7]](p0) :: (store (p0) into %ir.va, align 4)
+ ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.argp.cur)
+ ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD1]](s32)
+ ; RV64-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64-NEXT: PseudoRET implicit $x10
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %argp.cur = load ptr, ptr %va, align 4
+ %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4
+ store ptr %argp.next, ptr %va, align 4
+ %1 = load i32, ptr %argp.cur, align 4
+ call void @llvm.va_end(ptr %va)
+ ret i32 %1
+}
+
+; Ensure the adjustment when restoring the stack pointer using the frame
+; pointer is correct
+define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind {
+ ; ILP32-LABEL: name: va1_va_arg_alloca
+ ; ILP32: bb.1 (%ir-block.0):
+ ; ILP32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; ILP32-NEXT: {{ $}}
+ ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ILP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; ILP32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.6)
+ ; ILP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; ILP32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; ILP32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; ILP32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; ILP32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; ILP32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.4)
+ ; ILP32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; ILP32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; ILP32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; ILP32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; ILP32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; ILP32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.2)
+ ; ILP32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; ILP32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; ILP32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; ILP32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; ILP32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; ILP32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.0)
+ ; ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; ILP32-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; ILP32-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s32) into %ir.va, align 1)
+ ; ILP32-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; ILP32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[VAARG]], [[C]]
+ ; ILP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; ILP32-NEXT: [[ADD:%[0-9]+]]:_(s32) = nuw G_ADD [[MUL]], [[C1]]
+ ; ILP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -16
+ ; ILP32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
+ ; ILP32-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s32), 1
+ ; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; ILP32-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)
+ ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10
+ ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; ILP32-NEXT: $x10 = COPY [[VAARG]](s32)
+ ; ILP32-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32D-ILP32-LABEL: name: va1_va_arg_alloca
+ ; RV32D-ILP32: bb.1 (%ir-block.0):
+ ; RV32D-ILP32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32D-ILP32-NEXT: {{ $}}
+ ; RV32D-ILP32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32D-ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.6)
+ ; RV32D-ILP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; RV32D-ILP32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32D-ILP32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32D-ILP32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32D-ILP32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32D-ILP32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32D-ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV32D-ILP32-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s32) into %ir.va, align 1)
+ ; RV32D-ILP32-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[VAARG]], [[C]]
+ ; RV32D-ILP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; RV32D-ILP32-NEXT: [[ADD:%[0-9]+]]:_(s32) = nuw G_ADD [[MUL]], [[C1]]
+ ; RV32D-ILP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -16
+ ; RV32D-ILP32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
+ ; RV32D-ILP32-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s32), 1
+ ; RV32D-ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32D-ILP32-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)
+ ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10
+ ; RV32D-ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32D-ILP32-NEXT: $x10 = COPY [[VAARG]](s32)
+ ; RV32D-ILP32-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32D-ILP32F-LABEL: name: va1_va_arg_alloca
+ ; RV32D-ILP32F: bb.1 (%ir-block.0):
+ ; RV32D-ILP32F-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32D-ILP32F-NEXT: {{ $}}
+ ; RV32D-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32D-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.6)
+ ; RV32D-ILP32F-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; RV32D-ILP32F-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32D-ILP32F-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32D-ILP32F-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32D-ILP32F-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32D-ILP32F-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32D-ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV32D-ILP32F-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s32) into %ir.va, align 1)
+ ; RV32D-ILP32F-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32F-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[VAARG]], [[C]]
+ ; RV32D-ILP32F-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; RV32D-ILP32F-NEXT: [[ADD:%[0-9]+]]:_(s32) = nuw G_ADD [[MUL]], [[C1]]
+ ; RV32D-ILP32F-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -16
+ ; RV32D-ILP32F-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
+ ; RV32D-ILP32F-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s32), 1
+ ; RV32D-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32D-ILP32F-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)
+ ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10
+ ; RV32D-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32D-ILP32F-NEXT: $x10 = COPY [[VAARG]](s32)
+ ; RV32D-ILP32F-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32D-ILP32D-LABEL: name: va1_va_arg_alloca
+ ; RV32D-ILP32D: bb.1 (%ir-block.0):
+ ; RV32D-ILP32D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32D-ILP32D-NEXT: {{ $}}
+ ; RV32D-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32D-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.6)
+ ; RV32D-ILP32D-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; RV32D-ILP32D-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32D-ILP32D-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32D-ILP32D-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32D-ILP32D-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32D-ILP32D-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32D-ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV32D-ILP32D-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s32) into %ir.va, align 1)
+ ; RV32D-ILP32D-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32D-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[VAARG]], [[C]]
+ ; RV32D-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; RV32D-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = nuw G_ADD [[MUL]], [[C1]]
+ ; RV32D-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -16
+ ; RV32D-ILP32D-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
+ ; RV32D-ILP32D-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s32), 1
+ ; RV32D-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32D-ILP32D-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)
+ ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10
+ ; RV32D-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32D-ILP32D-NEXT: $x10 = COPY [[VAARG]](s32)
+ ; RV32D-ILP32D-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64-LABEL: name: va1_va_arg_alloca
+ ; LP64: bb.1 (%ir-block.0):
+ ; LP64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; LP64-NEXT: {{ $}}
+ ; LP64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; LP64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; LP64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; LP64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.6)
+ ; LP64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; LP64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; LP64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; LP64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; LP64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; LP64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.4)
+ ; LP64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; LP64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; LP64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; LP64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; LP64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; LP64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.2)
+ ; LP64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; LP64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; LP64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; LP64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; LP64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; LP64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX6]](p0) :: (store (s64) into %fixed-stack.0)
+ ; LP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; LP64-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; LP64-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s64) into %ir.va, align 1)
+ ; LP64-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VAARG]](s32)
+ ; LP64-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
+ ; LP64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
+ ; LP64-NEXT: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
+ ; LP64-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
+ ; LP64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
+ ; LP64-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1
+ ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; LP64-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)
+ ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10
+ ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; LP64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[VAARG]](s32)
+ ; LP64-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; LP64-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64F-LABEL: name: va1_va_arg_alloca
+ ; LP64F: bb.1 (%ir-block.0):
+ ; LP64F-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; LP64F-NEXT: {{ $}}
+ ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; LP64F-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; LP64F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; LP64F-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.6)
+ ; LP64F-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; LP64F-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; LP64F-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; LP64F-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; LP64F-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; LP64F-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.4)
+ ; LP64F-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; LP64F-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; LP64F-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; LP64F-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; LP64F-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; LP64F-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.2)
+ ; LP64F-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; LP64F-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; LP64F-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; LP64F-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; LP64F-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; LP64F-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX6]](p0) :: (store (s64) into %fixed-stack.0)
+ ; LP64F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; LP64F-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; LP64F-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s64) into %ir.va, align 1)
+ ; LP64F-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64F-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VAARG]](s32)
+ ; LP64F-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
+ ; LP64F-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
+ ; LP64F-NEXT: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
+ ; LP64F-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
+ ; LP64F-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
+ ; LP64F-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1
+ ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; LP64F-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)
+ ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10
+ ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; LP64F-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[VAARG]](s32)
+ ; LP64F-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; LP64F-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64D-LABEL: name: va1_va_arg_alloca
+ ; LP64D: bb.1 (%ir-block.0):
+ ; LP64D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; LP64D-NEXT: {{ $}}
+ ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; LP64D-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; LP64D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; LP64D-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.6)
+ ; LP64D-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; LP64D-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; LP64D-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; LP64D-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; LP64D-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; LP64D-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.4)
+ ; LP64D-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; LP64D-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; LP64D-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; LP64D-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; LP64D-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; LP64D-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.2)
+ ; LP64D-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; LP64D-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; LP64D-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; LP64D-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; LP64D-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; LP64D-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX6]](p0) :: (store (s64) into %fixed-stack.0)
+ ; LP64D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; LP64D-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; LP64D-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s64) into %ir.va, align 1)
+ ; LP64D-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64D-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VAARG]](s32)
+ ; LP64D-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
+ ; LP64D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
+ ; LP64D-NEXT: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
+ ; LP64D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
+ ; LP64D-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
+ ; LP64D-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1
+ ; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; LP64D-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)
+ ; LP64D-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10
+ ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; LP64D-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[VAARG]](s32)
+ ; LP64D-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; LP64D-NEXT: PseudoRET implicit $x10
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %1 = va_arg ptr %va, i32
+ %2 = alloca i8, i32 %1
+ call void @notdead(ptr %2)
+ call void @llvm.va_end(ptr %va)
+ ret i32 %1
+}
+
+
+define i32 @va1_va_arg(ptr %fmt, ...) nounwind {
+ ; RV32-LABEL: name: va1_va_arg
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.6)
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV32-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s32) into %ir.va, align 1)
+ ; RV32-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32-NEXT: $x10 = COPY [[VAARG]](s32)
+ ; RV32-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV64-LABEL: name: va1_va_arg
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.6)
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.4)
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.2)
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; RV64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX6]](p0) :: (store (s64) into %fixed-stack.0)
+ ; RV64-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV64-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s64) into %ir.va, align 1)
+ ; RV64-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[VAARG]](s32)
+ ; RV64-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64-NEXT: PseudoRET implicit $x10
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %1 = va_arg ptr %va, i32
+ call void @llvm.va_end(ptr %va)
+ ret i32 %1
+}
define void @va1_caller() nounwind {
; ILP32-LABEL: name: va1_caller
@@ -150,7 +627,180 @@ define void @va1_caller() nounwind {
; Ensure that 2x xlen size+alignment varargs are accessed via an "aligned"
; register pair (where the first register is even-numbered).
-declare i64 @va2(ptr %fmt, ...) nounwind
+define i64 @va2(ptr %fmt, ...) nounwind {
+ ; RV32-LABEL: name: va2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.6)
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -8
+ ; RV32-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV32-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s32) into %ir.va, align 1)
+ ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p0) :: (dereferenceable load (s32) from %ir.va)
+ ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[C]]
+ ; RV32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
+ ; RV32-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ADD]](s32)
+ ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[INTTOPTR]], [[C2]](s32)
+ ; RV32-NEXT: G_STORE [[PTR_ADD]](p0), [[FRAME_INDEX7]](p0) :: (store (p0) into %ir.va)
+ ; RV32-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32)
+ ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[INTTOPTR1]](p0) :: (load (s64) from %ir.3)
+ ; RV32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](s64)
+ ; RV32-NEXT: $x10 = COPY [[UV]](s32)
+ ; RV32-NEXT: $x11 = COPY [[UV1]](s32)
+ ; RV32-NEXT: PseudoRET implicit $x10, implicit $x11
+ ;
+ ; RV64-LABEL: name: va2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.6)
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.4)
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.2)
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; RV64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX6]](p0) :: (store (s64) into %fixed-stack.0)
+ ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -8
+ ; RV64-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV64-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s64) into %ir.va, align 1)
+ ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p0) :: (dereferenceable load (s32) from %ir.va)
+ ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[C]]
+ ; RV64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
+ ; RV64-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ADD]](s32)
+ ; RV64-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[INTTOPTR]], [[C2]](s64)
+ ; RV64-NEXT: G_STORE [[PTR_ADD]](p0), [[FRAME_INDEX7]](p0) :: (store (p0) into %ir.va, align 4)
+ ; RV64-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32)
+ ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[INTTOPTR1]](p0) :: (load (s64) from %ir.3)
+ ; RV64-NEXT: $x10 = COPY [[LOAD1]](s64)
+ ; RV64-NEXT: PseudoRET implicit $x10
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %argp.cur = load i32, ptr %va, align 4
+ %1 = add i32 %argp.cur, 7
+ %2 = and i32 %1, -8
+ %argp.cur.aligned = inttoptr i32 %1 to ptr
+ %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 8
+ store ptr %argp.next, ptr %va, align 4
+ %3 = inttoptr i32 %2 to ptr
+ %4 = load double, ptr %3, align 8
+ %5 = bitcast double %4 to i64
+ call void @llvm.va_end(ptr %va)
+ ret i64 %5
+}
+
+define i64 @va2_va_arg(ptr %fmt, ...) nounwind {
+ ; RV32-LABEL: name: va2_va_arg
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.6)
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV32-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s32) into %ir.va, align 1)
+ ; RV32-NEXT: [[VAARG:%[0-9]+]]:_(s64) = G_VAARG [[FRAME_INDEX7]](p0), 8
+ ; RV32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VAARG]](s64)
+ ; RV32-NEXT: $x10 = COPY [[UV]](s32)
+ ; RV32-NEXT: $x11 = COPY [[UV1]](s32)
+ ; RV32-NEXT: PseudoRET implicit $x10, implicit $x11
+ ;
+ ; RV64-LABEL: name: va2_va_arg
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.6)
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.4)
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.2)
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; RV64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX6]](p0) :: (store (s64) into %fixed-stack.0)
+ ; RV64-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV64-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s64) into %ir.va, align 1)
+ ; RV64-NEXT: [[VAARG:%[0-9]+]]:_(s64) = G_VAARG [[FRAME_INDEX7]](p0), 8
+ ; RV64-NEXT: $x10 = COPY [[VAARG]](s64)
+ ; RV64-NEXT: PseudoRET implicit $x10
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %1 = va_arg ptr %va, double
+ call void @llvm.va_end(ptr %va)
+ %2 = bitcast double %1 to i64
+ ret i64 %2
+}
define void @va2_caller() nounwind {
; ILP32-LABEL: name: va2_caller
@@ -259,7 +909,178 @@ define void @va2_caller() nounwind {
; On RV32, Ensure a named 2*xlen argument is passed in a1 and a2, while the
; vararg double is passed in a4 and a5 (rather than a3 and a4)
-declare i64 @va3(i32 %a, i64 %b, ...) nounwind
+define i64 @va3(i32 %a, i64 %b, ...) nounwind {
+ ; RV32-LABEL: name: va3
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -8
+ ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV32-NEXT: G_VASTART [[FRAME_INDEX5]](p0) :: (store (s32) into %ir.va, align 1)
+ ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p0) :: (dereferenceable load (s32) from %ir.va)
+ ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[C]]
+ ; RV32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
+ ; RV32-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ADD]](s32)
+ ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[INTTOPTR]], [[C2]](s32)
+ ; RV32-NEXT: G_STORE [[PTR_ADD]](p0), [[FRAME_INDEX5]](p0) :: (store (p0) into %ir.va)
+ ; RV32-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32)
+ ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[INTTOPTR1]](p0) :: (load (s64) from %ir.3)
+ ; RV32-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[MV]], [[LOAD1]]
+ ; RV32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ADD1]](s64)
+ ; RV32-NEXT: $x10 = COPY [[UV]](s32)
+ ; RV32-NEXT: $x11 = COPY [[UV1]](s32)
+ ; RV32-NEXT: PseudoRET implicit $x10, implicit $x11
+ ;
+ ; RV64-LABEL: name: va3
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.4)
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.2)
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.0)
+ ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -8
+ ; RV64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV64-NEXT: G_VASTART [[FRAME_INDEX6]](p0) :: (store (s64) into %ir.va, align 1)
+ ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p0) :: (dereferenceable load (s32) from %ir.va)
+ ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[C]]
+ ; RV64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
+ ; RV64-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ADD]](s32)
+ ; RV64-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[INTTOPTR]], [[C2]](s64)
+ ; RV64-NEXT: G_STORE [[PTR_ADD]](p0), [[FRAME_INDEX6]](p0) :: (store (p0) into %ir.va, align 4)
+ ; RV64-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32)
+ ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[INTTOPTR1]](p0) :: (load (s64) from %ir.3)
+ ; RV64-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[LOAD1]]
+ ; RV64-NEXT: $x10 = COPY [[ADD1]](s64)
+ ; RV64-NEXT: PseudoRET implicit $x10
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %argp.cur = load i32, ptr %va, align 4
+ %1 = add i32 %argp.cur, 7
+ %2 = and i32 %1, -8
+ %argp.cur.aligned = inttoptr i32 %1 to ptr
+ %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 8
+ store ptr %argp.next, ptr %va, align 4
+ %3 = inttoptr i32 %2 to ptr
+ %4 = load double, ptr %3, align 8
+ call void @llvm.va_end(ptr %va)
+ %5 = bitcast double %4 to i64
+ %6 = add i64 %b, %5
+ ret i64 %6
+}
+
+define i64 @va3_va_arg(i32 %a, i64 %b, ...) nounwind {
+ ; RV32-LABEL: name: va3_va_arg
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV32-NEXT: G_VASTART [[FRAME_INDEX5]](p0) :: (store (s32) into %ir.va, align 1)
+ ; RV32-NEXT: [[VAARG:%[0-9]+]]:_(s64) = G_VAARG [[FRAME_INDEX5]](p0), 8
+ ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[MV]], [[VAARG]]
+ ; RV32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ADD]](s64)
+ ; RV32-NEXT: $x10 = COPY [[UV]](s32)
+ ; RV32-NEXT: $x11 = COPY [[UV1]](s32)
+ ; RV32-NEXT: PseudoRET implicit $x10, implicit $x11
+ ;
+ ; RV64-LABEL: name: va3_va_arg
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.4)
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.2)
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.0)
+ ; RV64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV64-NEXT: G_VASTART [[FRAME_INDEX6]](p0) :: (store (s64) into %ir.va, align 1)
+ ; RV64-NEXT: [[VAARG:%[0-9]+]]:_(s64) = G_VAARG [[FRAME_INDEX6]](p0), 8
+ ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[VAARG]]
+ ; RV64-NEXT: $x10 = COPY [[ADD]](s64)
+ ; RV64-NEXT: PseudoRET implicit $x10
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %1 = va_arg ptr %va, double
+ call void @llvm.va_end(ptr %va)
+ %2 = bitcast double %1 to i64
+ %3 = add i64 %b, %2
+ ret i64 %3
+}
define void @va3_caller() nounwind {
; ILP32-LABEL: name: va3_caller
@@ -391,3 +1212,510 @@ define void @va3_caller() nounwind {
}
declare void @llvm.va_copy(ptr, ptr)
+
+define i32 @va4_va_copy(i32 %argno, ...) nounwind {
+ ; ILP32-LABEL: name: va4_va_copy
+ ; ILP32: bb.1 (%ir-block.0):
+ ; ILP32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; ILP32-NEXT: {{ $}}
+ ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ILP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; ILP32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.6)
+ ; ILP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; ILP32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; ILP32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; ILP32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; ILP32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; ILP32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.4)
+ ; ILP32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; ILP32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; ILP32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; ILP32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; ILP32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; ILP32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.2)
+ ; ILP32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; ILP32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; ILP32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; ILP32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; ILP32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; ILP32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.0)
+ ; ILP32-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs
+ ; ILP32-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs
+ ; ILP32-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s32) into %ir.vargs, align 1)
+ ; ILP32-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; ILP32-NEXT: G_VACOPY [[FRAME_INDEX8]](p0), [[FRAME_INDEX7]]
+ ; ILP32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX8]](p0) :: (dereferenceable load (p0) from %ir.wargs)
+ ; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; ILP32-NEXT: $x10 = COPY [[LOAD]](p0)
+ ; ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10
+ ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; ILP32-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; ILP32-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; ILP32-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; ILP32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]
+ ; ILP32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]
+ ; ILP32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]
+ ; ILP32-NEXT: $x10 = COPY [[ADD2]](s32)
+ ; ILP32-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32D-ILP32-LABEL: name: va4_va_copy
+ ; RV32D-ILP32: bb.1 (%ir-block.0):
+ ; RV32D-ILP32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32D-ILP32-NEXT: {{ $}}
+ ; RV32D-ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32D-ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.6)
+ ; RV32D-ILP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; RV32D-ILP32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32D-ILP32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32D-ILP32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32D-ILP32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32D-ILP32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32D-ILP32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs
+ ; RV32D-ILP32-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs
+ ; RV32D-ILP32-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s32) into %ir.vargs, align 1)
+ ; RV32D-ILP32-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32-NEXT: G_VACOPY [[FRAME_INDEX8]](p0), [[FRAME_INDEX7]]
+ ; RV32D-ILP32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX8]](p0) :: (dereferenceable load (p0) from %ir.wargs)
+ ; RV32D-ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32D-ILP32-NEXT: $x10 = COPY [[LOAD]](p0)
+ ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10
+ ; RV32D-ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32D-ILP32-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]
+ ; RV32D-ILP32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]
+ ; RV32D-ILP32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]
+ ; RV32D-ILP32-NEXT: $x10 = COPY [[ADD2]](s32)
+ ; RV32D-ILP32-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32D-ILP32F-LABEL: name: va4_va_copy
+ ; RV32D-ILP32F: bb.1 (%ir-block.0):
+ ; RV32D-ILP32F-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32D-ILP32F-NEXT: {{ $}}
+ ; RV32D-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32D-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.6)
+ ; RV32D-ILP32F-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; RV32D-ILP32F-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32D-ILP32F-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32D-ILP32F-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32D-ILP32F-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32D-ILP32F-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32D-ILP32F-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs
+ ; RV32D-ILP32F-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs
+ ; RV32D-ILP32F-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s32) into %ir.vargs, align 1)
+ ; RV32D-ILP32F-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32F-NEXT: G_VACOPY [[FRAME_INDEX8]](p0), [[FRAME_INDEX7]]
+ ; RV32D-ILP32F-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX8]](p0) :: (dereferenceable load (p0) from %ir.wargs)
+ ; RV32D-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32D-ILP32F-NEXT: $x10 = COPY [[LOAD]](p0)
+ ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10
+ ; RV32D-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32D-ILP32F-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32F-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32F-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32F-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]
+ ; RV32D-ILP32F-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]
+ ; RV32D-ILP32F-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]
+ ; RV32D-ILP32F-NEXT: $x10 = COPY [[ADD2]](s32)
+ ; RV32D-ILP32F-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32D-ILP32D-LABEL: name: va4_va_copy
+ ; RV32D-ILP32D: bb.1 (%ir-block.0):
+ ; RV32D-ILP32D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32D-ILP32D-NEXT: {{ $}}
+ ; RV32D-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32D-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.6)
+ ; RV32D-ILP32D-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; RV32D-ILP32D-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32D-ILP32D-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32D-ILP32D-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32D-ILP32D-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32D-ILP32D-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32D-ILP32D-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs
+ ; RV32D-ILP32D-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs
+ ; RV32D-ILP32D-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s32) into %ir.vargs, align 1)
+ ; RV32D-ILP32D-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32D-NEXT: G_VACOPY [[FRAME_INDEX8]](p0), [[FRAME_INDEX7]]
+ ; RV32D-ILP32D-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX8]](p0) :: (dereferenceable load (p0) from %ir.wargs)
+ ; RV32D-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; RV32D-ILP32D-NEXT: $x10 = COPY [[LOAD]](p0)
+ ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10
+ ; RV32D-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; RV32D-ILP32D-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32D-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32D-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; RV32D-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]
+ ; RV32D-ILP32D-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]
+ ; RV32D-ILP32D-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]
+ ; RV32D-ILP32D-NEXT: $x10 = COPY [[ADD2]](s32)
+ ; RV32D-ILP32D-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64-LABEL: name: va4_va_copy
+ ; LP64: bb.1 (%ir-block.0):
+ ; LP64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; LP64-NEXT: {{ $}}
+ ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; LP64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; LP64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; LP64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.6)
+ ; LP64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; LP64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; LP64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; LP64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; LP64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; LP64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.4)
+ ; LP64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; LP64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; LP64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; LP64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; LP64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; LP64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.2)
+ ; LP64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; LP64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; LP64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; LP64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; LP64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; LP64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX6]](p0) :: (store (s64) into %fixed-stack.0)
+ ; LP64-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs
+ ; LP64-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs
+ ; LP64-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s64) into %ir.vargs, align 1)
+ ; LP64-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64-NEXT: G_VACOPY [[FRAME_INDEX8]](p0), [[FRAME_INDEX7]]
+ ; LP64-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX8]](p0) :: (dereferenceable load (p0) from %ir.wargs, align 4)
+ ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; LP64-NEXT: $x10 = COPY [[LOAD]](p0)
+ ; LP64-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10
+ ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; LP64-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]
+ ; LP64-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]
+ ; LP64-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]
+ ; LP64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD2]](s32)
+ ; LP64-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; LP64-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64F-LABEL: name: va4_va_copy
+ ; LP64F: bb.1 (%ir-block.0):
+ ; LP64F-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; LP64F-NEXT: {{ $}}
+ ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64F-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; LP64F-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; LP64F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; LP64F-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.6)
+ ; LP64F-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; LP64F-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; LP64F-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; LP64F-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; LP64F-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; LP64F-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.4)
+ ; LP64F-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; LP64F-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; LP64F-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; LP64F-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; LP64F-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; LP64F-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.2)
+ ; LP64F-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; LP64F-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; LP64F-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; LP64F-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; LP64F-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; LP64F-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX6]](p0) :: (store (s64) into %fixed-stack.0)
+ ; LP64F-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs
+ ; LP64F-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs
+ ; LP64F-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s64) into %ir.vargs, align 1)
+ ; LP64F-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64F-NEXT: G_VACOPY [[FRAME_INDEX8]](p0), [[FRAME_INDEX7]]
+ ; LP64F-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX8]](p0) :: (dereferenceable load (p0) from %ir.wargs, align 4)
+ ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; LP64F-NEXT: $x10 = COPY [[LOAD]](p0)
+ ; LP64F-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10
+ ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; LP64F-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64F-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64F-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64F-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]
+ ; LP64F-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]
+ ; LP64F-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]
+ ; LP64F-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD2]](s32)
+ ; LP64F-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; LP64F-NEXT: PseudoRET implicit $x10
+ ;
+ ; LP64D-LABEL: name: va4_va_copy
+ ; LP64D: bb.1 (%ir-block.0):
+ ; LP64D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; LP64D-NEXT: {{ $}}
+ ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; LP64D-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; LP64D-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; LP64D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; LP64D-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.6)
+ ; LP64D-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; LP64D-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; LP64D-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; LP64D-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; LP64D-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; LP64D-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.4)
+ ; LP64D-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; LP64D-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; LP64D-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; LP64D-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; LP64D-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; LP64D-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.2)
+ ; LP64D-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; LP64D-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; LP64D-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; LP64D-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; LP64D-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; LP64D-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX6]](p0) :: (store (s64) into %fixed-stack.0)
+ ; LP64D-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs
+ ; LP64D-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs
+ ; LP64D-NEXT: G_VASTART [[FRAME_INDEX7]](p0) :: (store (s64) into %ir.vargs, align 1)
+ ; LP64D-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64D-NEXT: G_VACOPY [[FRAME_INDEX8]](p0), [[FRAME_INDEX7]]
+ ; LP64D-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX8]](p0) :: (dereferenceable load (p0) from %ir.wargs, align 4)
+ ; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; LP64D-NEXT: $x10 = COPY [[LOAD]](p0)
+ ; LP64D-NEXT: PseudoCALL target-flags(riscv-plt) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10
+ ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; LP64D-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64D-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64D-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX7]](p0), 4
+ ; LP64D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]
+ ; LP64D-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]
+ ; LP64D-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]
+ ; LP64D-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD2]](s32)
+ ; LP64D-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; LP64D-NEXT: PseudoRET implicit $x10
+ %vargs = alloca ptr
+ %wargs = alloca ptr
+ call void @llvm.va_start(ptr %vargs)
+ %1 = va_arg ptr %vargs, i32
+ call void @llvm.va_copy(ptr %wargs, ptr %vargs)
+ %2 = load ptr, ptr %wargs, align 4
+ call void @notdead(ptr %2)
+ %3 = va_arg ptr %vargs, i32
+ %4 = va_arg ptr %vargs, i32
+ %5 = va_arg ptr %vargs, i32
+ call void @llvm.va_end(ptr %vargs)
+ call void @llvm.va_end(ptr %wargs)
+ %add1 = add i32 %3, %1
+ %add2 = add i32 %add1, %4
+ %add3 = add i32 %add2, %5
+ ret i32 %add3
+}
+
+; A function with no fixed arguments is not valid C, but can be
+; specified in LLVM IR. We must ensure the vararg save area is
+; still set up correctly.
+
+define i32 @va6_no_fixed_args(...) nounwind {
+ ; RV32-LABEL: name: va6_no_fixed_args
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7
+ ; RV32-NEXT: G_STORE [[COPY]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.7, align 16)
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.6)
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX7]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV32-NEXT: G_VASTART [[FRAME_INDEX8]](p0) :: (store (s32) into %ir.va, align 1)
+ ; RV32-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX8]](p0), 4
+ ; RV32-NEXT: $x10 = COPY [[VAARG]](s32)
+ ; RV32-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV64-LABEL: name: va6_no_fixed_args
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7
+ ; RV64-NEXT: G_STORE [[COPY]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.7, align 16)
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.6)
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.4)
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.2)
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; RV64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX6]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; RV64-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX7]](p0) :: (store (s64) into %fixed-stack.0)
+ ; RV64-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va
+ ; RV64-NEXT: G_VASTART [[FRAME_INDEX8]](p0) :: (store (s64) into %ir.va, align 1)
+ ; RV64-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX8]](p0), 4
+ ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[VAARG]](s32)
+ ; RV64-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64-NEXT: PseudoRET implicit $x10
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %1 = va_arg ptr %va, i32
+ call void @llvm.va_end(ptr %va)
+ ret i32 %1
+}
+
+; TODO: improve constant materialization of stack addresses
+
+define i32 @va_large_stack(ptr %fmt, ...) {
+ ; RV32-LABEL: name: va_large_stack
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.6)
+ ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %fixed-stack.5, align 8)
+ ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32) into %fixed-stack.4)
+ ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
+ ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32) into %fixed-stack.3, align 16)
+ ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
+ ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32) into %fixed-stack.2)
+ ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
+ ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32) into %fixed-stack.1, align 8)
+ ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
+ ; RV32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32) into %fixed-stack.0)
+ ; RV32-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.large
+ ; RV32-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.va
+ ; RV32-NEXT: G_VASTART [[FRAME_INDEX8]](p0) :: (store (s32) into %ir.va, align 1)
+ ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX8]](p0) :: (dereferenceable load (p0) from %ir.va)
+ ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[LOAD]], [[C]](s32)
+ ; RV32-NEXT: G_STORE [[PTR_ADD]](p0), [[FRAME_INDEX8]](p0) :: (store (p0) into %ir.va)
+ ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.argp.cur)
+ ; RV32-NEXT: $x10 = COPY [[LOAD1]](s32)
+ ; RV32-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV64-LABEL: name: va_large_stack
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
+ ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.6)
+ ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+ ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
+ ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX1]](p0) :: (store (s64) into %fixed-stack.5, align 16)
+ ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
+ ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
+ ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX2]](p0) :: (store (s64) into %fixed-stack.4)
+ ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
+ ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX3]](p0) :: (store (s64) into %fixed-stack.3, align 16)
+ ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
+ ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX4]](p0) :: (store (s64) into %fixed-stack.2)
+ ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
+ ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX5]](p0) :: (store (s64) into %fixed-stack.1, align 16)
+ ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
+ ; RV64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX6]](p0) :: (store (s64) into %fixed-stack.0)
+ ; RV64-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.large
+ ; RV64-NEXT: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.va
+ ; RV64-NEXT: G_VASTART [[FRAME_INDEX8]](p0) :: (store (s64) into %ir.va, align 1)
+ ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX8]](p0) :: (dereferenceable load (p0) from %ir.va, align 4)
+ ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[LOAD]], [[C]](s64)
+ ; RV64-NEXT: G_STORE [[PTR_ADD]](p0), [[FRAME_INDEX8]](p0) :: (store (p0) into %ir.va, align 4)
+ ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.argp.cur)
+ ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD1]](s32)
+ ; RV64-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64-NEXT: PseudoRET implicit $x10
+ %large = alloca [ 100000000 x i8 ]
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %argp.cur = load ptr, ptr %va, align 4
+ %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4
+ store ptr %argp.next, ptr %va, align 4
+ %1 = load i32, ptr %argp.cur, align 4
+ call void @llvm.va_end(ptr %va)
+ ret i32 %1
+}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
new file mode 100644
index 00000000000000..eba35e2f4944c6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
@@ -0,0 +1,1896 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV32,ILP32 %s
+; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32 %s
+; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d -target-abi ilp32f \
+; RUN: -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32F %s
+; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d -target-abi ilp32d \
+; RUN: -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32D %s
+; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64,LP64 %s
+; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d -target-abi lp64f \
+; RUN: -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64,LP64F %s
+; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d -target-abi lp64d \
+; RUN: -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64,LP64D %s
+
+; The same vararg calling convention is used for ilp32/ilp32f/ilp32d and for
+; lp64/lp64f/lp64d. Different CHECK lines are required due to slight
+; codegen differences due to the way the f64 load operations are lowered and
+; because the PseudoCALL specifies the calling convention.
+; The nounwind attribute is omitted for some of the tests, to check that CFI
+; directives are correctly generated.
+
+declare void @llvm.va_start(ptr)
+declare void @llvm.va_end(ptr)
+
+declare void @notdead(ptr)
+
+; Although frontends are recommended to not generate va_arg due to the lack of
+; support for aggregate types, we test simple cases here to ensure they are
+; lowered correctly
+
+define i32 @va1(ptr %fmt, ...) {
+; RV32-LABEL: va1:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -48
+; RV32-NEXT: .cfi_def_cfa_offset 48
+; RV32-NEXT: addi a0, sp, 20
+; RV32-NEXT: sw a1, 0(a0)
+; RV32-NEXT: addi a0, sp, 24
+; RV32-NEXT: sw a2, 0(a0)
+; RV32-NEXT: addi a0, sp, 28
+; RV32-NEXT: sw a3, 0(a0)
+; RV32-NEXT: addi a0, sp, 32
+; RV32-NEXT: sw a4, 0(a0)
+; RV32-NEXT: addi a0, sp, 36
+; RV32-NEXT: sw a5, 0(a0)
+; RV32-NEXT: addi a0, sp, 40
+; RV32-NEXT: addi a1, sp, 12
+; RV32-NEXT: addi a2, sp, 20
+; RV32-NEXT: srli a3, a1, 16
+; RV32-NEXT: addi a4, a2, 2
+; RV32-NEXT: lui a5, 16
+; RV32-NEXT: addi a5, a5, -1
+; RV32-NEXT: and a5, a1, a5
+; RV32-NEXT: srli a5, a5, 8
+; RV32-NEXT: sb a1, 0(a2)
+; RV32-NEXT: addi a2, a2, 1
+; RV32-NEXT: sb a5, 0(a2)
+; RV32-NEXT: srli a2, a3, 8
+; RV32-NEXT: addi a5, a4, 1
+; RV32-NEXT: sb a3, 0(a4)
+; RV32-NEXT: sb a2, 0(a5)
+; RV32-NEXT: lw a2, 0(a1)
+; RV32-NEXT: sw a6, 0(a0)
+; RV32-NEXT: addi a0, sp, 44
+; RV32-NEXT: sw a7, 0(a0)
+; RV32-NEXT: addi a0, a2, 4
+; RV32-NEXT: sw a0, 0(a1)
+; RV32-NEXT: lw a0, 0(a2)
+; RV32-NEXT: addi sp, sp, 48
+; RV32-NEXT: ret
+;
+; RV64-LABEL: va1:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -80
+; RV64-NEXT: .cfi_def_cfa_offset 80
+; RV64-NEXT: addi a0, sp, 24
+; RV64-NEXT: sd a1, 0(a0)
+; RV64-NEXT: addi a0, sp, 32
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: addi a0, sp, 40
+; RV64-NEXT: sd a3, 0(a0)
+; RV64-NEXT: addi a0, sp, 48
+; RV64-NEXT: sd a4, 0(a0)
+; RV64-NEXT: addi a0, sp, 56
+; RV64-NEXT: sd a5, 0(a0)
+; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: sd a6, 0(a0)
+; RV64-NEXT: addi a0, sp, 8
+; RV64-NEXT: addi a1, sp, 24
+; RV64-NEXT: srli a2, a0, 32
+; RV64-NEXT: addi a3, a1, 4
+; RV64-NEXT: srliw a4, a0, 16
+; RV64-NEXT: addi a5, a1, 2
+; RV64-NEXT: lui a6, 16
+; RV64-NEXT: addi a6, a6, -1
+; RV64-NEXT: and t0, a0, a6
+; RV64-NEXT: srliw t0, t0, 8
+; RV64-NEXT: sb a0, 0(a1)
+; RV64-NEXT: addi a1, a1, 1
+; RV64-NEXT: sb t0, 0(a1)
+; RV64-NEXT: srliw a1, a4, 8
+; RV64-NEXT: addi t0, a5, 1
+; RV64-NEXT: sb a4, 0(a5)
+; RV64-NEXT: sb a1, 0(t0)
+; RV64-NEXT: srliw a1, a2, 16
+; RV64-NEXT: addi a4, a3, 2
+; RV64-NEXT: and a5, a2, a6
+; RV64-NEXT: srliw a5, a5, 8
+; RV64-NEXT: addi a6, a3, 1
+; RV64-NEXT: sb a2, 0(a3)
+; RV64-NEXT: sb a5, 0(a6)
+; RV64-NEXT: srliw a2, a1, 8
+; RV64-NEXT: addi a3, a4, 1
+; RV64-NEXT: sb a1, 0(a4)
+; RV64-NEXT: sb a2, 0(a3)
+; RV64-NEXT: addi a1, a0, 4
+; RV64-NEXT: lw a2, 0(a1)
+; RV64-NEXT: lwu a3, 0(a0)
+; RV64-NEXT: addi a4, sp, 72
+; RV64-NEXT: sd a7, 0(a4)
+; RV64-NEXT: slli a2, a2, 32
+; RV64-NEXT: or a2, a2, a3
+; RV64-NEXT: addi a3, a2, 4
+; RV64-NEXT: srli a4, a3, 32
+; RV64-NEXT: sw a3, 0(a0)
+; RV64-NEXT: sw a4, 0(a1)
+; RV64-NEXT: lw a0, 0(a2)
+; RV64-NEXT: addi sp, sp, 80
+; RV64-NEXT: ret
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %argp.cur = load ptr, ptr %va, align 4
+ %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4
+ store ptr %argp.next, ptr %va, align 4
+ %1 = load i32, ptr %argp.cur, align 4
+ call void @llvm.va_end(ptr %va)
+ ret i32 %1
+}
+
+; Ensure the adjustment when restoring the stack pointer using the frame
+; pointer is correct
+define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind {
+; RV32-LABEL: va1_va_arg_alloca:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -48
+; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32-NEXT: addi s0, sp, 16
+; RV32-NEXT: addi a0, s0, 4
+; RV32-NEXT: sw a1, 0(a0)
+; RV32-NEXT: addi a0, s0, 8
+; RV32-NEXT: sw a2, 0(a0)
+; RV32-NEXT: addi a0, s0, 12
+; RV32-NEXT: sw a3, 0(a0)
+; RV32-NEXT: addi a0, s0, 16
+; RV32-NEXT: sw a4, 0(a0)
+; RV32-NEXT: addi a0, s0, 20
+; RV32-NEXT: sw a5, 0(a0)
+; RV32-NEXT: addi a0, s0, 24
+; RV32-NEXT: sw a6, 0(a0)
+; RV32-NEXT: addi a0, s0, 28
+; RV32-NEXT: sw a7, 0(a0)
+; RV32-NEXT: addi a0, s0, -16
+; RV32-NEXT: addi a1, s0, 4
+; RV32-NEXT: srli a2, a0, 16
+; RV32-NEXT: addi a3, a1, 2
+; RV32-NEXT: lui a4, 16
+; RV32-NEXT: addi a4, a4, -1
+; RV32-NEXT: and a4, a0, a4
+; RV32-NEXT: srli a4, a4, 8
+; RV32-NEXT: addi a5, a1, 1
+; RV32-NEXT: sb a0, 0(a1)
+; RV32-NEXT: sb a4, 0(a5)
+; RV32-NEXT: srli a1, a2, 8
+; RV32-NEXT: addi a4, a3, 1
+; RV32-NEXT: sb a2, 0(a3)
+; RV32-NEXT: sb a1, 0(a4)
+; RV32-NEXT: lw a1, 0(a0)
+; RV32-NEXT: addi a1, a1, 3
+; RV32-NEXT: andi a1, a1, -4
+; RV32-NEXT: addi a2, a1, 4
+; RV32-NEXT: sw a2, 0(a0)
+; RV32-NEXT: lw s1, 0(a1)
+; RV32-NEXT: addi a0, s1, 15
+; RV32-NEXT: andi a0, a0, -16
+; RV32-NEXT: sub a0, sp, a0
+; RV32-NEXT: mv sp, a0
+; RV32-NEXT: call notdead at plt
+; RV32-NEXT: mv a0, s1
+; RV32-NEXT: addi sp, s0, -16
+; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32-NEXT: addi sp, sp, 48
+; RV32-NEXT: ret
+;
+; RV64-LABEL: va1_va_arg_alloca:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -96
+; RV64-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT: addi s0, sp, 32
+; RV64-NEXT: addi a0, s0, 8
+; RV64-NEXT: sd a1, 0(a0)
+; RV64-NEXT: addi a0, s0, 16
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: addi a0, s0, 24
+; RV64-NEXT: sd a3, 0(a0)
+; RV64-NEXT: addi a0, s0, 32
+; RV64-NEXT: sd a4, 0(a0)
+; RV64-NEXT: addi a0, s0, 40
+; RV64-NEXT: sd a5, 0(a0)
+; RV64-NEXT: addi a0, s0, 48
+; RV64-NEXT: sd a6, 0(a0)
+; RV64-NEXT: addi a0, s0, 56
+; RV64-NEXT: sd a7, 0(a0)
+; RV64-NEXT: addi a0, s0, -32
+; RV64-NEXT: addi a1, s0, 8
+; RV64-NEXT: srli a2, a0, 32
+; RV64-NEXT: addi a3, a1, 4
+; RV64-NEXT: srliw a4, a0, 16
+; RV64-NEXT: addi a5, a1, 2
+; RV64-NEXT: lui a6, 16
+; RV64-NEXT: addi a6, a6, -1
+; RV64-NEXT: and a7, a0, a6
+; RV64-NEXT: srliw a7, a7, 8
+; RV64-NEXT: addi t0, a1, 1
+; RV64-NEXT: sb a0, 0(a1)
+; RV64-NEXT: sb a7, 0(t0)
+; RV64-NEXT: srliw a1, a4, 8
+; RV64-NEXT: addi a7, a5, 1
+; RV64-NEXT: sb a4, 0(a5)
+; RV64-NEXT: sb a1, 0(a7)
+; RV64-NEXT: srliw a1, a2, 16
+; RV64-NEXT: addi a4, a3, 2
+; RV64-NEXT: and a5, a2, a6
+; RV64-NEXT: srliw a5, a5, 8
+; RV64-NEXT: addi a6, a3, 1
+; RV64-NEXT: sb a2, 0(a3)
+; RV64-NEXT: sb a5, 0(a6)
+; RV64-NEXT: srliw a2, a1, 8
+; RV64-NEXT: addi a3, a4, 1
+; RV64-NEXT: sb a1, 0(a4)
+; RV64-NEXT: sb a2, 0(a3)
+; RV64-NEXT: ld a1, 0(a0)
+; RV64-NEXT: addi a1, a1, 3
+; RV64-NEXT: andi a1, a1, -4
+; RV64-NEXT: addi a2, a1, 4
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: lw s1, 0(a1)
+; RV64-NEXT: slli a0, s1, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: addi a0, a0, 15
+; RV64-NEXT: andi a0, a0, -16
+; RV64-NEXT: sub a0, sp, a0
+; RV64-NEXT: mv sp, a0
+; RV64-NEXT: call notdead at plt
+; RV64-NEXT: mv a0, s1
+; RV64-NEXT: addi sp, s0, -32
+; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT: addi sp, sp, 96
+; RV64-NEXT: ret
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %1 = va_arg ptr %va, i32
+ %2 = alloca i8, i32 %1
+ call void @notdead(ptr %2)
+ call void @llvm.va_end(ptr %va)
+ ret i32 %1
+}
+
+
+define i32 @va1_va_arg(ptr %fmt, ...) nounwind {
+; RV32-LABEL: va1_va_arg:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -48
+; RV32-NEXT: addi a0, sp, 20
+; RV32-NEXT: sw a1, 0(a0)
+; RV32-NEXT: addi a0, sp, 24
+; RV32-NEXT: sw a2, 0(a0)
+; RV32-NEXT: addi a0, sp, 28
+; RV32-NEXT: sw a3, 0(a0)
+; RV32-NEXT: addi a0, sp, 32
+; RV32-NEXT: sw a4, 0(a0)
+; RV32-NEXT: addi a0, sp, 36
+; RV32-NEXT: sw a5, 0(a0)
+; RV32-NEXT: addi a0, sp, 40
+; RV32-NEXT: sw a6, 0(a0)
+; RV32-NEXT: addi a0, sp, 44
+; RV32-NEXT: sw a7, 0(a0)
+; RV32-NEXT: addi a0, sp, 12
+; RV32-NEXT: addi a1, sp, 20
+; RV32-NEXT: srli a2, a0, 16
+; RV32-NEXT: addi a3, a1, 2
+; RV32-NEXT: lui a4, 16
+; RV32-NEXT: addi a4, a4, -1
+; RV32-NEXT: and a4, a0, a4
+; RV32-NEXT: srli a4, a4, 8
+; RV32-NEXT: addi a5, a1, 1
+; RV32-NEXT: sb a0, 0(a1)
+; RV32-NEXT: sb a4, 0(a5)
+; RV32-NEXT: srli a1, a2, 8
+; RV32-NEXT: addi a4, a3, 1
+; RV32-NEXT: sb a2, 0(a3)
+; RV32-NEXT: sb a1, 0(a4)
+; RV32-NEXT: lw a1, 0(a0)
+; RV32-NEXT: addi a1, a1, 3
+; RV32-NEXT: andi a1, a1, -4
+; RV32-NEXT: addi a2, a1, 4
+; RV32-NEXT: sw a2, 0(a0)
+; RV32-NEXT: lw a0, 0(a1)
+; RV32-NEXT: addi sp, sp, 48
+; RV32-NEXT: ret
+;
+; RV64-LABEL: va1_va_arg:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -80
+; RV64-NEXT: addi a0, sp, 24
+; RV64-NEXT: sd a1, 0(a0)
+; RV64-NEXT: addi a0, sp, 32
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: addi a0, sp, 40
+; RV64-NEXT: sd a3, 0(a0)
+; RV64-NEXT: addi a0, sp, 48
+; RV64-NEXT: sd a4, 0(a0)
+; RV64-NEXT: addi a0, sp, 56
+; RV64-NEXT: sd a5, 0(a0)
+; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: sd a6, 0(a0)
+; RV64-NEXT: addi a0, sp, 72
+; RV64-NEXT: sd a7, 0(a0)
+; RV64-NEXT: addi a0, sp, 8
+; RV64-NEXT: addi a1, sp, 24
+; RV64-NEXT: srli a2, a0, 32
+; RV64-NEXT: addi a3, a1, 4
+; RV64-NEXT: srliw a4, a0, 16
+; RV64-NEXT: addi a5, a1, 2
+; RV64-NEXT: lui a6, 16
+; RV64-NEXT: addi a6, a6, -1
+; RV64-NEXT: and a7, a0, a6
+; RV64-NEXT: srliw a7, a7, 8
+; RV64-NEXT: addi t0, a1, 1
+; RV64-NEXT: sb a0, 0(a1)
+; RV64-NEXT: sb a7, 0(t0)
+; RV64-NEXT: srliw a1, a4, 8
+; RV64-NEXT: addi a7, a5, 1
+; RV64-NEXT: sb a4, 0(a5)
+; RV64-NEXT: sb a1, 0(a7)
+; RV64-NEXT: srliw a1, a2, 16
+; RV64-NEXT: addi a4, a3, 2
+; RV64-NEXT: and a5, a2, a6
+; RV64-NEXT: srliw a5, a5, 8
+; RV64-NEXT: addi a6, a3, 1
+; RV64-NEXT: sb a2, 0(a3)
+; RV64-NEXT: sb a5, 0(a6)
+; RV64-NEXT: srliw a2, a1, 8
+; RV64-NEXT: addi a3, a4, 1
+; RV64-NEXT: sb a1, 0(a4)
+; RV64-NEXT: sb a2, 0(a3)
+; RV64-NEXT: ld a1, 0(a0)
+; RV64-NEXT: addi a1, a1, 3
+; RV64-NEXT: andi a1, a1, -4
+; RV64-NEXT: addi a2, a1, 4
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: lw a0, 0(a1)
+; RV64-NEXT: addi sp, sp, 80
+; RV64-NEXT: ret
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %1 = va_arg ptr %va, i32
+ call void @llvm.va_end(ptr %va)
+ ret i32 %1
+}
+
+define void @va1_caller() nounwind {
+; RV32-LABEL: va1_caller:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: li a4, 2
+; RV32-NEXT: li a2, 0
+; RV32-NEXT: li a3, 0
+; RV32-NEXT: call va1 at plt
+; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: va1_caller:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -16
+; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT: li a2, 2
+; RV64-NEXT: li a1, 0
+; RV64-NEXT: call va1 at plt
+; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT: addi sp, sp, 16
+; RV64-NEXT: ret
+ %1 = call i32 (ptr, ...) @va1(ptr undef, i64 0, i32 2)
+ ret void
+}
+
+; Ensure that 2x xlen size+alignment varargs are accessed via an "aligned"
+; register pair (where the first register is even-numbered).
+
+define i64 @va2(ptr %fmt, ...) nounwind {
+; ILP32-LABEL: va2:
+; ILP32: # %bb.0:
+; ILP32-NEXT: addi sp, sp, -48
+; ILP32-NEXT: addi a0, sp, 20
+; ILP32-NEXT: sw a1, 0(a0)
+; ILP32-NEXT: addi a0, sp, 24
+; ILP32-NEXT: sw a2, 0(a0)
+; ILP32-NEXT: addi a0, sp, 28
+; ILP32-NEXT: sw a3, 0(a0)
+; ILP32-NEXT: addi a0, sp, 32
+; ILP32-NEXT: sw a4, 0(a0)
+; ILP32-NEXT: addi a0, sp, 36
+; ILP32-NEXT: sw a5, 0(a0)
+; ILP32-NEXT: addi a0, sp, 40
+; ILP32-NEXT: addi a1, sp, 12
+; ILP32-NEXT: addi a2, sp, 20
+; ILP32-NEXT: srli a3, a1, 16
+; ILP32-NEXT: addi a4, a2, 2
+; ILP32-NEXT: lui a5, 16
+; ILP32-NEXT: addi a5, a5, -1
+; ILP32-NEXT: and a5, a1, a5
+; ILP32-NEXT: srli a5, a5, 8
+; ILP32-NEXT: sb a1, 0(a2)
+; ILP32-NEXT: addi a2, a2, 1
+; ILP32-NEXT: sb a5, 0(a2)
+; ILP32-NEXT: srli a2, a3, 8
+; ILP32-NEXT: addi a5, a4, 1
+; ILP32-NEXT: sb a3, 0(a4)
+; ILP32-NEXT: sb a2, 0(a5)
+; ILP32-NEXT: lw a2, 0(a1)
+; ILP32-NEXT: sw a6, 0(a0)
+; ILP32-NEXT: addi a0, sp, 44
+; ILP32-NEXT: sw a7, 0(a0)
+; ILP32-NEXT: addi a2, a2, 7
+; ILP32-NEXT: andi a3, a2, -8
+; ILP32-NEXT: addi a2, a2, 8
+; ILP32-NEXT: sw a2, 0(a1)
+; ILP32-NEXT: lw a0, 0(a3)
+; ILP32-NEXT: addi a3, a3, 4
+; ILP32-NEXT: lw a1, 0(a3)
+; ILP32-NEXT: addi sp, sp, 48
+; ILP32-NEXT: ret
+;
+; RV32D-ILP32-LABEL: va2:
+; RV32D-ILP32: # %bb.0:
+; RV32D-ILP32-NEXT: addi sp, sp, -48
+; RV32D-ILP32-NEXT: addi a0, sp, 20
+; RV32D-ILP32-NEXT: sw a1, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 24
+; RV32D-ILP32-NEXT: sw a2, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 28
+; RV32D-ILP32-NEXT: sw a3, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 32
+; RV32D-ILP32-NEXT: sw a4, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 36
+; RV32D-ILP32-NEXT: sw a5, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 40
+; RV32D-ILP32-NEXT: addi a1, sp, 12
+; RV32D-ILP32-NEXT: addi a2, sp, 20
+; RV32D-ILP32-NEXT: srli a3, a1, 16
+; RV32D-ILP32-NEXT: addi a4, a2, 2
+; RV32D-ILP32-NEXT: lui a5, 16
+; RV32D-ILP32-NEXT: addi a5, a5, -1
+; RV32D-ILP32-NEXT: and a5, a1, a5
+; RV32D-ILP32-NEXT: srli a5, a5, 8
+; RV32D-ILP32-NEXT: sb a1, 0(a2)
+; RV32D-ILP32-NEXT: addi a2, a2, 1
+; RV32D-ILP32-NEXT: sb a5, 0(a2)
+; RV32D-ILP32-NEXT: srli a2, a3, 8
+; RV32D-ILP32-NEXT: addi a5, a4, 1
+; RV32D-ILP32-NEXT: sb a3, 0(a4)
+; RV32D-ILP32-NEXT: sb a2, 0(a5)
+; RV32D-ILP32-NEXT: lw a2, 0(a1)
+; RV32D-ILP32-NEXT: sw a6, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 44
+; RV32D-ILP32-NEXT: sw a7, 0(a0)
+; RV32D-ILP32-NEXT: addi a2, a2, 7
+; RV32D-ILP32-NEXT: andi a0, a2, -8
+; RV32D-ILP32-NEXT: fld fa5, 0(a0)
+; RV32D-ILP32-NEXT: addi a2, a2, 8
+; RV32D-ILP32-NEXT: sw a2, 0(a1)
+; RV32D-ILP32-NEXT: fsd fa5, 0(sp)
+; RV32D-ILP32-NEXT: lw a0, 0(sp)
+; RV32D-ILP32-NEXT: lw a1, 4(sp)
+; RV32D-ILP32-NEXT: addi sp, sp, 48
+; RV32D-ILP32-NEXT: ret
+;
+; RV32D-ILP32F-LABEL: va2:
+; RV32D-ILP32F: # %bb.0:
+; RV32D-ILP32F-NEXT: addi sp, sp, -48
+; RV32D-ILP32F-NEXT: addi a0, sp, 20
+; RV32D-ILP32F-NEXT: sw a1, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 24
+; RV32D-ILP32F-NEXT: sw a2, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 28
+; RV32D-ILP32F-NEXT: sw a3, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 32
+; RV32D-ILP32F-NEXT: sw a4, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 36
+; RV32D-ILP32F-NEXT: sw a5, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 40
+; RV32D-ILP32F-NEXT: addi a1, sp, 12
+; RV32D-ILP32F-NEXT: addi a2, sp, 20
+; RV32D-ILP32F-NEXT: srli a3, a1, 16
+; RV32D-ILP32F-NEXT: addi a4, a2, 2
+; RV32D-ILP32F-NEXT: lui a5, 16
+; RV32D-ILP32F-NEXT: addi a5, a5, -1
+; RV32D-ILP32F-NEXT: and a5, a1, a5
+; RV32D-ILP32F-NEXT: srli a5, a5, 8
+; RV32D-ILP32F-NEXT: sb a1, 0(a2)
+; RV32D-ILP32F-NEXT: addi a2, a2, 1
+; RV32D-ILP32F-NEXT: sb a5, 0(a2)
+; RV32D-ILP32F-NEXT: srli a2, a3, 8
+; RV32D-ILP32F-NEXT: addi a5, a4, 1
+; RV32D-ILP32F-NEXT: sb a3, 0(a4)
+; RV32D-ILP32F-NEXT: sb a2, 0(a5)
+; RV32D-ILP32F-NEXT: lw a2, 0(a1)
+; RV32D-ILP32F-NEXT: sw a6, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 44
+; RV32D-ILP32F-NEXT: sw a7, 0(a0)
+; RV32D-ILP32F-NEXT: addi a2, a2, 7
+; RV32D-ILP32F-NEXT: andi a0, a2, -8
+; RV32D-ILP32F-NEXT: fld fa5, 0(a0)
+; RV32D-ILP32F-NEXT: addi a2, a2, 8
+; RV32D-ILP32F-NEXT: sw a2, 0(a1)
+; RV32D-ILP32F-NEXT: fsd fa5, 0(sp)
+; RV32D-ILP32F-NEXT: lw a0, 0(sp)
+; RV32D-ILP32F-NEXT: lw a1, 4(sp)
+; RV32D-ILP32F-NEXT: addi sp, sp, 48
+; RV32D-ILP32F-NEXT: ret
+;
+; RV32D-ILP32D-LABEL: va2:
+; RV32D-ILP32D: # %bb.0:
+; RV32D-ILP32D-NEXT: addi sp, sp, -48
+; RV32D-ILP32D-NEXT: addi a0, sp, 20
+; RV32D-ILP32D-NEXT: sw a1, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 24
+; RV32D-ILP32D-NEXT: sw a2, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 28
+; RV32D-ILP32D-NEXT: sw a3, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 32
+; RV32D-ILP32D-NEXT: sw a4, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 36
+; RV32D-ILP32D-NEXT: sw a5, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 40
+; RV32D-ILP32D-NEXT: addi a1, sp, 12
+; RV32D-ILP32D-NEXT: addi a2, sp, 20
+; RV32D-ILP32D-NEXT: srli a3, a1, 16
+; RV32D-ILP32D-NEXT: addi a4, a2, 2
+; RV32D-ILP32D-NEXT: lui a5, 16
+; RV32D-ILP32D-NEXT: addi a5, a5, -1
+; RV32D-ILP32D-NEXT: and a5, a1, a5
+; RV32D-ILP32D-NEXT: srli a5, a5, 8
+; RV32D-ILP32D-NEXT: sb a1, 0(a2)
+; RV32D-ILP32D-NEXT: addi a2, a2, 1
+; RV32D-ILP32D-NEXT: sb a5, 0(a2)
+; RV32D-ILP32D-NEXT: srli a2, a3, 8
+; RV32D-ILP32D-NEXT: addi a5, a4, 1
+; RV32D-ILP32D-NEXT: sb a3, 0(a4)
+; RV32D-ILP32D-NEXT: sb a2, 0(a5)
+; RV32D-ILP32D-NEXT: lw a2, 0(a1)
+; RV32D-ILP32D-NEXT: sw a6, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 44
+; RV32D-ILP32D-NEXT: sw a7, 0(a0)
+; RV32D-ILP32D-NEXT: addi a2, a2, 7
+; RV32D-ILP32D-NEXT: andi a0, a2, -8
+; RV32D-ILP32D-NEXT: fld fa5, 0(a0)
+; RV32D-ILP32D-NEXT: addi a2, a2, 8
+; RV32D-ILP32D-NEXT: sw a2, 0(a1)
+; RV32D-ILP32D-NEXT: fsd fa5, 0(sp)
+; RV32D-ILP32D-NEXT: lw a0, 0(sp)
+; RV32D-ILP32D-NEXT: lw a1, 4(sp)
+; RV32D-ILP32D-NEXT: addi sp, sp, 48
+; RV32D-ILP32D-NEXT: ret
+;
+; RV64-LABEL: va2:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -80
+; RV64-NEXT: addi a0, sp, 24
+; RV64-NEXT: sd a1, 0(a0)
+; RV64-NEXT: addi a0, sp, 32
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: addi a0, sp, 40
+; RV64-NEXT: sd a3, 0(a0)
+; RV64-NEXT: addi a0, sp, 48
+; RV64-NEXT: sd a4, 0(a0)
+; RV64-NEXT: addi a0, sp, 56
+; RV64-NEXT: sd a5, 0(a0)
+; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: sd a6, 0(a0)
+; RV64-NEXT: addi a0, sp, 72
+; RV64-NEXT: sd a7, 0(a0)
+; RV64-NEXT: addi a0, sp, 8
+; RV64-NEXT: addi a1, sp, 24
+; RV64-NEXT: srli a2, a0, 32
+; RV64-NEXT: addi a3, a1, 4
+; RV64-NEXT: srliw a4, a0, 16
+; RV64-NEXT: addi a5, a1, 2
+; RV64-NEXT: lui a6, 16
+; RV64-NEXT: addi a6, a6, -1
+; RV64-NEXT: and a7, a0, a6
+; RV64-NEXT: srliw a7, a7, 8
+; RV64-NEXT: addi t0, a1, 1
+; RV64-NEXT: sb a0, 0(a1)
+; RV64-NEXT: sb a7, 0(t0)
+; RV64-NEXT: srliw a1, a4, 8
+; RV64-NEXT: addi a7, a5, 1
+; RV64-NEXT: sb a4, 0(a5)
+; RV64-NEXT: sb a1, 0(a7)
+; RV64-NEXT: srliw a1, a2, 16
+; RV64-NEXT: addi a4, a3, 2
+; RV64-NEXT: and a5, a2, a6
+; RV64-NEXT: srliw a5, a5, 8
+; RV64-NEXT: addi a6, a3, 1
+; RV64-NEXT: sb a2, 0(a3)
+; RV64-NEXT: sb a5, 0(a6)
+; RV64-NEXT: srliw a2, a1, 8
+; RV64-NEXT: lw a3, 0(a0)
+; RV64-NEXT: addi a5, a4, 1
+; RV64-NEXT: sb a1, 0(a4)
+; RV64-NEXT: sb a2, 0(a5)
+; RV64-NEXT: addi a3, a3, 7
+; RV64-NEXT: andi a1, a3, -8
+; RV64-NEXT: slli a3, a3, 32
+; RV64-NEXT: srli a3, a3, 32
+; RV64-NEXT: addi a3, a3, 8
+; RV64-NEXT: srli a2, a3, 32
+; RV64-NEXT: addi a4, a0, 4
+; RV64-NEXT: sw a3, 0(a0)
+; RV64-NEXT: sw a2, 0(a4)
+; RV64-NEXT: slli a1, a1, 32
+; RV64-NEXT: srli a1, a1, 32
+; RV64-NEXT: ld a0, 0(a1)
+; RV64-NEXT: addi sp, sp, 80
+; RV64-NEXT: ret
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %argp.cur = load i32, ptr %va, align 4
+ %1 = add i32 %argp.cur, 7
+ %2 = and i32 %1, -8
+ %argp.cur.aligned = inttoptr i32 %1 to ptr
+ %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 8
+ store ptr %argp.next, ptr %va, align 4
+ %3 = inttoptr i32 %2 to ptr
+ %4 = load double, ptr %3, align 8
+ %5 = bitcast double %4 to i64
+ call void @llvm.va_end(ptr %va)
+ ret i64 %5
+}
+
+define i64 @va2_va_arg(ptr %fmt, ...) nounwind {
+; ILP32-LABEL: va2_va_arg:
+; ILP32: # %bb.0:
+; ILP32-NEXT: addi sp, sp, -48
+; ILP32-NEXT: addi a0, sp, 20
+; ILP32-NEXT: sw a1, 0(a0)
+; ILP32-NEXT: addi a0, sp, 24
+; ILP32-NEXT: sw a2, 0(a0)
+; ILP32-NEXT: addi a0, sp, 28
+; ILP32-NEXT: sw a3, 0(a0)
+; ILP32-NEXT: addi a0, sp, 32
+; ILP32-NEXT: sw a4, 0(a0)
+; ILP32-NEXT: addi a0, sp, 36
+; ILP32-NEXT: sw a5, 0(a0)
+; ILP32-NEXT: addi a0, sp, 40
+; ILP32-NEXT: sw a6, 0(a0)
+; ILP32-NEXT: addi a0, sp, 44
+; ILP32-NEXT: sw a7, 0(a0)
+; ILP32-NEXT: addi a0, sp, 12
+; ILP32-NEXT: addi a1, sp, 20
+; ILP32-NEXT: srli a2, a0, 16
+; ILP32-NEXT: addi a3, a1, 2
+; ILP32-NEXT: lui a4, 16
+; ILP32-NEXT: addi a4, a4, -1
+; ILP32-NEXT: and a4, a0, a4
+; ILP32-NEXT: srli a4, a4, 8
+; ILP32-NEXT: addi a5, a1, 1
+; ILP32-NEXT: sb a0, 0(a1)
+; ILP32-NEXT: sb a4, 0(a5)
+; ILP32-NEXT: srli a1, a2, 8
+; ILP32-NEXT: addi a4, a3, 1
+; ILP32-NEXT: sb a2, 0(a3)
+; ILP32-NEXT: sb a1, 0(a4)
+; ILP32-NEXT: lw a1, 0(a0)
+; ILP32-NEXT: addi a1, a1, 7
+; ILP32-NEXT: andi a1, a1, -8
+; ILP32-NEXT: addi a2, a1, 8
+; ILP32-NEXT: sw a2, 0(a0)
+; ILP32-NEXT: lw a0, 0(a1)
+; ILP32-NEXT: addi a1, a1, 4
+; ILP32-NEXT: lw a1, 0(a1)
+; ILP32-NEXT: addi sp, sp, 48
+; ILP32-NEXT: ret
+;
+; RV32D-ILP32-LABEL: va2_va_arg:
+; RV32D-ILP32: # %bb.0:
+; RV32D-ILP32-NEXT: addi sp, sp, -48
+; RV32D-ILP32-NEXT: addi a0, sp, 20
+; RV32D-ILP32-NEXT: sw a1, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 24
+; RV32D-ILP32-NEXT: sw a2, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 28
+; RV32D-ILP32-NEXT: sw a3, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 32
+; RV32D-ILP32-NEXT: sw a4, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 36
+; RV32D-ILP32-NEXT: sw a5, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 40
+; RV32D-ILP32-NEXT: sw a6, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 44
+; RV32D-ILP32-NEXT: sw a7, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 12
+; RV32D-ILP32-NEXT: addi a1, sp, 20
+; RV32D-ILP32-NEXT: srli a2, a0, 16
+; RV32D-ILP32-NEXT: addi a3, a1, 2
+; RV32D-ILP32-NEXT: lui a4, 16
+; RV32D-ILP32-NEXT: addi a4, a4, -1
+; RV32D-ILP32-NEXT: and a4, a0, a4
+; RV32D-ILP32-NEXT: srli a4, a4, 8
+; RV32D-ILP32-NEXT: addi a5, a1, 1
+; RV32D-ILP32-NEXT: sb a0, 0(a1)
+; RV32D-ILP32-NEXT: sb a4, 0(a5)
+; RV32D-ILP32-NEXT: srli a1, a2, 8
+; RV32D-ILP32-NEXT: addi a4, a3, 1
+; RV32D-ILP32-NEXT: sb a2, 0(a3)
+; RV32D-ILP32-NEXT: sb a1, 0(a4)
+; RV32D-ILP32-NEXT: lw a1, 0(a0)
+; RV32D-ILP32-NEXT: addi a1, a1, 7
+; RV32D-ILP32-NEXT: andi a1, a1, -8
+; RV32D-ILP32-NEXT: addi a2, a1, 8
+; RV32D-ILP32-NEXT: sw a2, 0(a0)
+; RV32D-ILP32-NEXT: fld fa5, 0(a1)
+; RV32D-ILP32-NEXT: fsd fa5, 0(sp)
+; RV32D-ILP32-NEXT: lw a0, 0(sp)
+; RV32D-ILP32-NEXT: lw a1, 4(sp)
+; RV32D-ILP32-NEXT: addi sp, sp, 48
+; RV32D-ILP32-NEXT: ret
+;
+; RV32D-ILP32F-LABEL: va2_va_arg:
+; RV32D-ILP32F: # %bb.0:
+; RV32D-ILP32F-NEXT: addi sp, sp, -48
+; RV32D-ILP32F-NEXT: addi a0, sp, 20
+; RV32D-ILP32F-NEXT: sw a1, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 24
+; RV32D-ILP32F-NEXT: sw a2, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 28
+; RV32D-ILP32F-NEXT: sw a3, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 32
+; RV32D-ILP32F-NEXT: sw a4, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 36
+; RV32D-ILP32F-NEXT: sw a5, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 40
+; RV32D-ILP32F-NEXT: sw a6, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 44
+; RV32D-ILP32F-NEXT: sw a7, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 12
+; RV32D-ILP32F-NEXT: addi a1, sp, 20
+; RV32D-ILP32F-NEXT: srli a2, a0, 16
+; RV32D-ILP32F-NEXT: addi a3, a1, 2
+; RV32D-ILP32F-NEXT: lui a4, 16
+; RV32D-ILP32F-NEXT: addi a4, a4, -1
+; RV32D-ILP32F-NEXT: and a4, a0, a4
+; RV32D-ILP32F-NEXT: srli a4, a4, 8
+; RV32D-ILP32F-NEXT: addi a5, a1, 1
+; RV32D-ILP32F-NEXT: sb a0, 0(a1)
+; RV32D-ILP32F-NEXT: sb a4, 0(a5)
+; RV32D-ILP32F-NEXT: srli a1, a2, 8
+; RV32D-ILP32F-NEXT: addi a4, a3, 1
+; RV32D-ILP32F-NEXT: sb a2, 0(a3)
+; RV32D-ILP32F-NEXT: sb a1, 0(a4)
+; RV32D-ILP32F-NEXT: lw a1, 0(a0)
+; RV32D-ILP32F-NEXT: addi a1, a1, 7
+; RV32D-ILP32F-NEXT: andi a1, a1, -8
+; RV32D-ILP32F-NEXT: addi a2, a1, 8
+; RV32D-ILP32F-NEXT: sw a2, 0(a0)
+; RV32D-ILP32F-NEXT: fld fa5, 0(a1)
+; RV32D-ILP32F-NEXT: fsd fa5, 0(sp)
+; RV32D-ILP32F-NEXT: lw a0, 0(sp)
+; RV32D-ILP32F-NEXT: lw a1, 4(sp)
+; RV32D-ILP32F-NEXT: addi sp, sp, 48
+; RV32D-ILP32F-NEXT: ret
+;
+; RV32D-ILP32D-LABEL: va2_va_arg:
+; RV32D-ILP32D: # %bb.0:
+; RV32D-ILP32D-NEXT: addi sp, sp, -48
+; RV32D-ILP32D-NEXT: addi a0, sp, 20
+; RV32D-ILP32D-NEXT: sw a1, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 24
+; RV32D-ILP32D-NEXT: sw a2, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 28
+; RV32D-ILP32D-NEXT: sw a3, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 32
+; RV32D-ILP32D-NEXT: sw a4, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 36
+; RV32D-ILP32D-NEXT: sw a5, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 40
+; RV32D-ILP32D-NEXT: sw a6, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 44
+; RV32D-ILP32D-NEXT: sw a7, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 12
+; RV32D-ILP32D-NEXT: addi a1, sp, 20
+; RV32D-ILP32D-NEXT: srli a2, a0, 16
+; RV32D-ILP32D-NEXT: addi a3, a1, 2
+; RV32D-ILP32D-NEXT: lui a4, 16
+; RV32D-ILP32D-NEXT: addi a4, a4, -1
+; RV32D-ILP32D-NEXT: and a4, a0, a4
+; RV32D-ILP32D-NEXT: srli a4, a4, 8
+; RV32D-ILP32D-NEXT: addi a5, a1, 1
+; RV32D-ILP32D-NEXT: sb a0, 0(a1)
+; RV32D-ILP32D-NEXT: sb a4, 0(a5)
+; RV32D-ILP32D-NEXT: srli a1, a2, 8
+; RV32D-ILP32D-NEXT: addi a4, a3, 1
+; RV32D-ILP32D-NEXT: sb a2, 0(a3)
+; RV32D-ILP32D-NEXT: sb a1, 0(a4)
+; RV32D-ILP32D-NEXT: lw a1, 0(a0)
+; RV32D-ILP32D-NEXT: addi a1, a1, 7
+; RV32D-ILP32D-NEXT: andi a1, a1, -8
+; RV32D-ILP32D-NEXT: addi a2, a1, 8
+; RV32D-ILP32D-NEXT: sw a2, 0(a0)
+; RV32D-ILP32D-NEXT: fld fa5, 0(a1)
+; RV32D-ILP32D-NEXT: fsd fa5, 0(sp)
+; RV32D-ILP32D-NEXT: lw a0, 0(sp)
+; RV32D-ILP32D-NEXT: lw a1, 4(sp)
+; RV32D-ILP32D-NEXT: addi sp, sp, 48
+; RV32D-ILP32D-NEXT: ret
+;
+; RV64-LABEL: va2_va_arg:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -80
+; RV64-NEXT: addi a0, sp, 24
+; RV64-NEXT: sd a1, 0(a0)
+; RV64-NEXT: addi a0, sp, 32
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: addi a0, sp, 40
+; RV64-NEXT: sd a3, 0(a0)
+; RV64-NEXT: addi a0, sp, 48
+; RV64-NEXT: sd a4, 0(a0)
+; RV64-NEXT: addi a0, sp, 56
+; RV64-NEXT: sd a5, 0(a0)
+; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: sd a6, 0(a0)
+; RV64-NEXT: addi a0, sp, 72
+; RV64-NEXT: sd a7, 0(a0)
+; RV64-NEXT: addi a0, sp, 8
+; RV64-NEXT: addi a1, sp, 24
+; RV64-NEXT: srli a2, a0, 32
+; RV64-NEXT: addi a3, a1, 4
+; RV64-NEXT: srliw a4, a0, 16
+; RV64-NEXT: addi a5, a1, 2
+; RV64-NEXT: lui a6, 16
+; RV64-NEXT: addi a6, a6, -1
+; RV64-NEXT: and a7, a0, a6
+; RV64-NEXT: srliw a7, a7, 8
+; RV64-NEXT: addi t0, a1, 1
+; RV64-NEXT: sb a0, 0(a1)
+; RV64-NEXT: sb a7, 0(t0)
+; RV64-NEXT: srliw a1, a4, 8
+; RV64-NEXT: addi a7, a5, 1
+; RV64-NEXT: sb a4, 0(a5)
+; RV64-NEXT: sb a1, 0(a7)
+; RV64-NEXT: srliw a1, a2, 16
+; RV64-NEXT: addi a4, a3, 2
+; RV64-NEXT: and a5, a2, a6
+; RV64-NEXT: srliw a5, a5, 8
+; RV64-NEXT: addi a6, a3, 1
+; RV64-NEXT: sb a2, 0(a3)
+; RV64-NEXT: sb a5, 0(a6)
+; RV64-NEXT: srliw a2, a1, 8
+; RV64-NEXT: addi a3, a4, 1
+; RV64-NEXT: sb a1, 0(a4)
+; RV64-NEXT: sb a2, 0(a3)
+; RV64-NEXT: ld a1, 0(a0)
+; RV64-NEXT: addi a1, a1, 7
+; RV64-NEXT: andi a1, a1, -8
+; RV64-NEXT: addi a2, a1, 8
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: ld a0, 0(a1)
+; RV64-NEXT: addi sp, sp, 80
+; RV64-NEXT: ret
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %1 = va_arg ptr %va, double
+ call void @llvm.va_end(ptr %va)
+ %2 = bitcast double %1 to i64
+ ret i64 %2
+}
+
+define void @va2_caller() nounwind {
+; RV32-LABEL: va2_caller:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: li a1, 1
+; RV32-NEXT: call va2 at plt
+; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: va2_caller:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -16
+; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT: li a1, 1
+; RV64-NEXT: call va2 at plt
+; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT: addi sp, sp, 16
+; RV64-NEXT: ret
+ %1 = call i64 (ptr, ...) @va2(ptr undef, i32 1)
+ ret void
+}
+
+; On RV32, Ensure a named 2*xlen argument is passed in a1 and a2, while the
+; vararg double is passed in a4 and a5 (rather than a3 and a4)
+
+define i64 @va3(i32 %a, i64 %b, ...) nounwind {
+; ILP32-LABEL: va3:
+; ILP32: # %bb.0:
+; ILP32-NEXT: addi sp, sp, -32
+; ILP32-NEXT: addi a0, sp, 12
+; ILP32-NEXT: sw a3, 0(a0)
+; ILP32-NEXT: addi a0, sp, 16
+; ILP32-NEXT: sw a4, 0(a0)
+; ILP32-NEXT: addi a0, sp, 20
+; ILP32-NEXT: sw a5, 0(a0)
+; ILP32-NEXT: addi a0, sp, 4
+; ILP32-NEXT: addi a3, sp, 12
+; ILP32-NEXT: lui a4, 16
+; ILP32-NEXT: addi a4, a4, -1
+; ILP32-NEXT: and a4, a0, a4
+; ILP32-NEXT: srli a4, a4, 8
+; ILP32-NEXT: addi a5, a3, 1
+; ILP32-NEXT: sb a4, 0(a5)
+; ILP32-NEXT: addi a4, sp, 24
+; ILP32-NEXT: srli a5, a0, 16
+; ILP32-NEXT: sb a0, 0(a3)
+; ILP32-NEXT: addi a3, a3, 2
+; ILP32-NEXT: sb a5, 0(a3)
+; ILP32-NEXT: srli a5, a5, 8
+; ILP32-NEXT: addi a3, a3, 1
+; ILP32-NEXT: sb a5, 0(a3)
+; ILP32-NEXT: lw a3, 0(a0)
+; ILP32-NEXT: sw a6, 0(a4)
+; ILP32-NEXT: addi a4, sp, 28
+; ILP32-NEXT: sw a7, 0(a4)
+; ILP32-NEXT: addi a3, a3, 7
+; ILP32-NEXT: andi a4, a3, -8
+; ILP32-NEXT: addi a3, a3, 8
+; ILP32-NEXT: sw a3, 0(a0)
+; ILP32-NEXT: lw a3, 0(a4)
+; ILP32-NEXT: addi a4, a4, 4
+; ILP32-NEXT: lw a4, 0(a4)
+; ILP32-NEXT: add a0, a1, a3
+; ILP32-NEXT: sltu a1, a0, a3
+; ILP32-NEXT: add a2, a2, a4
+; ILP32-NEXT: add a1, a2, a1
+; ILP32-NEXT: addi sp, sp, 32
+; ILP32-NEXT: ret
+;
+; RV32D-ILP32-LABEL: va3:
+; RV32D-ILP32: # %bb.0:
+; RV32D-ILP32-NEXT: addi sp, sp, -48
+; RV32D-ILP32-NEXT: addi a0, sp, 28
+; RV32D-ILP32-NEXT: sw a3, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 32
+; RV32D-ILP32-NEXT: sw a4, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 36
+; RV32D-ILP32-NEXT: sw a5, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 20
+; RV32D-ILP32-NEXT: addi a3, sp, 28
+; RV32D-ILP32-NEXT: lui a4, 16
+; RV32D-ILP32-NEXT: addi a4, a4, -1
+; RV32D-ILP32-NEXT: and a4, a0, a4
+; RV32D-ILP32-NEXT: srli a4, a4, 8
+; RV32D-ILP32-NEXT: addi a5, a3, 1
+; RV32D-ILP32-NEXT: sb a4, 0(a5)
+; RV32D-ILP32-NEXT: addi a4, sp, 40
+; RV32D-ILP32-NEXT: srli a5, a0, 16
+; RV32D-ILP32-NEXT: sb a0, 0(a3)
+; RV32D-ILP32-NEXT: addi a3, a3, 2
+; RV32D-ILP32-NEXT: sb a5, 0(a3)
+; RV32D-ILP32-NEXT: srli a5, a5, 8
+; RV32D-ILP32-NEXT: addi a3, a3, 1
+; RV32D-ILP32-NEXT: sb a5, 0(a3)
+; RV32D-ILP32-NEXT: lw a3, 0(a0)
+; RV32D-ILP32-NEXT: sw a6, 0(a4)
+; RV32D-ILP32-NEXT: addi a4, sp, 44
+; RV32D-ILP32-NEXT: sw a7, 0(a4)
+; RV32D-ILP32-NEXT: addi a3, a3, 7
+; RV32D-ILP32-NEXT: andi a4, a3, -8
+; RV32D-ILP32-NEXT: fld fa5, 0(a4)
+; RV32D-ILP32-NEXT: addi a3, a3, 8
+; RV32D-ILP32-NEXT: sw a3, 0(a0)
+; RV32D-ILP32-NEXT: fsd fa5, 8(sp)
+; RV32D-ILP32-NEXT: lw a3, 8(sp)
+; RV32D-ILP32-NEXT: lw a4, 12(sp)
+; RV32D-ILP32-NEXT: add a0, a1, a3
+; RV32D-ILP32-NEXT: sltu a1, a0, a3
+; RV32D-ILP32-NEXT: add a2, a2, a4
+; RV32D-ILP32-NEXT: add a1, a2, a1
+; RV32D-ILP32-NEXT: addi sp, sp, 48
+; RV32D-ILP32-NEXT: ret
+;
+; RV32D-ILP32F-LABEL: va3:
+; RV32D-ILP32F: # %bb.0:
+; RV32D-ILP32F-NEXT: addi sp, sp, -48
+; RV32D-ILP32F-NEXT: addi a0, sp, 28
+; RV32D-ILP32F-NEXT: sw a3, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 32
+; RV32D-ILP32F-NEXT: sw a4, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 36
+; RV32D-ILP32F-NEXT: sw a5, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 20
+; RV32D-ILP32F-NEXT: addi a3, sp, 28
+; RV32D-ILP32F-NEXT: lui a4, 16
+; RV32D-ILP32F-NEXT: addi a4, a4, -1
+; RV32D-ILP32F-NEXT: and a4, a0, a4
+; RV32D-ILP32F-NEXT: srli a4, a4, 8
+; RV32D-ILP32F-NEXT: addi a5, a3, 1
+; RV32D-ILP32F-NEXT: sb a4, 0(a5)
+; RV32D-ILP32F-NEXT: addi a4, sp, 40
+; RV32D-ILP32F-NEXT: srli a5, a0, 16
+; RV32D-ILP32F-NEXT: sb a0, 0(a3)
+; RV32D-ILP32F-NEXT: addi a3, a3, 2
+; RV32D-ILP32F-NEXT: sb a5, 0(a3)
+; RV32D-ILP32F-NEXT: srli a5, a5, 8
+; RV32D-ILP32F-NEXT: addi a3, a3, 1
+; RV32D-ILP32F-NEXT: sb a5, 0(a3)
+; RV32D-ILP32F-NEXT: lw a3, 0(a0)
+; RV32D-ILP32F-NEXT: sw a6, 0(a4)
+; RV32D-ILP32F-NEXT: addi a4, sp, 44
+; RV32D-ILP32F-NEXT: sw a7, 0(a4)
+; RV32D-ILP32F-NEXT: addi a3, a3, 7
+; RV32D-ILP32F-NEXT: andi a4, a3, -8
+; RV32D-ILP32F-NEXT: fld fa5, 0(a4)
+; RV32D-ILP32F-NEXT: addi a3, a3, 8
+; RV32D-ILP32F-NEXT: sw a3, 0(a0)
+; RV32D-ILP32F-NEXT: fsd fa5, 8(sp)
+; RV32D-ILP32F-NEXT: lw a3, 8(sp)
+; RV32D-ILP32F-NEXT: lw a4, 12(sp)
+; RV32D-ILP32F-NEXT: add a0, a1, a3
+; RV32D-ILP32F-NEXT: sltu a1, a0, a3
+; RV32D-ILP32F-NEXT: add a2, a2, a4
+; RV32D-ILP32F-NEXT: add a1, a2, a1
+; RV32D-ILP32F-NEXT: addi sp, sp, 48
+; RV32D-ILP32F-NEXT: ret
+;
+; RV32D-ILP32D-LABEL: va3:
+; RV32D-ILP32D: # %bb.0:
+; RV32D-ILP32D-NEXT: addi sp, sp, -48
+; RV32D-ILP32D-NEXT: addi a0, sp, 28
+; RV32D-ILP32D-NEXT: sw a3, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 32
+; RV32D-ILP32D-NEXT: sw a4, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 36
+; RV32D-ILP32D-NEXT: sw a5, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 20
+; RV32D-ILP32D-NEXT: addi a3, sp, 28
+; RV32D-ILP32D-NEXT: lui a4, 16
+; RV32D-ILP32D-NEXT: addi a4, a4, -1
+; RV32D-ILP32D-NEXT: and a4, a0, a4
+; RV32D-ILP32D-NEXT: srli a4, a4, 8
+; RV32D-ILP32D-NEXT: addi a5, a3, 1
+; RV32D-ILP32D-NEXT: sb a4, 0(a5)
+; RV32D-ILP32D-NEXT: addi a4, sp, 40
+; RV32D-ILP32D-NEXT: srli a5, a0, 16
+; RV32D-ILP32D-NEXT: sb a0, 0(a3)
+; RV32D-ILP32D-NEXT: addi a3, a3, 2
+; RV32D-ILP32D-NEXT: sb a5, 0(a3)
+; RV32D-ILP32D-NEXT: srli a5, a5, 8
+; RV32D-ILP32D-NEXT: addi a3, a3, 1
+; RV32D-ILP32D-NEXT: sb a5, 0(a3)
+; RV32D-ILP32D-NEXT: lw a3, 0(a0)
+; RV32D-ILP32D-NEXT: sw a6, 0(a4)
+; RV32D-ILP32D-NEXT: addi a4, sp, 44
+; RV32D-ILP32D-NEXT: sw a7, 0(a4)
+; RV32D-ILP32D-NEXT: addi a3, a3, 7
+; RV32D-ILP32D-NEXT: andi a4, a3, -8
+; RV32D-ILP32D-NEXT: fld fa5, 0(a4)
+; RV32D-ILP32D-NEXT: addi a3, a3, 8
+; RV32D-ILP32D-NEXT: sw a3, 0(a0)
+; RV32D-ILP32D-NEXT: fsd fa5, 8(sp)
+; RV32D-ILP32D-NEXT: lw a3, 8(sp)
+; RV32D-ILP32D-NEXT: lw a4, 12(sp)
+; RV32D-ILP32D-NEXT: add a0, a1, a3
+; RV32D-ILP32D-NEXT: sltu a1, a0, a3
+; RV32D-ILP32D-NEXT: add a2, a2, a4
+; RV32D-ILP32D-NEXT: add a1, a2, a1
+; RV32D-ILP32D-NEXT: addi sp, sp, 48
+; RV32D-ILP32D-NEXT: ret
+;
+; RV64-LABEL: va3:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -64
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: addi a0, sp, 24
+; RV64-NEXT: sd a3, 0(a0)
+; RV64-NEXT: addi a0, sp, 32
+; RV64-NEXT: sd a4, 0(a0)
+; RV64-NEXT: addi a0, sp, 40
+; RV64-NEXT: sd a5, 0(a0)
+; RV64-NEXT: addi a0, sp, 48
+; RV64-NEXT: sd a6, 0(a0)
+; RV64-NEXT: addi a0, sp, 56
+; RV64-NEXT: sd a7, 0(a0)
+; RV64-NEXT: addi a0, sp, 8
+; RV64-NEXT: addi a2, sp, 16
+; RV64-NEXT: srli a3, a0, 32
+; RV64-NEXT: addi a4, a2, 4
+; RV64-NEXT: srliw a5, a0, 16
+; RV64-NEXT: addi a6, a2, 2
+; RV64-NEXT: lui a7, 16
+; RV64-NEXT: addi a7, a7, -1
+; RV64-NEXT: and t0, a0, a7
+; RV64-NEXT: srliw t0, t0, 8
+; RV64-NEXT: addi t1, a2, 1
+; RV64-NEXT: sb a0, 0(a2)
+; RV64-NEXT: sb t0, 0(t1)
+; RV64-NEXT: srliw a2, a5, 8
+; RV64-NEXT: addi t0, a6, 1
+; RV64-NEXT: sb a5, 0(a6)
+; RV64-NEXT: sb a2, 0(t0)
+; RV64-NEXT: srliw a2, a3, 16
+; RV64-NEXT: addi a5, a4, 2
+; RV64-NEXT: and a6, a3, a7
+; RV64-NEXT: srliw a6, a6, 8
+; RV64-NEXT: addi a7, a4, 1
+; RV64-NEXT: sb a3, 0(a4)
+; RV64-NEXT: sb a6, 0(a7)
+; RV64-NEXT: srliw a3, a2, 8
+; RV64-NEXT: lw a4, 0(a0)
+; RV64-NEXT: addi a6, a5, 1
+; RV64-NEXT: sb a2, 0(a5)
+; RV64-NEXT: sb a3, 0(a6)
+; RV64-NEXT: addi a4, a4, 7
+; RV64-NEXT: andi a2, a4, -8
+; RV64-NEXT: slli a4, a4, 32
+; RV64-NEXT: srli a4, a4, 32
+; RV64-NEXT: addi a4, a4, 8
+; RV64-NEXT: srli a3, a4, 32
+; RV64-NEXT: addi a5, a0, 4
+; RV64-NEXT: sw a4, 0(a0)
+; RV64-NEXT: sw a3, 0(a5)
+; RV64-NEXT: slli a2, a2, 32
+; RV64-NEXT: srli a2, a2, 32
+; RV64-NEXT: ld a0, 0(a2)
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: addi sp, sp, 64
+; RV64-NEXT: ret
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %argp.cur = load i32, ptr %va, align 4
+ %1 = add i32 %argp.cur, 7
+ %2 = and i32 %1, -8
+ %argp.cur.aligned = inttoptr i32 %1 to ptr
+ %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 8
+ store ptr %argp.next, ptr %va, align 4
+ %3 = inttoptr i32 %2 to ptr
+ %4 = load double, ptr %3, align 8
+ call void @llvm.va_end(ptr %va)
+ %5 = bitcast double %4 to i64
+ %6 = add i64 %b, %5
+ ret i64 %6
+}
+
+define i64 @va3_va_arg(i32 %a, i64 %b, ...) nounwind {
+; ILP32-LABEL: va3_va_arg:
+; ILP32: # %bb.0:
+; ILP32-NEXT: addi sp, sp, -32
+; ILP32-NEXT: addi a0, sp, 12
+; ILP32-NEXT: sw a3, 0(a0)
+; ILP32-NEXT: addi a0, sp, 16
+; ILP32-NEXT: sw a4, 0(a0)
+; ILP32-NEXT: addi a0, sp, 20
+; ILP32-NEXT: sw a5, 0(a0)
+; ILP32-NEXT: addi a0, sp, 24
+; ILP32-NEXT: sw a6, 0(a0)
+; ILP32-NEXT: addi a0, sp, 28
+; ILP32-NEXT: sw a7, 0(a0)
+; ILP32-NEXT: addi a0, sp, 4
+; ILP32-NEXT: addi a3, sp, 12
+; ILP32-NEXT: srli a4, a0, 16
+; ILP32-NEXT: addi a5, a3, 2
+; ILP32-NEXT: lui a6, 16
+; ILP32-NEXT: addi a6, a6, -1
+; ILP32-NEXT: and a6, a0, a6
+; ILP32-NEXT: srli a6, a6, 8
+; ILP32-NEXT: addi a7, a3, 1
+; ILP32-NEXT: sb a0, 0(a3)
+; ILP32-NEXT: sb a6, 0(a7)
+; ILP32-NEXT: srli a3, a4, 8
+; ILP32-NEXT: addi a6, a5, 1
+; ILP32-NEXT: sb a4, 0(a5)
+; ILP32-NEXT: sb a3, 0(a6)
+; ILP32-NEXT: lw a3, 0(a0)
+; ILP32-NEXT: addi a3, a3, 7
+; ILP32-NEXT: andi a3, a3, -8
+; ILP32-NEXT: addi a4, a3, 8
+; ILP32-NEXT: sw a4, 0(a0)
+; ILP32-NEXT: lw a4, 0(a3)
+; ILP32-NEXT: addi a3, a3, 4
+; ILP32-NEXT: lw a3, 0(a3)
+; ILP32-NEXT: add a0, a1, a4
+; ILP32-NEXT: sltu a1, a0, a4
+; ILP32-NEXT: add a2, a2, a3
+; ILP32-NEXT: add a1, a2, a1
+; ILP32-NEXT: addi sp, sp, 32
+; ILP32-NEXT: ret
+;
+; RV32D-ILP32-LABEL: va3_va_arg:
+; RV32D-ILP32: # %bb.0:
+; RV32D-ILP32-NEXT: addi sp, sp, -48
+; RV32D-ILP32-NEXT: addi a0, sp, 28
+; RV32D-ILP32-NEXT: sw a3, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 32
+; RV32D-ILP32-NEXT: sw a4, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 36
+; RV32D-ILP32-NEXT: sw a5, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 40
+; RV32D-ILP32-NEXT: sw a6, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 44
+; RV32D-ILP32-NEXT: sw a7, 0(a0)
+; RV32D-ILP32-NEXT: addi a0, sp, 20
+; RV32D-ILP32-NEXT: addi a3, sp, 28
+; RV32D-ILP32-NEXT: srli a4, a0, 16
+; RV32D-ILP32-NEXT: addi a5, a3, 2
+; RV32D-ILP32-NEXT: lui a6, 16
+; RV32D-ILP32-NEXT: addi a6, a6, -1
+; RV32D-ILP32-NEXT: and a6, a0, a6
+; RV32D-ILP32-NEXT: srli a6, a6, 8
+; RV32D-ILP32-NEXT: addi a7, a3, 1
+; RV32D-ILP32-NEXT: sb a0, 0(a3)
+; RV32D-ILP32-NEXT: sb a6, 0(a7)
+; RV32D-ILP32-NEXT: srli a3, a4, 8
+; RV32D-ILP32-NEXT: addi a6, a5, 1
+; RV32D-ILP32-NEXT: sb a4, 0(a5)
+; RV32D-ILP32-NEXT: sb a3, 0(a6)
+; RV32D-ILP32-NEXT: lw a3, 0(a0)
+; RV32D-ILP32-NEXT: addi a3, a3, 7
+; RV32D-ILP32-NEXT: andi a3, a3, -8
+; RV32D-ILP32-NEXT: addi a4, a3, 8
+; RV32D-ILP32-NEXT: sw a4, 0(a0)
+; RV32D-ILP32-NEXT: fld fa5, 0(a3)
+; RV32D-ILP32-NEXT: fsd fa5, 8(sp)
+; RV32D-ILP32-NEXT: lw a3, 8(sp)
+; RV32D-ILP32-NEXT: lw a4, 12(sp)
+; RV32D-ILP32-NEXT: add a0, a1, a3
+; RV32D-ILP32-NEXT: sltu a1, a0, a3
+; RV32D-ILP32-NEXT: add a2, a2, a4
+; RV32D-ILP32-NEXT: add a1, a2, a1
+; RV32D-ILP32-NEXT: addi sp, sp, 48
+; RV32D-ILP32-NEXT: ret
+;
+; RV32D-ILP32F-LABEL: va3_va_arg:
+; RV32D-ILP32F: # %bb.0:
+; RV32D-ILP32F-NEXT: addi sp, sp, -48
+; RV32D-ILP32F-NEXT: addi a0, sp, 28
+; RV32D-ILP32F-NEXT: sw a3, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 32
+; RV32D-ILP32F-NEXT: sw a4, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 36
+; RV32D-ILP32F-NEXT: sw a5, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 40
+; RV32D-ILP32F-NEXT: sw a6, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 44
+; RV32D-ILP32F-NEXT: sw a7, 0(a0)
+; RV32D-ILP32F-NEXT: addi a0, sp, 20
+; RV32D-ILP32F-NEXT: addi a3, sp, 28
+; RV32D-ILP32F-NEXT: srli a4, a0, 16
+; RV32D-ILP32F-NEXT: addi a5, a3, 2
+; RV32D-ILP32F-NEXT: lui a6, 16
+; RV32D-ILP32F-NEXT: addi a6, a6, -1
+; RV32D-ILP32F-NEXT: and a6, a0, a6
+; RV32D-ILP32F-NEXT: srli a6, a6, 8
+; RV32D-ILP32F-NEXT: addi a7, a3, 1
+; RV32D-ILP32F-NEXT: sb a0, 0(a3)
+; RV32D-ILP32F-NEXT: sb a6, 0(a7)
+; RV32D-ILP32F-NEXT: srli a3, a4, 8
+; RV32D-ILP32F-NEXT: addi a6, a5, 1
+; RV32D-ILP32F-NEXT: sb a4, 0(a5)
+; RV32D-ILP32F-NEXT: sb a3, 0(a6)
+; RV32D-ILP32F-NEXT: lw a3, 0(a0)
+; RV32D-ILP32F-NEXT: addi a3, a3, 7
+; RV32D-ILP32F-NEXT: andi a3, a3, -8
+; RV32D-ILP32F-NEXT: addi a4, a3, 8
+; RV32D-ILP32F-NEXT: sw a4, 0(a0)
+; RV32D-ILP32F-NEXT: fld fa5, 0(a3)
+; RV32D-ILP32F-NEXT: fsd fa5, 8(sp)
+; RV32D-ILP32F-NEXT: lw a3, 8(sp)
+; RV32D-ILP32F-NEXT: lw a4, 12(sp)
+; RV32D-ILP32F-NEXT: add a0, a1, a3
+; RV32D-ILP32F-NEXT: sltu a1, a0, a3
+; RV32D-ILP32F-NEXT: add a2, a2, a4
+; RV32D-ILP32F-NEXT: add a1, a2, a1
+; RV32D-ILP32F-NEXT: addi sp, sp, 48
+; RV32D-ILP32F-NEXT: ret
+;
+; RV32D-ILP32D-LABEL: va3_va_arg:
+; RV32D-ILP32D: # %bb.0:
+; RV32D-ILP32D-NEXT: addi sp, sp, -48
+; RV32D-ILP32D-NEXT: addi a0, sp, 28
+; RV32D-ILP32D-NEXT: sw a3, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 32
+; RV32D-ILP32D-NEXT: sw a4, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 36
+; RV32D-ILP32D-NEXT: sw a5, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 40
+; RV32D-ILP32D-NEXT: sw a6, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 44
+; RV32D-ILP32D-NEXT: sw a7, 0(a0)
+; RV32D-ILP32D-NEXT: addi a0, sp, 20
+; RV32D-ILP32D-NEXT: addi a3, sp, 28
+; RV32D-ILP32D-NEXT: srli a4, a0, 16
+; RV32D-ILP32D-NEXT: addi a5, a3, 2
+; RV32D-ILP32D-NEXT: lui a6, 16
+; RV32D-ILP32D-NEXT: addi a6, a6, -1
+; RV32D-ILP32D-NEXT: and a6, a0, a6
+; RV32D-ILP32D-NEXT: srli a6, a6, 8
+; RV32D-ILP32D-NEXT: addi a7, a3, 1
+; RV32D-ILP32D-NEXT: sb a0, 0(a3)
+; RV32D-ILP32D-NEXT: sb a6, 0(a7)
+; RV32D-ILP32D-NEXT: srli a3, a4, 8
+; RV32D-ILP32D-NEXT: addi a6, a5, 1
+; RV32D-ILP32D-NEXT: sb a4, 0(a5)
+; RV32D-ILP32D-NEXT: sb a3, 0(a6)
+; RV32D-ILP32D-NEXT: lw a3, 0(a0)
+; RV32D-ILP32D-NEXT: addi a3, a3, 7
+; RV32D-ILP32D-NEXT: andi a3, a3, -8
+; RV32D-ILP32D-NEXT: addi a4, a3, 8
+; RV32D-ILP32D-NEXT: sw a4, 0(a0)
+; RV32D-ILP32D-NEXT: fld fa5, 0(a3)
+; RV32D-ILP32D-NEXT: fsd fa5, 8(sp)
+; RV32D-ILP32D-NEXT: lw a3, 8(sp)
+; RV32D-ILP32D-NEXT: lw a4, 12(sp)
+; RV32D-ILP32D-NEXT: add a0, a1, a3
+; RV32D-ILP32D-NEXT: sltu a1, a0, a3
+; RV32D-ILP32D-NEXT: add a2, a2, a4
+; RV32D-ILP32D-NEXT: add a1, a2, a1
+; RV32D-ILP32D-NEXT: addi sp, sp, 48
+; RV32D-ILP32D-NEXT: ret
+;
+; RV64-LABEL: va3_va_arg:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -64
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: addi a0, sp, 24
+; RV64-NEXT: sd a3, 0(a0)
+; RV64-NEXT: addi a0, sp, 32
+; RV64-NEXT: sd a4, 0(a0)
+; RV64-NEXT: addi a0, sp, 40
+; RV64-NEXT: sd a5, 0(a0)
+; RV64-NEXT: addi a0, sp, 48
+; RV64-NEXT: sd a6, 0(a0)
+; RV64-NEXT: addi a0, sp, 56
+; RV64-NEXT: sd a7, 0(a0)
+; RV64-NEXT: addi a0, sp, 8
+; RV64-NEXT: addi a2, sp, 16
+; RV64-NEXT: srli a3, a0, 32
+; RV64-NEXT: addi a4, a2, 4
+; RV64-NEXT: srliw a5, a0, 16
+; RV64-NEXT: addi a6, a2, 2
+; RV64-NEXT: lui a7, 16
+; RV64-NEXT: addi a7, a7, -1
+; RV64-NEXT: and t0, a0, a7
+; RV64-NEXT: srliw t0, t0, 8
+; RV64-NEXT: addi t1, a2, 1
+; RV64-NEXT: sb a0, 0(a2)
+; RV64-NEXT: sb t0, 0(t1)
+; RV64-NEXT: srliw a2, a5, 8
+; RV64-NEXT: addi t0, a6, 1
+; RV64-NEXT: sb a5, 0(a6)
+; RV64-NEXT: sb a2, 0(t0)
+; RV64-NEXT: srliw a2, a3, 16
+; RV64-NEXT: addi a5, a4, 2
+; RV64-NEXT: and a6, a3, a7
+; RV64-NEXT: srliw a6, a6, 8
+; RV64-NEXT: addi a7, a4, 1
+; RV64-NEXT: sb a3, 0(a4)
+; RV64-NEXT: sb a6, 0(a7)
+; RV64-NEXT: srliw a3, a2, 8
+; RV64-NEXT: addi a4, a5, 1
+; RV64-NEXT: sb a2, 0(a5)
+; RV64-NEXT: sb a3, 0(a4)
+; RV64-NEXT: ld a2, 0(a0)
+; RV64-NEXT: addi a2, a2, 7
+; RV64-NEXT: andi a2, a2, -8
+; RV64-NEXT: addi a3, a2, 8
+; RV64-NEXT: sd a3, 0(a0)
+; RV64-NEXT: ld a0, 0(a2)
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: addi sp, sp, 64
+; RV64-NEXT: ret
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %1 = va_arg ptr %va, double
+ call void @llvm.va_end(ptr %va)
+ %2 = bitcast double %1 to i64
+ %3 = add i64 %b, %2
+ ret i64 %3
+}
+
+define void @va3_caller() nounwind {
+; RV32-LABEL: va3_caller:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: lui a0, 5
+; RV32-NEXT: addi a3, a0, -480
+; RV32-NEXT: li a0, 2
+; RV32-NEXT: li a1, 1111
+; RV32-NEXT: li a2, 0
+; RV32-NEXT: call va3 at plt
+; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: va3_caller:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -16
+; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT: lui a0, 5
+; RV64-NEXT: addiw a2, a0, -480
+; RV64-NEXT: li a0, 2
+; RV64-NEXT: li a1, 1111
+; RV64-NEXT: call va3 at plt
+; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT: addi sp, sp, 16
+; RV64-NEXT: ret
+ %1 = call i64 (i32, i64, ...) @va3(i32 2, i64 1111, i32 20000)
+ ret void
+}
+
+declare void @llvm.va_copy(ptr, ptr)
+
+define i32 @va4_va_copy(i32 %argno, ...) nounwind {
+; RV32-LABEL: va4_va_copy:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -64
+; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32-NEXT: addi a0, sp, 36
+; RV32-NEXT: sw a1, 0(a0)
+; RV32-NEXT: addi a0, sp, 40
+; RV32-NEXT: sw a2, 0(a0)
+; RV32-NEXT: addi a0, sp, 44
+; RV32-NEXT: sw a3, 0(a0)
+; RV32-NEXT: addi a0, sp, 48
+; RV32-NEXT: sw a4, 0(a0)
+; RV32-NEXT: addi a0, sp, 52
+; RV32-NEXT: sw a5, 0(a0)
+; RV32-NEXT: addi a0, sp, 56
+; RV32-NEXT: sw a6, 0(a0)
+; RV32-NEXT: addi a0, sp, 60
+; RV32-NEXT: sw a7, 0(a0)
+; RV32-NEXT: addi s0, sp, 16
+; RV32-NEXT: addi a0, sp, 36
+; RV32-NEXT: srli a1, s0, 16
+; RV32-NEXT: addi a2, a0, 2
+; RV32-NEXT: lui a3, 16
+; RV32-NEXT: addi a3, a3, -1
+; RV32-NEXT: and a3, s0, a3
+; RV32-NEXT: srli a3, a3, 8
+; RV32-NEXT: addi a4, a0, 1
+; RV32-NEXT: sb s0, 0(a0)
+; RV32-NEXT: sb a3, 0(a4)
+; RV32-NEXT: srli a0, a1, 8
+; RV32-NEXT: addi a3, a2, 1
+; RV32-NEXT: sb a1, 0(a2)
+; RV32-NEXT: sb a0, 0(a3)
+; RV32-NEXT: lw a0, 0(s0)
+; RV32-NEXT: addi a0, a0, 3
+; RV32-NEXT: andi a0, a0, -4
+; RV32-NEXT: addi a1, a0, 4
+; RV32-NEXT: sw a1, 0(s0)
+; RV32-NEXT: lw a1, 0(s0)
+; RV32-NEXT: addi a2, sp, 12
+; RV32-NEXT: lw s1, 0(a0)
+; RV32-NEXT: sw a2, 0(a1)
+; RV32-NEXT: lw a0, 0(a2)
+; RV32-NEXT: call notdead at plt
+; RV32-NEXT: lw a0, 0(s0)
+; RV32-NEXT: addi a0, a0, 3
+; RV32-NEXT: andi a0, a0, -4
+; RV32-NEXT: addi a1, a0, 4
+; RV32-NEXT: sw a1, 0(s0)
+; RV32-NEXT: lw a1, 0(s0)
+; RV32-NEXT: lw a0, 0(a0)
+; RV32-NEXT: addi a1, a1, 3
+; RV32-NEXT: andi a1, a1, -4
+; RV32-NEXT: addi a2, a1, 4
+; RV32-NEXT: sw a2, 0(s0)
+; RV32-NEXT: lw a2, 0(s0)
+; RV32-NEXT: lw a1, 0(a1)
+; RV32-NEXT: addi a2, a2, 3
+; RV32-NEXT: andi a2, a2, -4
+; RV32-NEXT: addi a3, a2, 4
+; RV32-NEXT: sw a3, 0(s0)
+; RV32-NEXT: lw a2, 0(a2)
+; RV32-NEXT: add a0, a0, s1
+; RV32-NEXT: add a1, a1, a2
+; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32-NEXT: addi sp, sp, 64
+; RV32-NEXT: ret
+;
+; RV64-LABEL: va4_va_copy:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -112
+; RV64-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64-NEXT: addi a0, sp, 56
+; RV64-NEXT: sd a1, 0(a0)
+; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: addi a0, sp, 72
+; RV64-NEXT: sd a3, 0(a0)
+; RV64-NEXT: addi a0, sp, 80
+; RV64-NEXT: sd a4, 0(a0)
+; RV64-NEXT: addi a0, sp, 88
+; RV64-NEXT: sd a5, 0(a0)
+; RV64-NEXT: addi a0, sp, 96
+; RV64-NEXT: sd a6, 0(a0)
+; RV64-NEXT: addi a0, sp, 104
+; RV64-NEXT: sd a7, 0(a0)
+; RV64-NEXT: addi s0, sp, 16
+; RV64-NEXT: addi a0, sp, 56
+; RV64-NEXT: srli a1, s0, 32
+; RV64-NEXT: addi a2, a0, 4
+; RV64-NEXT: srliw a3, s0, 16
+; RV64-NEXT: addi a4, a0, 2
+; RV64-NEXT: lui a5, 16
+; RV64-NEXT: addi a5, a5, -1
+; RV64-NEXT: and a6, s0, a5
+; RV64-NEXT: srliw a6, a6, 8
+; RV64-NEXT: addi a7, a0, 1
+; RV64-NEXT: sb s0, 0(a0)
+; RV64-NEXT: sb a6, 0(a7)
+; RV64-NEXT: srliw a0, a3, 8
+; RV64-NEXT: addi a6, a4, 1
+; RV64-NEXT: sb a3, 0(a4)
+; RV64-NEXT: sb a0, 0(a6)
+; RV64-NEXT: srliw a0, a1, 16
+; RV64-NEXT: addi a3, a2, 2
+; RV64-NEXT: and a5, a1, a5
+; RV64-NEXT: srliw a4, a5, 8
+; RV64-NEXT: addi a5, a2, 1
+; RV64-NEXT: sb a1, 0(a2)
+; RV64-NEXT: sb a4, 0(a5)
+; RV64-NEXT: srliw a1, a0, 8
+; RV64-NEXT: addi a2, a3, 1
+; RV64-NEXT: sb a0, 0(a3)
+; RV64-NEXT: sb a1, 0(a2)
+; RV64-NEXT: ld a0, 0(s0)
+; RV64-NEXT: addi a0, a0, 3
+; RV64-NEXT: andi a0, a0, -4
+; RV64-NEXT: addi a1, a0, 4
+; RV64-NEXT: sd a1, 0(s0)
+; RV64-NEXT: ld a1, 0(s0)
+; RV64-NEXT: addi a2, sp, 8
+; RV64-NEXT: lw s1, 0(a0)
+; RV64-NEXT: sd a2, 0(a1)
+; RV64-NEXT: addi a0, a2, 4
+; RV64-NEXT: lw a0, 0(a0)
+; RV64-NEXT: lwu a1, 0(a2)
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: or a0, a0, a1
+; RV64-NEXT: call notdead at plt
+; RV64-NEXT: ld a0, 0(s0)
+; RV64-NEXT: addi a0, a0, 3
+; RV64-NEXT: andi a0, a0, -4
+; RV64-NEXT: addi a1, a0, 4
+; RV64-NEXT: sd a1, 0(s0)
+; RV64-NEXT: ld a1, 0(s0)
+; RV64-NEXT: lw a0, 0(a0)
+; RV64-NEXT: addi a1, a1, 3
+; RV64-NEXT: andi a1, a1, -4
+; RV64-NEXT: addi a2, a1, 4
+; RV64-NEXT: sd a2, 0(s0)
+; RV64-NEXT: ld a2, 0(s0)
+; RV64-NEXT: lw a1, 0(a1)
+; RV64-NEXT: addi a2, a2, 3
+; RV64-NEXT: andi a2, a2, -4
+; RV64-NEXT: addi a3, a2, 4
+; RV64-NEXT: sd a3, 0(s0)
+; RV64-NEXT: lw a2, 0(a2)
+; RV64-NEXT: add a0, a0, s1
+; RV64-NEXT: add a1, a1, a2
+; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64-NEXT: addi sp, sp, 112
+; RV64-NEXT: ret
+ %vargs = alloca ptr
+ %wargs = alloca ptr
+ call void @llvm.va_start(ptr %vargs)
+ %1 = va_arg ptr %vargs, i32
+ call void @llvm.va_copy(ptr %wargs, ptr %vargs)
+ %2 = load ptr, ptr %wargs, align 4
+ call void @notdead(ptr %2)
+ %3 = va_arg ptr %vargs, i32
+ %4 = va_arg ptr %vargs, i32
+ %5 = va_arg ptr %vargs, i32
+ call void @llvm.va_end(ptr %vargs)
+ call void @llvm.va_end(ptr %wargs)
+ %add1 = add i32 %3, %1
+ %add2 = add i32 %add1, %4
+ %add3 = add i32 %add2, %5
+ ret i32 %add3
+}
+
+; A function with no fixed arguments is not valid C, but can be
+; specified in LLVM IR. We must ensure the vararg save area is
+; still set up correctly.
+
+define i32 @va6_no_fixed_args(...) nounwind {
+; RV32-LABEL: va6_no_fixed_args:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -48
+; RV32-NEXT: addi t0, sp, 16
+; RV32-NEXT: sw a0, 0(t0)
+; RV32-NEXT: addi a0, sp, 20
+; RV32-NEXT: sw a1, 0(a0)
+; RV32-NEXT: addi a0, sp, 24
+; RV32-NEXT: sw a2, 0(a0)
+; RV32-NEXT: addi a0, sp, 28
+; RV32-NEXT: sw a3, 0(a0)
+; RV32-NEXT: addi a0, sp, 32
+; RV32-NEXT: sw a4, 0(a0)
+; RV32-NEXT: addi a0, sp, 36
+; RV32-NEXT: sw a5, 0(a0)
+; RV32-NEXT: addi a0, sp, 40
+; RV32-NEXT: sw a6, 0(a0)
+; RV32-NEXT: addi a0, sp, 44
+; RV32-NEXT: sw a7, 0(a0)
+; RV32-NEXT: addi a0, sp, 12
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: srli a2, a0, 16
+; RV32-NEXT: addi a3, a1, 2
+; RV32-NEXT: lui a4, 16
+; RV32-NEXT: addi a4, a4, -1
+; RV32-NEXT: and a4, a0, a4
+; RV32-NEXT: srli a4, a4, 8
+; RV32-NEXT: addi a5, a1, 1
+; RV32-NEXT: sb a0, 0(a1)
+; RV32-NEXT: sb a4, 0(a5)
+; RV32-NEXT: srli a1, a2, 8
+; RV32-NEXT: addi a4, a3, 1
+; RV32-NEXT: sb a2, 0(a3)
+; RV32-NEXT: sb a1, 0(a4)
+; RV32-NEXT: lw a1, 0(a0)
+; RV32-NEXT: addi a1, a1, 3
+; RV32-NEXT: andi a1, a1, -4
+; RV32-NEXT: addi a2, a1, 4
+; RV32-NEXT: sw a2, 0(a0)
+; RV32-NEXT: lw a0, 0(a1)
+; RV32-NEXT: addi sp, sp, 48
+; RV32-NEXT: ret
+;
+; RV64-LABEL: va6_no_fixed_args:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -80
+; RV64-NEXT: addi t0, sp, 16
+; RV64-NEXT: sd a0, 0(t0)
+; RV64-NEXT: addi a0, sp, 24
+; RV64-NEXT: sd a1, 0(a0)
+; RV64-NEXT: addi a0, sp, 32
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: addi a0, sp, 40
+; RV64-NEXT: sd a3, 0(a0)
+; RV64-NEXT: addi a0, sp, 48
+; RV64-NEXT: sd a4, 0(a0)
+; RV64-NEXT: addi a0, sp, 56
+; RV64-NEXT: sd a5, 0(a0)
+; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: sd a6, 0(a0)
+; RV64-NEXT: addi a0, sp, 72
+; RV64-NEXT: sd a7, 0(a0)
+; RV64-NEXT: addi a0, sp, 8
+; RV64-NEXT: addi a1, sp, 16
+; RV64-NEXT: srli a2, a0, 32
+; RV64-NEXT: addi a3, a1, 4
+; RV64-NEXT: srliw a4, a0, 16
+; RV64-NEXT: addi a5, a1, 2
+; RV64-NEXT: lui a6, 16
+; RV64-NEXT: addi a6, a6, -1
+; RV64-NEXT: and a7, a0, a6
+; RV64-NEXT: srliw a7, a7, 8
+; RV64-NEXT: addi t0, a1, 1
+; RV64-NEXT: sb a0, 0(a1)
+; RV64-NEXT: sb a7, 0(t0)
+; RV64-NEXT: srliw a1, a4, 8
+; RV64-NEXT: addi a7, a5, 1
+; RV64-NEXT: sb a4, 0(a5)
+; RV64-NEXT: sb a1, 0(a7)
+; RV64-NEXT: srliw a1, a2, 16
+; RV64-NEXT: addi a4, a3, 2
+; RV64-NEXT: and a5, a2, a6
+; RV64-NEXT: srliw a5, a5, 8
+; RV64-NEXT: addi a6, a3, 1
+; RV64-NEXT: sb a2, 0(a3)
+; RV64-NEXT: sb a5, 0(a6)
+; RV64-NEXT: srliw a2, a1, 8
+; RV64-NEXT: addi a3, a4, 1
+; RV64-NEXT: sb a1, 0(a4)
+; RV64-NEXT: sb a2, 0(a3)
+; RV64-NEXT: ld a1, 0(a0)
+; RV64-NEXT: addi a1, a1, 3
+; RV64-NEXT: andi a1, a1, -4
+; RV64-NEXT: addi a2, a1, 4
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: lw a0, 0(a1)
+; RV64-NEXT: addi sp, sp, 80
+; RV64-NEXT: ret
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %1 = va_arg ptr %va, i32
+ call void @llvm.va_end(ptr %va)
+ ret i32 %1
+}
+
+; TODO: improve constant materialization of stack addresses
+
+define i32 @va_large_stack(ptr %fmt, ...) {
+; RV32-LABEL: va_large_stack:
+; RV32: # %bb.0:
+; RV32-NEXT: lui a0, 24414
+; RV32-NEXT: addi a0, a0, 304
+; RV32-NEXT: sub sp, sp, a0
+; RV32-NEXT: .cfi_def_cfa_offset 100000048
+; RV32-NEXT: lui a0, 24414
+; RV32-NEXT: addi a0, a0, 276
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: sw a1, 0(a0)
+; RV32-NEXT: lui a0, 24414
+; RV32-NEXT: addi a0, a0, 280
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: sw a2, 0(a0)
+; RV32-NEXT: lui a0, 24414
+; RV32-NEXT: addi a0, a0, 284
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: sw a3, 0(a0)
+; RV32-NEXT: lui a0, 24414
+; RV32-NEXT: addi a0, a0, 288
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: sw a4, 0(a0)
+; RV32-NEXT: lui a0, 24414
+; RV32-NEXT: addi a0, a0, 292
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: sw a5, 0(a0)
+; RV32-NEXT: lui a0, 24414
+; RV32-NEXT: addi a0, a0, 296
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a1, sp, 12
+; RV32-NEXT: lui a2, 24414
+; RV32-NEXT: addi a2, a2, 276
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: srli a3, a1, 16
+; RV32-NEXT: addi a4, a2, 2
+; RV32-NEXT: lui a5, 16
+; RV32-NEXT: addi a5, a5, -1
+; RV32-NEXT: and a5, a1, a5
+; RV32-NEXT: srli a5, a5, 8
+; RV32-NEXT: sb a1, 0(a2)
+; RV32-NEXT: addi a2, a2, 1
+; RV32-NEXT: sb a5, 0(a2)
+; RV32-NEXT: srli a2, a3, 8
+; RV32-NEXT: addi a5, a4, 1
+; RV32-NEXT: sb a3, 0(a4)
+; RV32-NEXT: sb a2, 0(a5)
+; RV32-NEXT: lw a2, 0(a1)
+; RV32-NEXT: sw a6, 0(a0)
+; RV32-NEXT: lui a0, 24414
+; RV32-NEXT: addi a0, a0, 300
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: sw a7, 0(a0)
+; RV32-NEXT: addi a0, a2, 4
+; RV32-NEXT: sw a0, 0(a1)
+; RV32-NEXT: lw a0, 0(a2)
+; RV32-NEXT: lui a1, 24414
+; RV32-NEXT: addi a1, a1, 304
+; RV32-NEXT: add sp, sp, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: va_large_stack:
+; RV64: # %bb.0:
+; RV64-NEXT: lui a0, 24414
+; RV64-NEXT: addiw a0, a0, 336
+; RV64-NEXT: sub sp, sp, a0
+; RV64-NEXT: .cfi_def_cfa_offset 100000080
+; RV64-NEXT: lui a0, 24414
+; RV64-NEXT: addiw a0, a0, 280
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: sd a1, 0(a0)
+; RV64-NEXT: lui a0, 24414
+; RV64-NEXT: addiw a0, a0, 288
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: sd a2, 0(a0)
+; RV64-NEXT: lui a0, 24414
+; RV64-NEXT: addiw a0, a0, 296
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: sd a3, 0(a0)
+; RV64-NEXT: lui a0, 24414
+; RV64-NEXT: addiw a0, a0, 304
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: sd a4, 0(a0)
+; RV64-NEXT: lui a0, 24414
+; RV64-NEXT: addiw a0, a0, 312
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: sd a5, 0(a0)
+; RV64-NEXT: lui a0, 24414
+; RV64-NEXT: addiw a0, a0, 320
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: sd a6, 0(a0)
+; RV64-NEXT: addi a0, sp, 8
+; RV64-NEXT: lui a1, 24414
+; RV64-NEXT: addiw a1, a1, 280
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: srli a2, a0, 32
+; RV64-NEXT: addi a3, a1, 4
+; RV64-NEXT: srliw a4, a0, 16
+; RV64-NEXT: addi a5, a1, 2
+; RV64-NEXT: lui a6, 16
+; RV64-NEXT: addi a6, a6, -1
+; RV64-NEXT: and t0, a0, a6
+; RV64-NEXT: srliw t0, t0, 8
+; RV64-NEXT: sb a0, 0(a1)
+; RV64-NEXT: addi a1, a1, 1
+; RV64-NEXT: sb t0, 0(a1)
+; RV64-NEXT: srliw a1, a4, 8
+; RV64-NEXT: addi t0, a5, 1
+; RV64-NEXT: sb a4, 0(a5)
+; RV64-NEXT: sb a1, 0(t0)
+; RV64-NEXT: srliw a1, a2, 16
+; RV64-NEXT: addi a4, a3, 2
+; RV64-NEXT: and a5, a2, a6
+; RV64-NEXT: srliw a5, a5, 8
+; RV64-NEXT: addi a6, a3, 1
+; RV64-NEXT: sb a2, 0(a3)
+; RV64-NEXT: sb a5, 0(a6)
+; RV64-NEXT: srliw a2, a1, 8
+; RV64-NEXT: addi a3, a4, 1
+; RV64-NEXT: sb a1, 0(a4)
+; RV64-NEXT: sb a2, 0(a3)
+; RV64-NEXT: addi a1, a0, 4
+; RV64-NEXT: lw a2, 0(a1)
+; RV64-NEXT: lwu a3, 0(a0)
+; RV64-NEXT: lui a4, 24414
+; RV64-NEXT: addiw a4, a4, 328
+; RV64-NEXT: add a4, sp, a4
+; RV64-NEXT: sd a7, 0(a4)
+; RV64-NEXT: slli a2, a2, 32
+; RV64-NEXT: or a2, a2, a3
+; RV64-NEXT: addi a3, a2, 4
+; RV64-NEXT: srli a4, a3, 32
+; RV64-NEXT: sw a3, 0(a0)
+; RV64-NEXT: sw a4, 0(a1)
+; RV64-NEXT: lw a0, 0(a2)
+; RV64-NEXT: lui a1, 24414
+; RV64-NEXT: addiw a1, a1, 336
+; RV64-NEXT: add sp, sp, a1
+; RV64-NEXT: ret
+ %large = alloca [ 100000000 x i8 ]
+ %va = alloca ptr
+ call void @llvm.va_start(ptr %va)
+ %argp.cur = load ptr, ptr %va, align 4
+ %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4
+ store ptr %argp.next, ptr %va, align 4
+ %1 = load i32, ptr %argp.cur, align 4
+ call void @llvm.va_end(ptr %va)
+ ret i32 %1
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; LP64: {{.*}}
+; LP64D: {{.*}}
+; LP64F: {{.*}}
>From c0c19ea5ba0dc6271c0a5d469f8d2db0f5433f28 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 27 Nov 2023 16:53:52 -0800
Subject: [PATCH 2/5] use legalizeIntrinsic
---
llvm/docs/GlobalISel/GenericOpcode.rst | 11 ----
.../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 1 -
llvm/include/llvm/Support/TargetOpcodes.def | 4 --
llvm/include/llvm/Target/GenericOpcodes.td | 7 ---
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 6 ---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 31 -----------
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 51 +++++++++++++++++--
.../Target/RISCV/GISel/RISCVLegalizerInfo.h | 3 ++
8 files changed, 51 insertions(+), 63 deletions(-)
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index 34ba9ec00ab0ea..26ff34376fb838 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -899,17 +899,6 @@ G_VAARG
I found no documentation for this instruction at the time of writing.
-G_VACOPY
-^^^^^^^^
-
-In a target-dependent way, it copies the source va_list element into the
-destination va_list element. This opcode is necessary because the copy may be
-arbitrarily complex.
-
-.. code-block:: none
-
- G_VACOPY %2(p0), %3(p0)
-
Other Operations
----------------
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
index 81ab4048cfd769..711ba10247c34d 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -433,7 +433,6 @@ class LegalizerHelper {
LegalizeResult lowerMemcpyInline(MachineInstr &MI);
LegalizeResult lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
LegalizeResult lowerVAArg(MachineInstr &MI);
- LegalizeResult lowerVACopy(MachineInstr &MI);
};
/// Helper function that creates a libcall to the given \p Name using the given
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 5c3da9e65c7406..16a747d23e73e2 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -457,10 +457,6 @@ HANDLE_TARGET_OPCODE(G_VASTART)
/// Generic va_arg instruction. Stores to its one pointer operand.
HANDLE_TARGET_OPCODE(G_VAARG)
-/// Generic va_copy instruction. Copies the source element into the destination
-/// element.
-HANDLE_TARGET_OPCODE(G_VACOPY)
-
// Generic sign extend
HANDLE_TARGET_OPCODE(G_SEXT)
HANDLE_TARGET_OPCODE(G_SEXT_INREG)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 3b26ab35fa509f..9a9c09d3c20d61 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -155,13 +155,6 @@ def G_VASTART : GenericInstruction {
let mayStore = true;
}
-def G_VACOPY : GenericInstruction {
- let OutOperandList = (outs);
- let InOperandList = (ins type0:$dest, type0:$src);
- let hasSideEffects = true;
- let mayStore = true;
-}
-
def G_VAARG : GenericInstruction {
let OutOperandList = (outs type0:$val);
let InOperandList = (ins type1:$list, unknown:$align);
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index d1554140e9fcb6..14a4e72152e7c4 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2076,12 +2076,6 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
ListSize, Alignment));
return true;
}
- case Intrinsic::vacopy: {
- Register DstList = getOrCreateVReg(*CI.getArgOperand(0));
- Register SrcList = getOrCreateVReg(*CI.getArgOperand(1));
- MIRBuilder.buildInstr(TargetOpcode::G_VACOPY, {}, {DstList, SrcList});
- return true;
- }
case Intrinsic::dbg_value: {
// This form of DBG_VALUE is target-independent.
const DbgValueInst &DI = cast<DbgValueInst>(CI);
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index c59ad2af37da70..37e7153be5720e 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3795,8 +3795,6 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
return lowerVectorReduction(MI);
case G_VAARG:
return lowerVAArg(MI);
- case G_VACOPY:
- return lowerVACopy(MI);
}
}
@@ -7941,35 +7939,6 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerVAArg(MachineInstr &MI) {
return Legalized;
}
-LegalizerHelper::LegalizeResult LegalizerHelper::lowerVACopy(MachineInstr &MI) {
- MachineFunction &MF = *MI.getMF();
- const DataLayout &DL = MIRBuilder.getDataLayout();
- LLVMContext &Ctx = MF.getFunction().getContext();
-
- Register DstLst = MI.getOperand(0).getReg();
- LLT PtrTy = MRI.getType(DstLst);
-
- // Load the source va_list
- Align Alignment = Align(DL.getABITypeAlign(getTypeForLLT(PtrTy, Ctx)));
- MachineMemOperand *LoadMMO =
- MF.getMachineMemOperand(MachinePointerInfo::getUnknownStack(MF),
- MachineMemOperand::MOLoad, PtrTy, Alignment);
- Register Tmp = MRI.createGenericVirtualRegister(PtrTy);
- Register SrcLst = MI.getOperand(1).getReg();
- MIRBuilder.buildLoad(Tmp, SrcLst, *LoadMMO);
-
- // Store the result in the destination va_list
- MachineMemOperand *StoreMMO =
- MF.getMachineMemOperand(MachinePointerInfo::getUnknownStack(MF),
- MachineMemOperand::MOStore, PtrTy, Alignment);
- MIRBuilder.buildStore(DstLst, Tmp, *StoreMMO);
-
- Observer.changedInstr(MI);
- Observer.erasingInstr(MI);
- MI.eraseFromParent();
- return Legalized;
-}
-
static bool shouldLowerMemFuncForSize(const MachineFunction &MF) {
// On Darwin, -Os means optimize for size without hurting performance, so
// only really optimize for size when -Oz (MinSize) is used.
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 52018eb56ad338..ffcc677245f39d 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -325,12 +325,57 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.clampScalar(0, s32, sXLen)
.lowerForCartesianProduct({s32, sXLen, p0}, {p0});
- // The va_list arguments must be a pointer
- getActionDefinitionsBuilder(G_VACOPY).lowerFor({p0});
-
getLegacyLegalizerInfo().computeTables();
}
+static Type *getTypeForLLT(LLT Ty, LLVMContext &C) {
+ if (Ty.isVector())
+ return FixedVectorType::get(IntegerType::get(C, Ty.getScalarSizeInBits()),
+ Ty.getNumElements());
+ return IntegerType::get(C, Ty.getSizeInBits());
+}
+
+#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
+bool RISCVLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
+ MachineInstr &MI) const {
+ Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();
+ switch (IntrinsicID) {
+ default:
+ return false;
+ case Intrinsic::vacopy: {
+ // vacopy arguments must be legal because of the intrinsic signature.
+ // No need to check here.
+
+ MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
+ MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
+ MachineFunction &MF = *MI.getMF();
+ const DataLayout &DL = MIRBuilder.getDataLayout();
+ LLVMContext &Ctx = MF.getFunction().getContext();
+
+ Register DstLst = MI.getOperand(0).getReg();
+ LLT PtrTy = MRI.getType(DstLst);
+
+ // Load the source va_list
+ Align Alignment = Align(DL.getABITypeAlign(getTypeForLLT(PtrTy, Ctx)));
+ MachineMemOperand *LoadMMO =
+ MF.getMachineMemOperand(MachinePointerInfo::getUnknownStack(MF),
+ MachineMemOperand::MOLoad, PtrTy, Alignment);
+ Register Tmp = MRI.createGenericVirtualRegister(PtrTy);
+ Register SrcLst = MI.getOperand(1).getReg();
+ MIRBuilder.buildLoad(Tmp, SrcLst, *LoadMMO);
+
+ // Store the result in the destination va_list
+ MachineMemOperand *StoreMMO =
+ MF.getMachineMemOperand(MachinePointerInfo::getUnknownStack(MF),
+ MachineMemOperand::MOStore, PtrTy, Alignment);
+ MIRBuilder.buildStore(DstLst, Tmp, *StoreMMO);
+
+ MI.eraseFromParent();
+ return true;
+ }
+ }
+}
+
bool RISCVLegalizerInfo::legalizeShlAshrLshr(
MachineInstr &MI, MachineIRBuilder &MIRBuilder,
GISelChangeObserver &Observer) const {
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
index 246ea90dcd7490..48c36976501fc5 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
@@ -32,6 +32,9 @@ class RISCVLegalizerInfo : public LegalizerInfo {
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
+ bool legalizeIntrinsic(LegalizerHelper &Helper,
+ MachineInstr &MI) const override;
+
private:
bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
GISelChangeObserver &Observer) const;
>From 3de9035bf660b5bee659c048cbbcf109786b807a Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 29 Nov 2023 10:43:13 -0800
Subject: [PATCH 3/5] !fixup fix MPO and simplify builder calls
---
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 18 ++++++---------
.../RISCV/GlobalISel/irtranslator/vacopy.ll | 4 ++--
.../GlobalISel/legalizer/legalize-vacopy.mir | 23 +++++++++++++++++++
3 files changed, 32 insertions(+), 13 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vacopy.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index ffcc677245f39d..22ed2c27cf17fa 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -13,6 +13,7 @@
#include "RISCVLegalizerInfo.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
+#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -335,7 +336,6 @@ static Type *getTypeForLLT(LLT Ty, LLVMContext &C) {
return IntegerType::get(C, Ty.getSizeInBits());
}
-#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
bool RISCVLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const {
Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();
@@ -352,22 +352,18 @@ bool RISCVLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
const DataLayout &DL = MIRBuilder.getDataLayout();
LLVMContext &Ctx = MF.getFunction().getContext();
- Register DstLst = MI.getOperand(0).getReg();
+ Register DstLst = MI.getOperand(1).getReg();
LLT PtrTy = MRI.getType(DstLst);
// Load the source va_list
Align Alignment = Align(DL.getABITypeAlign(getTypeForLLT(PtrTy, Ctx)));
- MachineMemOperand *LoadMMO =
- MF.getMachineMemOperand(MachinePointerInfo::getUnknownStack(MF),
- MachineMemOperand::MOLoad, PtrTy, Alignment);
- Register Tmp = MRI.createGenericVirtualRegister(PtrTy);
- Register SrcLst = MI.getOperand(1).getReg();
- MIRBuilder.buildLoad(Tmp, SrcLst, *LoadMMO);
+ MachineMemOperand *LoadMMO = MF.getMachineMemOperand(
+ MachinePointerInfo(), MachineMemOperand::MOLoad, PtrTy, Alignment);
+ auto Tmp = MIRBuilder.buildLoad(PtrTy, MI.getOperand(2), *LoadMMO);
// Store the result in the destination va_list
- MachineMemOperand *StoreMMO =
- MF.getMachineMemOperand(MachinePointerInfo::getUnknownStack(MF),
- MachineMemOperand::MOStore, PtrTy, Alignment);
+ MachineMemOperand *StoreMMO = MF.getMachineMemOperand(
+ MachinePointerInfo(), MachineMemOperand::MOStore, PtrTy, Alignment);
MIRBuilder.buildStore(DstLst, Tmp, *StoreMMO);
MI.eraseFromParent();
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
index 1fdd2e1cdc7650..48d72108335e46 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
@@ -12,7 +12,7 @@ define void @test_va_copy(ptr %dest_list, ptr %src_list) {
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
- ; RV32I-NEXT: G_VACOPY [[COPY]](p0), [[COPY1]]
+ ; RV32I-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[COPY]](p0), [[COPY1]](p0)
; RV32I-NEXT: PseudoRET
;
; RV64I-LABEL: name: test_va_copy
@@ -21,7 +21,7 @@ define void @test_va_copy(ptr %dest_list, ptr %src_list) {
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
- ; RV64I-NEXT: G_VACOPY [[COPY]](p0), [[COPY1]]
+ ; RV64I-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[COPY]](p0), [[COPY1]](p0)
; RV64I-NEXT: PseudoRET
call void @llvm.va_copy(ptr %dest_list, ptr %src_list)
ret void
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vacopy.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vacopy.mir
new file mode 100644
index 00000000000000..f9eda1252937e8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vacopy.mir
@@ -0,0 +1,23 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: test_va_copy
+body: |
+ bb.1:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: test_va_copy
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY1]](p0) :: (load (p0))
+ ; CHECK-NEXT: G_STORE [[COPY]](p0), [[LOAD]](p0) :: (store (p0))
+ ; CHECK-NEXT: PseudoRET
+ %0:_(p0) = COPY $x10
+ %1:_(p0) = COPY $x11
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), %0(p0), %1(p0)
+ PseudoRET
+...
>From 6679dbe22629faff95a66ec204539ed9ae255287 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 30 Nov 2023 09:31:47 -0800
Subject: [PATCH 4/5] !fixup remove Align constructor; use builder to create
genericreg; remove incorrect observer call
---
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 22ed2c27cf17fa..f47db58e09372d 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -356,7 +356,7 @@ bool RISCVLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
LLT PtrTy = MRI.getType(DstLst);
// Load the source va_list
- Align Alignment = Align(DL.getABITypeAlign(getTypeForLLT(PtrTy, Ctx)));
+ Align Alignment = DL.getABITypeAlign(getTypeForLLT(PtrTy, Ctx));
MachineMemOperand *LoadMMO = MF.getMachineMemOperand(
MachinePointerInfo(), MachineMemOperand::MOLoad, PtrTy, Alignment);
auto Tmp = MIRBuilder.buildLoad(PtrTy, MI.getOperand(2), *LoadMMO);
>From 04d3975c0ef11945f72fadd64239b48b7a4670a4 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Fri, 8 Dec 2023 10:32:32 -0800
Subject: [PATCH 5/5] !fixup remove vararg.ll test. It will be comitted
seperately.
---
llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll | 1896 ------------------
1 file changed, 1896 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
deleted file mode 100644
index eba35e2f4944c6..00000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
+++ /dev/null
@@ -1,1896 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV32,ILP32 %s
-; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32 %s
-; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d -target-abi ilp32f \
-; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32F %s
-; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d -target-abi ilp32d \
-; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32D %s
-; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV64,LP64 %s
-; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d -target-abi lp64f \
-; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV64,LP64F %s
-; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d -target-abi lp64d \
-; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV64,LP64D %s
-
-; The same vararg calling convention is used for ilp32/ilp32f/ilp32d and for
-; lp64/lp64f/lp64d. Different CHECK lines are required due to slight
-; codegen differences due to the way the f64 load operations are lowered and
-; because the PseudoCALL specifies the calling convention.
-; The nounwind attribute is omitted for some of the tests, to check that CFI
-; directives are correctly generated.
-
-declare void @llvm.va_start(ptr)
-declare void @llvm.va_end(ptr)
-
-declare void @notdead(ptr)
-
-; Although frontends are recommended to not generate va_arg due to the lack of
-; support for aggregate types, we test simple cases here to ensure they are
-; lowered correctly
-
-define i32 @va1(ptr %fmt, ...) {
-; RV32-LABEL: va1:
-; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -48
-; RV32-NEXT: .cfi_def_cfa_offset 48
-; RV32-NEXT: addi a0, sp, 20
-; RV32-NEXT: sw a1, 0(a0)
-; RV32-NEXT: addi a0, sp, 24
-; RV32-NEXT: sw a2, 0(a0)
-; RV32-NEXT: addi a0, sp, 28
-; RV32-NEXT: sw a3, 0(a0)
-; RV32-NEXT: addi a0, sp, 32
-; RV32-NEXT: sw a4, 0(a0)
-; RV32-NEXT: addi a0, sp, 36
-; RV32-NEXT: sw a5, 0(a0)
-; RV32-NEXT: addi a0, sp, 40
-; RV32-NEXT: addi a1, sp, 12
-; RV32-NEXT: addi a2, sp, 20
-; RV32-NEXT: srli a3, a1, 16
-; RV32-NEXT: addi a4, a2, 2
-; RV32-NEXT: lui a5, 16
-; RV32-NEXT: addi a5, a5, -1
-; RV32-NEXT: and a5, a1, a5
-; RV32-NEXT: srli a5, a5, 8
-; RV32-NEXT: sb a1, 0(a2)
-; RV32-NEXT: addi a2, a2, 1
-; RV32-NEXT: sb a5, 0(a2)
-; RV32-NEXT: srli a2, a3, 8
-; RV32-NEXT: addi a5, a4, 1
-; RV32-NEXT: sb a3, 0(a4)
-; RV32-NEXT: sb a2, 0(a5)
-; RV32-NEXT: lw a2, 0(a1)
-; RV32-NEXT: sw a6, 0(a0)
-; RV32-NEXT: addi a0, sp, 44
-; RV32-NEXT: sw a7, 0(a0)
-; RV32-NEXT: addi a0, a2, 4
-; RV32-NEXT: sw a0, 0(a1)
-; RV32-NEXT: lw a0, 0(a2)
-; RV32-NEXT: addi sp, sp, 48
-; RV32-NEXT: ret
-;
-; RV64-LABEL: va1:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -80
-; RV64-NEXT: .cfi_def_cfa_offset 80
-; RV64-NEXT: addi a0, sp, 24
-; RV64-NEXT: sd a1, 0(a0)
-; RV64-NEXT: addi a0, sp, 32
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: addi a0, sp, 40
-; RV64-NEXT: sd a3, 0(a0)
-; RV64-NEXT: addi a0, sp, 48
-; RV64-NEXT: sd a4, 0(a0)
-; RV64-NEXT: addi a0, sp, 56
-; RV64-NEXT: sd a5, 0(a0)
-; RV64-NEXT: addi a0, sp, 64
-; RV64-NEXT: sd a6, 0(a0)
-; RV64-NEXT: addi a0, sp, 8
-; RV64-NEXT: addi a1, sp, 24
-; RV64-NEXT: srli a2, a0, 32
-; RV64-NEXT: addi a3, a1, 4
-; RV64-NEXT: srliw a4, a0, 16
-; RV64-NEXT: addi a5, a1, 2
-; RV64-NEXT: lui a6, 16
-; RV64-NEXT: addi a6, a6, -1
-; RV64-NEXT: and t0, a0, a6
-; RV64-NEXT: srliw t0, t0, 8
-; RV64-NEXT: sb a0, 0(a1)
-; RV64-NEXT: addi a1, a1, 1
-; RV64-NEXT: sb t0, 0(a1)
-; RV64-NEXT: srliw a1, a4, 8
-; RV64-NEXT: addi t0, a5, 1
-; RV64-NEXT: sb a4, 0(a5)
-; RV64-NEXT: sb a1, 0(t0)
-; RV64-NEXT: srliw a1, a2, 16
-; RV64-NEXT: addi a4, a3, 2
-; RV64-NEXT: and a5, a2, a6
-; RV64-NEXT: srliw a5, a5, 8
-; RV64-NEXT: addi a6, a3, 1
-; RV64-NEXT: sb a2, 0(a3)
-; RV64-NEXT: sb a5, 0(a6)
-; RV64-NEXT: srliw a2, a1, 8
-; RV64-NEXT: addi a3, a4, 1
-; RV64-NEXT: sb a1, 0(a4)
-; RV64-NEXT: sb a2, 0(a3)
-; RV64-NEXT: addi a1, a0, 4
-; RV64-NEXT: lw a2, 0(a1)
-; RV64-NEXT: lwu a3, 0(a0)
-; RV64-NEXT: addi a4, sp, 72
-; RV64-NEXT: sd a7, 0(a4)
-; RV64-NEXT: slli a2, a2, 32
-; RV64-NEXT: or a2, a2, a3
-; RV64-NEXT: addi a3, a2, 4
-; RV64-NEXT: srli a4, a3, 32
-; RV64-NEXT: sw a3, 0(a0)
-; RV64-NEXT: sw a4, 0(a1)
-; RV64-NEXT: lw a0, 0(a2)
-; RV64-NEXT: addi sp, sp, 80
-; RV64-NEXT: ret
- %va = alloca ptr
- call void @llvm.va_start(ptr %va)
- %argp.cur = load ptr, ptr %va, align 4
- %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4
- store ptr %argp.next, ptr %va, align 4
- %1 = load i32, ptr %argp.cur, align 4
- call void @llvm.va_end(ptr %va)
- ret i32 %1
-}
-
-; Ensure the adjustment when restoring the stack pointer using the frame
-; pointer is correct
-define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind {
-; RV32-LABEL: va1_va_arg_alloca:
-; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -48
-; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
-; RV32-NEXT: addi s0, sp, 16
-; RV32-NEXT: addi a0, s0, 4
-; RV32-NEXT: sw a1, 0(a0)
-; RV32-NEXT: addi a0, s0, 8
-; RV32-NEXT: sw a2, 0(a0)
-; RV32-NEXT: addi a0, s0, 12
-; RV32-NEXT: sw a3, 0(a0)
-; RV32-NEXT: addi a0, s0, 16
-; RV32-NEXT: sw a4, 0(a0)
-; RV32-NEXT: addi a0, s0, 20
-; RV32-NEXT: sw a5, 0(a0)
-; RV32-NEXT: addi a0, s0, 24
-; RV32-NEXT: sw a6, 0(a0)
-; RV32-NEXT: addi a0, s0, 28
-; RV32-NEXT: sw a7, 0(a0)
-; RV32-NEXT: addi a0, s0, -16
-; RV32-NEXT: addi a1, s0, 4
-; RV32-NEXT: srli a2, a0, 16
-; RV32-NEXT: addi a3, a1, 2
-; RV32-NEXT: lui a4, 16
-; RV32-NEXT: addi a4, a4, -1
-; RV32-NEXT: and a4, a0, a4
-; RV32-NEXT: srli a4, a4, 8
-; RV32-NEXT: addi a5, a1, 1
-; RV32-NEXT: sb a0, 0(a1)
-; RV32-NEXT: sb a4, 0(a5)
-; RV32-NEXT: srli a1, a2, 8
-; RV32-NEXT: addi a4, a3, 1
-; RV32-NEXT: sb a2, 0(a3)
-; RV32-NEXT: sb a1, 0(a4)
-; RV32-NEXT: lw a1, 0(a0)
-; RV32-NEXT: addi a1, a1, 3
-; RV32-NEXT: andi a1, a1, -4
-; RV32-NEXT: addi a2, a1, 4
-; RV32-NEXT: sw a2, 0(a0)
-; RV32-NEXT: lw s1, 0(a1)
-; RV32-NEXT: addi a0, s1, 15
-; RV32-NEXT: andi a0, a0, -16
-; RV32-NEXT: sub a0, sp, a0
-; RV32-NEXT: mv sp, a0
-; RV32-NEXT: call notdead at plt
-; RV32-NEXT: mv a0, s1
-; RV32-NEXT: addi sp, s0, -16
-; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
-; RV32-NEXT: addi sp, sp, 48
-; RV32-NEXT: ret
-;
-; RV64-LABEL: va1_va_arg_alloca:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -96
-; RV64-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; RV64-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: addi s0, sp, 32
-; RV64-NEXT: addi a0, s0, 8
-; RV64-NEXT: sd a1, 0(a0)
-; RV64-NEXT: addi a0, s0, 16
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: addi a0, s0, 24
-; RV64-NEXT: sd a3, 0(a0)
-; RV64-NEXT: addi a0, s0, 32
-; RV64-NEXT: sd a4, 0(a0)
-; RV64-NEXT: addi a0, s0, 40
-; RV64-NEXT: sd a5, 0(a0)
-; RV64-NEXT: addi a0, s0, 48
-; RV64-NEXT: sd a6, 0(a0)
-; RV64-NEXT: addi a0, s0, 56
-; RV64-NEXT: sd a7, 0(a0)
-; RV64-NEXT: addi a0, s0, -32
-; RV64-NEXT: addi a1, s0, 8
-; RV64-NEXT: srli a2, a0, 32
-; RV64-NEXT: addi a3, a1, 4
-; RV64-NEXT: srliw a4, a0, 16
-; RV64-NEXT: addi a5, a1, 2
-; RV64-NEXT: lui a6, 16
-; RV64-NEXT: addi a6, a6, -1
-; RV64-NEXT: and a7, a0, a6
-; RV64-NEXT: srliw a7, a7, 8
-; RV64-NEXT: addi t0, a1, 1
-; RV64-NEXT: sb a0, 0(a1)
-; RV64-NEXT: sb a7, 0(t0)
-; RV64-NEXT: srliw a1, a4, 8
-; RV64-NEXT: addi a7, a5, 1
-; RV64-NEXT: sb a4, 0(a5)
-; RV64-NEXT: sb a1, 0(a7)
-; RV64-NEXT: srliw a1, a2, 16
-; RV64-NEXT: addi a4, a3, 2
-; RV64-NEXT: and a5, a2, a6
-; RV64-NEXT: srliw a5, a5, 8
-; RV64-NEXT: addi a6, a3, 1
-; RV64-NEXT: sb a2, 0(a3)
-; RV64-NEXT: sb a5, 0(a6)
-; RV64-NEXT: srliw a2, a1, 8
-; RV64-NEXT: addi a3, a4, 1
-; RV64-NEXT: sb a1, 0(a4)
-; RV64-NEXT: sb a2, 0(a3)
-; RV64-NEXT: ld a1, 0(a0)
-; RV64-NEXT: addi a1, a1, 3
-; RV64-NEXT: andi a1, a1, -4
-; RV64-NEXT: addi a2, a1, 4
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: lw s1, 0(a1)
-; RV64-NEXT: slli a0, s1, 32
-; RV64-NEXT: srli a0, a0, 32
-; RV64-NEXT: addi a0, a0, 15
-; RV64-NEXT: andi a0, a0, -16
-; RV64-NEXT: sub a0, sp, a0
-; RV64-NEXT: mv sp, a0
-; RV64-NEXT: call notdead at plt
-; RV64-NEXT: mv a0, s1
-; RV64-NEXT: addi sp, s0, -32
-; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; RV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
-; RV64-NEXT: addi sp, sp, 96
-; RV64-NEXT: ret
- %va = alloca ptr
- call void @llvm.va_start(ptr %va)
- %1 = va_arg ptr %va, i32
- %2 = alloca i8, i32 %1
- call void @notdead(ptr %2)
- call void @llvm.va_end(ptr %va)
- ret i32 %1
-}
-
-
-define i32 @va1_va_arg(ptr %fmt, ...) nounwind {
-; RV32-LABEL: va1_va_arg:
-; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -48
-; RV32-NEXT: addi a0, sp, 20
-; RV32-NEXT: sw a1, 0(a0)
-; RV32-NEXT: addi a0, sp, 24
-; RV32-NEXT: sw a2, 0(a0)
-; RV32-NEXT: addi a0, sp, 28
-; RV32-NEXT: sw a3, 0(a0)
-; RV32-NEXT: addi a0, sp, 32
-; RV32-NEXT: sw a4, 0(a0)
-; RV32-NEXT: addi a0, sp, 36
-; RV32-NEXT: sw a5, 0(a0)
-; RV32-NEXT: addi a0, sp, 40
-; RV32-NEXT: sw a6, 0(a0)
-; RV32-NEXT: addi a0, sp, 44
-; RV32-NEXT: sw a7, 0(a0)
-; RV32-NEXT: addi a0, sp, 12
-; RV32-NEXT: addi a1, sp, 20
-; RV32-NEXT: srli a2, a0, 16
-; RV32-NEXT: addi a3, a1, 2
-; RV32-NEXT: lui a4, 16
-; RV32-NEXT: addi a4, a4, -1
-; RV32-NEXT: and a4, a0, a4
-; RV32-NEXT: srli a4, a4, 8
-; RV32-NEXT: addi a5, a1, 1
-; RV32-NEXT: sb a0, 0(a1)
-; RV32-NEXT: sb a4, 0(a5)
-; RV32-NEXT: srli a1, a2, 8
-; RV32-NEXT: addi a4, a3, 1
-; RV32-NEXT: sb a2, 0(a3)
-; RV32-NEXT: sb a1, 0(a4)
-; RV32-NEXT: lw a1, 0(a0)
-; RV32-NEXT: addi a1, a1, 3
-; RV32-NEXT: andi a1, a1, -4
-; RV32-NEXT: addi a2, a1, 4
-; RV32-NEXT: sw a2, 0(a0)
-; RV32-NEXT: lw a0, 0(a1)
-; RV32-NEXT: addi sp, sp, 48
-; RV32-NEXT: ret
-;
-; RV64-LABEL: va1_va_arg:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -80
-; RV64-NEXT: addi a0, sp, 24
-; RV64-NEXT: sd a1, 0(a0)
-; RV64-NEXT: addi a0, sp, 32
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: addi a0, sp, 40
-; RV64-NEXT: sd a3, 0(a0)
-; RV64-NEXT: addi a0, sp, 48
-; RV64-NEXT: sd a4, 0(a0)
-; RV64-NEXT: addi a0, sp, 56
-; RV64-NEXT: sd a5, 0(a0)
-; RV64-NEXT: addi a0, sp, 64
-; RV64-NEXT: sd a6, 0(a0)
-; RV64-NEXT: addi a0, sp, 72
-; RV64-NEXT: sd a7, 0(a0)
-; RV64-NEXT: addi a0, sp, 8
-; RV64-NEXT: addi a1, sp, 24
-; RV64-NEXT: srli a2, a0, 32
-; RV64-NEXT: addi a3, a1, 4
-; RV64-NEXT: srliw a4, a0, 16
-; RV64-NEXT: addi a5, a1, 2
-; RV64-NEXT: lui a6, 16
-; RV64-NEXT: addi a6, a6, -1
-; RV64-NEXT: and a7, a0, a6
-; RV64-NEXT: srliw a7, a7, 8
-; RV64-NEXT: addi t0, a1, 1
-; RV64-NEXT: sb a0, 0(a1)
-; RV64-NEXT: sb a7, 0(t0)
-; RV64-NEXT: srliw a1, a4, 8
-; RV64-NEXT: addi a7, a5, 1
-; RV64-NEXT: sb a4, 0(a5)
-; RV64-NEXT: sb a1, 0(a7)
-; RV64-NEXT: srliw a1, a2, 16
-; RV64-NEXT: addi a4, a3, 2
-; RV64-NEXT: and a5, a2, a6
-; RV64-NEXT: srliw a5, a5, 8
-; RV64-NEXT: addi a6, a3, 1
-; RV64-NEXT: sb a2, 0(a3)
-; RV64-NEXT: sb a5, 0(a6)
-; RV64-NEXT: srliw a2, a1, 8
-; RV64-NEXT: addi a3, a4, 1
-; RV64-NEXT: sb a1, 0(a4)
-; RV64-NEXT: sb a2, 0(a3)
-; RV64-NEXT: ld a1, 0(a0)
-; RV64-NEXT: addi a1, a1, 3
-; RV64-NEXT: andi a1, a1, -4
-; RV64-NEXT: addi a2, a1, 4
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: lw a0, 0(a1)
-; RV64-NEXT: addi sp, sp, 80
-; RV64-NEXT: ret
- %va = alloca ptr
- call void @llvm.va_start(ptr %va)
- %1 = va_arg ptr %va, i32
- call void @llvm.va_end(ptr %va)
- ret i32 %1
-}
-
-define void @va1_caller() nounwind {
-; RV32-LABEL: va1_caller:
-; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: li a4, 2
-; RV32-NEXT: li a2, 0
-; RV32-NEXT: li a3, 0
-; RV32-NEXT: call va1 at plt
-; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-NEXT: addi sp, sp, 16
-; RV32-NEXT: ret
-;
-; RV64-LABEL: va1_caller:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: li a2, 2
-; RV64-NEXT: li a1, 0
-; RV64-NEXT: call va1 at plt
-; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: ret
- %1 = call i32 (ptr, ...) @va1(ptr undef, i64 0, i32 2)
- ret void
-}
-
-; Ensure that 2x xlen size+alignment varargs are accessed via an "aligned"
-; register pair (where the first register is even-numbered).
-
-define i64 @va2(ptr %fmt, ...) nounwind {
-; ILP32-LABEL: va2:
-; ILP32: # %bb.0:
-; ILP32-NEXT: addi sp, sp, -48
-; ILP32-NEXT: addi a0, sp, 20
-; ILP32-NEXT: sw a1, 0(a0)
-; ILP32-NEXT: addi a0, sp, 24
-; ILP32-NEXT: sw a2, 0(a0)
-; ILP32-NEXT: addi a0, sp, 28
-; ILP32-NEXT: sw a3, 0(a0)
-; ILP32-NEXT: addi a0, sp, 32
-; ILP32-NEXT: sw a4, 0(a0)
-; ILP32-NEXT: addi a0, sp, 36
-; ILP32-NEXT: sw a5, 0(a0)
-; ILP32-NEXT: addi a0, sp, 40
-; ILP32-NEXT: addi a1, sp, 12
-; ILP32-NEXT: addi a2, sp, 20
-; ILP32-NEXT: srli a3, a1, 16
-; ILP32-NEXT: addi a4, a2, 2
-; ILP32-NEXT: lui a5, 16
-; ILP32-NEXT: addi a5, a5, -1
-; ILP32-NEXT: and a5, a1, a5
-; ILP32-NEXT: srli a5, a5, 8
-; ILP32-NEXT: sb a1, 0(a2)
-; ILP32-NEXT: addi a2, a2, 1
-; ILP32-NEXT: sb a5, 0(a2)
-; ILP32-NEXT: srli a2, a3, 8
-; ILP32-NEXT: addi a5, a4, 1
-; ILP32-NEXT: sb a3, 0(a4)
-; ILP32-NEXT: sb a2, 0(a5)
-; ILP32-NEXT: lw a2, 0(a1)
-; ILP32-NEXT: sw a6, 0(a0)
-; ILP32-NEXT: addi a0, sp, 44
-; ILP32-NEXT: sw a7, 0(a0)
-; ILP32-NEXT: addi a2, a2, 7
-; ILP32-NEXT: andi a3, a2, -8
-; ILP32-NEXT: addi a2, a2, 8
-; ILP32-NEXT: sw a2, 0(a1)
-; ILP32-NEXT: lw a0, 0(a3)
-; ILP32-NEXT: addi a3, a3, 4
-; ILP32-NEXT: lw a1, 0(a3)
-; ILP32-NEXT: addi sp, sp, 48
-; ILP32-NEXT: ret
-;
-; RV32D-ILP32-LABEL: va2:
-; RV32D-ILP32: # %bb.0:
-; RV32D-ILP32-NEXT: addi sp, sp, -48
-; RV32D-ILP32-NEXT: addi a0, sp, 20
-; RV32D-ILP32-NEXT: sw a1, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 24
-; RV32D-ILP32-NEXT: sw a2, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 28
-; RV32D-ILP32-NEXT: sw a3, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 32
-; RV32D-ILP32-NEXT: sw a4, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 36
-; RV32D-ILP32-NEXT: sw a5, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 40
-; RV32D-ILP32-NEXT: addi a1, sp, 12
-; RV32D-ILP32-NEXT: addi a2, sp, 20
-; RV32D-ILP32-NEXT: srli a3, a1, 16
-; RV32D-ILP32-NEXT: addi a4, a2, 2
-; RV32D-ILP32-NEXT: lui a5, 16
-; RV32D-ILP32-NEXT: addi a5, a5, -1
-; RV32D-ILP32-NEXT: and a5, a1, a5
-; RV32D-ILP32-NEXT: srli a5, a5, 8
-; RV32D-ILP32-NEXT: sb a1, 0(a2)
-; RV32D-ILP32-NEXT: addi a2, a2, 1
-; RV32D-ILP32-NEXT: sb a5, 0(a2)
-; RV32D-ILP32-NEXT: srli a2, a3, 8
-; RV32D-ILP32-NEXT: addi a5, a4, 1
-; RV32D-ILP32-NEXT: sb a3, 0(a4)
-; RV32D-ILP32-NEXT: sb a2, 0(a5)
-; RV32D-ILP32-NEXT: lw a2, 0(a1)
-; RV32D-ILP32-NEXT: sw a6, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 44
-; RV32D-ILP32-NEXT: sw a7, 0(a0)
-; RV32D-ILP32-NEXT: addi a2, a2, 7
-; RV32D-ILP32-NEXT: andi a0, a2, -8
-; RV32D-ILP32-NEXT: fld fa5, 0(a0)
-; RV32D-ILP32-NEXT: addi a2, a2, 8
-; RV32D-ILP32-NEXT: sw a2, 0(a1)
-; RV32D-ILP32-NEXT: fsd fa5, 0(sp)
-; RV32D-ILP32-NEXT: lw a0, 0(sp)
-; RV32D-ILP32-NEXT: lw a1, 4(sp)
-; RV32D-ILP32-NEXT: addi sp, sp, 48
-; RV32D-ILP32-NEXT: ret
-;
-; RV32D-ILP32F-LABEL: va2:
-; RV32D-ILP32F: # %bb.0:
-; RV32D-ILP32F-NEXT: addi sp, sp, -48
-; RV32D-ILP32F-NEXT: addi a0, sp, 20
-; RV32D-ILP32F-NEXT: sw a1, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 24
-; RV32D-ILP32F-NEXT: sw a2, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 28
-; RV32D-ILP32F-NEXT: sw a3, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 32
-; RV32D-ILP32F-NEXT: sw a4, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 36
-; RV32D-ILP32F-NEXT: sw a5, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 40
-; RV32D-ILP32F-NEXT: addi a1, sp, 12
-; RV32D-ILP32F-NEXT: addi a2, sp, 20
-; RV32D-ILP32F-NEXT: srli a3, a1, 16
-; RV32D-ILP32F-NEXT: addi a4, a2, 2
-; RV32D-ILP32F-NEXT: lui a5, 16
-; RV32D-ILP32F-NEXT: addi a5, a5, -1
-; RV32D-ILP32F-NEXT: and a5, a1, a5
-; RV32D-ILP32F-NEXT: srli a5, a5, 8
-; RV32D-ILP32F-NEXT: sb a1, 0(a2)
-; RV32D-ILP32F-NEXT: addi a2, a2, 1
-; RV32D-ILP32F-NEXT: sb a5, 0(a2)
-; RV32D-ILP32F-NEXT: srli a2, a3, 8
-; RV32D-ILP32F-NEXT: addi a5, a4, 1
-; RV32D-ILP32F-NEXT: sb a3, 0(a4)
-; RV32D-ILP32F-NEXT: sb a2, 0(a5)
-; RV32D-ILP32F-NEXT: lw a2, 0(a1)
-; RV32D-ILP32F-NEXT: sw a6, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 44
-; RV32D-ILP32F-NEXT: sw a7, 0(a0)
-; RV32D-ILP32F-NEXT: addi a2, a2, 7
-; RV32D-ILP32F-NEXT: andi a0, a2, -8
-; RV32D-ILP32F-NEXT: fld fa5, 0(a0)
-; RV32D-ILP32F-NEXT: addi a2, a2, 8
-; RV32D-ILP32F-NEXT: sw a2, 0(a1)
-; RV32D-ILP32F-NEXT: fsd fa5, 0(sp)
-; RV32D-ILP32F-NEXT: lw a0, 0(sp)
-; RV32D-ILP32F-NEXT: lw a1, 4(sp)
-; RV32D-ILP32F-NEXT: addi sp, sp, 48
-; RV32D-ILP32F-NEXT: ret
-;
-; RV32D-ILP32D-LABEL: va2:
-; RV32D-ILP32D: # %bb.0:
-; RV32D-ILP32D-NEXT: addi sp, sp, -48
-; RV32D-ILP32D-NEXT: addi a0, sp, 20
-; RV32D-ILP32D-NEXT: sw a1, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 24
-; RV32D-ILP32D-NEXT: sw a2, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 28
-; RV32D-ILP32D-NEXT: sw a3, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 32
-; RV32D-ILP32D-NEXT: sw a4, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 36
-; RV32D-ILP32D-NEXT: sw a5, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 40
-; RV32D-ILP32D-NEXT: addi a1, sp, 12
-; RV32D-ILP32D-NEXT: addi a2, sp, 20
-; RV32D-ILP32D-NEXT: srli a3, a1, 16
-; RV32D-ILP32D-NEXT: addi a4, a2, 2
-; RV32D-ILP32D-NEXT: lui a5, 16
-; RV32D-ILP32D-NEXT: addi a5, a5, -1
-; RV32D-ILP32D-NEXT: and a5, a1, a5
-; RV32D-ILP32D-NEXT: srli a5, a5, 8
-; RV32D-ILP32D-NEXT: sb a1, 0(a2)
-; RV32D-ILP32D-NEXT: addi a2, a2, 1
-; RV32D-ILP32D-NEXT: sb a5, 0(a2)
-; RV32D-ILP32D-NEXT: srli a2, a3, 8
-; RV32D-ILP32D-NEXT: addi a5, a4, 1
-; RV32D-ILP32D-NEXT: sb a3, 0(a4)
-; RV32D-ILP32D-NEXT: sb a2, 0(a5)
-; RV32D-ILP32D-NEXT: lw a2, 0(a1)
-; RV32D-ILP32D-NEXT: sw a6, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 44
-; RV32D-ILP32D-NEXT: sw a7, 0(a0)
-; RV32D-ILP32D-NEXT: addi a2, a2, 7
-; RV32D-ILP32D-NEXT: andi a0, a2, -8
-; RV32D-ILP32D-NEXT: fld fa5, 0(a0)
-; RV32D-ILP32D-NEXT: addi a2, a2, 8
-; RV32D-ILP32D-NEXT: sw a2, 0(a1)
-; RV32D-ILP32D-NEXT: fsd fa5, 0(sp)
-; RV32D-ILP32D-NEXT: lw a0, 0(sp)
-; RV32D-ILP32D-NEXT: lw a1, 4(sp)
-; RV32D-ILP32D-NEXT: addi sp, sp, 48
-; RV32D-ILP32D-NEXT: ret
-;
-; RV64-LABEL: va2:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -80
-; RV64-NEXT: addi a0, sp, 24
-; RV64-NEXT: sd a1, 0(a0)
-; RV64-NEXT: addi a0, sp, 32
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: addi a0, sp, 40
-; RV64-NEXT: sd a3, 0(a0)
-; RV64-NEXT: addi a0, sp, 48
-; RV64-NEXT: sd a4, 0(a0)
-; RV64-NEXT: addi a0, sp, 56
-; RV64-NEXT: sd a5, 0(a0)
-; RV64-NEXT: addi a0, sp, 64
-; RV64-NEXT: sd a6, 0(a0)
-; RV64-NEXT: addi a0, sp, 72
-; RV64-NEXT: sd a7, 0(a0)
-; RV64-NEXT: addi a0, sp, 8
-; RV64-NEXT: addi a1, sp, 24
-; RV64-NEXT: srli a2, a0, 32
-; RV64-NEXT: addi a3, a1, 4
-; RV64-NEXT: srliw a4, a0, 16
-; RV64-NEXT: addi a5, a1, 2
-; RV64-NEXT: lui a6, 16
-; RV64-NEXT: addi a6, a6, -1
-; RV64-NEXT: and a7, a0, a6
-; RV64-NEXT: srliw a7, a7, 8
-; RV64-NEXT: addi t0, a1, 1
-; RV64-NEXT: sb a0, 0(a1)
-; RV64-NEXT: sb a7, 0(t0)
-; RV64-NEXT: srliw a1, a4, 8
-; RV64-NEXT: addi a7, a5, 1
-; RV64-NEXT: sb a4, 0(a5)
-; RV64-NEXT: sb a1, 0(a7)
-; RV64-NEXT: srliw a1, a2, 16
-; RV64-NEXT: addi a4, a3, 2
-; RV64-NEXT: and a5, a2, a6
-; RV64-NEXT: srliw a5, a5, 8
-; RV64-NEXT: addi a6, a3, 1
-; RV64-NEXT: sb a2, 0(a3)
-; RV64-NEXT: sb a5, 0(a6)
-; RV64-NEXT: srliw a2, a1, 8
-; RV64-NEXT: lw a3, 0(a0)
-; RV64-NEXT: addi a5, a4, 1
-; RV64-NEXT: sb a1, 0(a4)
-; RV64-NEXT: sb a2, 0(a5)
-; RV64-NEXT: addi a3, a3, 7
-; RV64-NEXT: andi a1, a3, -8
-; RV64-NEXT: slli a3, a3, 32
-; RV64-NEXT: srli a3, a3, 32
-; RV64-NEXT: addi a3, a3, 8
-; RV64-NEXT: srli a2, a3, 32
-; RV64-NEXT: addi a4, a0, 4
-; RV64-NEXT: sw a3, 0(a0)
-; RV64-NEXT: sw a2, 0(a4)
-; RV64-NEXT: slli a1, a1, 32
-; RV64-NEXT: srli a1, a1, 32
-; RV64-NEXT: ld a0, 0(a1)
-; RV64-NEXT: addi sp, sp, 80
-; RV64-NEXT: ret
- %va = alloca ptr
- call void @llvm.va_start(ptr %va)
- %argp.cur = load i32, ptr %va, align 4
- %1 = add i32 %argp.cur, 7
- %2 = and i32 %1, -8
- %argp.cur.aligned = inttoptr i32 %1 to ptr
- %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 8
- store ptr %argp.next, ptr %va, align 4
- %3 = inttoptr i32 %2 to ptr
- %4 = load double, ptr %3, align 8
- %5 = bitcast double %4 to i64
- call void @llvm.va_end(ptr %va)
- ret i64 %5
-}
-
-define i64 @va2_va_arg(ptr %fmt, ...) nounwind {
-; ILP32-LABEL: va2_va_arg:
-; ILP32: # %bb.0:
-; ILP32-NEXT: addi sp, sp, -48
-; ILP32-NEXT: addi a0, sp, 20
-; ILP32-NEXT: sw a1, 0(a0)
-; ILP32-NEXT: addi a0, sp, 24
-; ILP32-NEXT: sw a2, 0(a0)
-; ILP32-NEXT: addi a0, sp, 28
-; ILP32-NEXT: sw a3, 0(a0)
-; ILP32-NEXT: addi a0, sp, 32
-; ILP32-NEXT: sw a4, 0(a0)
-; ILP32-NEXT: addi a0, sp, 36
-; ILP32-NEXT: sw a5, 0(a0)
-; ILP32-NEXT: addi a0, sp, 40
-; ILP32-NEXT: sw a6, 0(a0)
-; ILP32-NEXT: addi a0, sp, 44
-; ILP32-NEXT: sw a7, 0(a0)
-; ILP32-NEXT: addi a0, sp, 12
-; ILP32-NEXT: addi a1, sp, 20
-; ILP32-NEXT: srli a2, a0, 16
-; ILP32-NEXT: addi a3, a1, 2
-; ILP32-NEXT: lui a4, 16
-; ILP32-NEXT: addi a4, a4, -1
-; ILP32-NEXT: and a4, a0, a4
-; ILP32-NEXT: srli a4, a4, 8
-; ILP32-NEXT: addi a5, a1, 1
-; ILP32-NEXT: sb a0, 0(a1)
-; ILP32-NEXT: sb a4, 0(a5)
-; ILP32-NEXT: srli a1, a2, 8
-; ILP32-NEXT: addi a4, a3, 1
-; ILP32-NEXT: sb a2, 0(a3)
-; ILP32-NEXT: sb a1, 0(a4)
-; ILP32-NEXT: lw a1, 0(a0)
-; ILP32-NEXT: addi a1, a1, 7
-; ILP32-NEXT: andi a1, a1, -8
-; ILP32-NEXT: addi a2, a1, 8
-; ILP32-NEXT: sw a2, 0(a0)
-; ILP32-NEXT: lw a0, 0(a1)
-; ILP32-NEXT: addi a1, a1, 4
-; ILP32-NEXT: lw a1, 0(a1)
-; ILP32-NEXT: addi sp, sp, 48
-; ILP32-NEXT: ret
-;
-; RV32D-ILP32-LABEL: va2_va_arg:
-; RV32D-ILP32: # %bb.0:
-; RV32D-ILP32-NEXT: addi sp, sp, -48
-; RV32D-ILP32-NEXT: addi a0, sp, 20
-; RV32D-ILP32-NEXT: sw a1, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 24
-; RV32D-ILP32-NEXT: sw a2, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 28
-; RV32D-ILP32-NEXT: sw a3, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 32
-; RV32D-ILP32-NEXT: sw a4, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 36
-; RV32D-ILP32-NEXT: sw a5, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 40
-; RV32D-ILP32-NEXT: sw a6, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 44
-; RV32D-ILP32-NEXT: sw a7, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 12
-; RV32D-ILP32-NEXT: addi a1, sp, 20
-; RV32D-ILP32-NEXT: srli a2, a0, 16
-; RV32D-ILP32-NEXT: addi a3, a1, 2
-; RV32D-ILP32-NEXT: lui a4, 16
-; RV32D-ILP32-NEXT: addi a4, a4, -1
-; RV32D-ILP32-NEXT: and a4, a0, a4
-; RV32D-ILP32-NEXT: srli a4, a4, 8
-; RV32D-ILP32-NEXT: addi a5, a1, 1
-; RV32D-ILP32-NEXT: sb a0, 0(a1)
-; RV32D-ILP32-NEXT: sb a4, 0(a5)
-; RV32D-ILP32-NEXT: srli a1, a2, 8
-; RV32D-ILP32-NEXT: addi a4, a3, 1
-; RV32D-ILP32-NEXT: sb a2, 0(a3)
-; RV32D-ILP32-NEXT: sb a1, 0(a4)
-; RV32D-ILP32-NEXT: lw a1, 0(a0)
-; RV32D-ILP32-NEXT: addi a1, a1, 7
-; RV32D-ILP32-NEXT: andi a1, a1, -8
-; RV32D-ILP32-NEXT: addi a2, a1, 8
-; RV32D-ILP32-NEXT: sw a2, 0(a0)
-; RV32D-ILP32-NEXT: fld fa5, 0(a1)
-; RV32D-ILP32-NEXT: fsd fa5, 0(sp)
-; RV32D-ILP32-NEXT: lw a0, 0(sp)
-; RV32D-ILP32-NEXT: lw a1, 4(sp)
-; RV32D-ILP32-NEXT: addi sp, sp, 48
-; RV32D-ILP32-NEXT: ret
-;
-; RV32D-ILP32F-LABEL: va2_va_arg:
-; RV32D-ILP32F: # %bb.0:
-; RV32D-ILP32F-NEXT: addi sp, sp, -48
-; RV32D-ILP32F-NEXT: addi a0, sp, 20
-; RV32D-ILP32F-NEXT: sw a1, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 24
-; RV32D-ILP32F-NEXT: sw a2, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 28
-; RV32D-ILP32F-NEXT: sw a3, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 32
-; RV32D-ILP32F-NEXT: sw a4, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 36
-; RV32D-ILP32F-NEXT: sw a5, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 40
-; RV32D-ILP32F-NEXT: sw a6, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 44
-; RV32D-ILP32F-NEXT: sw a7, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 12
-; RV32D-ILP32F-NEXT: addi a1, sp, 20
-; RV32D-ILP32F-NEXT: srli a2, a0, 16
-; RV32D-ILP32F-NEXT: addi a3, a1, 2
-; RV32D-ILP32F-NEXT: lui a4, 16
-; RV32D-ILP32F-NEXT: addi a4, a4, -1
-; RV32D-ILP32F-NEXT: and a4, a0, a4
-; RV32D-ILP32F-NEXT: srli a4, a4, 8
-; RV32D-ILP32F-NEXT: addi a5, a1, 1
-; RV32D-ILP32F-NEXT: sb a0, 0(a1)
-; RV32D-ILP32F-NEXT: sb a4, 0(a5)
-; RV32D-ILP32F-NEXT: srli a1, a2, 8
-; RV32D-ILP32F-NEXT: addi a4, a3, 1
-; RV32D-ILP32F-NEXT: sb a2, 0(a3)
-; RV32D-ILP32F-NEXT: sb a1, 0(a4)
-; RV32D-ILP32F-NEXT: lw a1, 0(a0)
-; RV32D-ILP32F-NEXT: addi a1, a1, 7
-; RV32D-ILP32F-NEXT: andi a1, a1, -8
-; RV32D-ILP32F-NEXT: addi a2, a1, 8
-; RV32D-ILP32F-NEXT: sw a2, 0(a0)
-; RV32D-ILP32F-NEXT: fld fa5, 0(a1)
-; RV32D-ILP32F-NEXT: fsd fa5, 0(sp)
-; RV32D-ILP32F-NEXT: lw a0, 0(sp)
-; RV32D-ILP32F-NEXT: lw a1, 4(sp)
-; RV32D-ILP32F-NEXT: addi sp, sp, 48
-; RV32D-ILP32F-NEXT: ret
-;
-; RV32D-ILP32D-LABEL: va2_va_arg:
-; RV32D-ILP32D: # %bb.0:
-; RV32D-ILP32D-NEXT: addi sp, sp, -48
-; RV32D-ILP32D-NEXT: addi a0, sp, 20
-; RV32D-ILP32D-NEXT: sw a1, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 24
-; RV32D-ILP32D-NEXT: sw a2, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 28
-; RV32D-ILP32D-NEXT: sw a3, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 32
-; RV32D-ILP32D-NEXT: sw a4, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 36
-; RV32D-ILP32D-NEXT: sw a5, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 40
-; RV32D-ILP32D-NEXT: sw a6, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 44
-; RV32D-ILP32D-NEXT: sw a7, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 12
-; RV32D-ILP32D-NEXT: addi a1, sp, 20
-; RV32D-ILP32D-NEXT: srli a2, a0, 16
-; RV32D-ILP32D-NEXT: addi a3, a1, 2
-; RV32D-ILP32D-NEXT: lui a4, 16
-; RV32D-ILP32D-NEXT: addi a4, a4, -1
-; RV32D-ILP32D-NEXT: and a4, a0, a4
-; RV32D-ILP32D-NEXT: srli a4, a4, 8
-; RV32D-ILP32D-NEXT: addi a5, a1, 1
-; RV32D-ILP32D-NEXT: sb a0, 0(a1)
-; RV32D-ILP32D-NEXT: sb a4, 0(a5)
-; RV32D-ILP32D-NEXT: srli a1, a2, 8
-; RV32D-ILP32D-NEXT: addi a4, a3, 1
-; RV32D-ILP32D-NEXT: sb a2, 0(a3)
-; RV32D-ILP32D-NEXT: sb a1, 0(a4)
-; RV32D-ILP32D-NEXT: lw a1, 0(a0)
-; RV32D-ILP32D-NEXT: addi a1, a1, 7
-; RV32D-ILP32D-NEXT: andi a1, a1, -8
-; RV32D-ILP32D-NEXT: addi a2, a1, 8
-; RV32D-ILP32D-NEXT: sw a2, 0(a0)
-; RV32D-ILP32D-NEXT: fld fa5, 0(a1)
-; RV32D-ILP32D-NEXT: fsd fa5, 0(sp)
-; RV32D-ILP32D-NEXT: lw a0, 0(sp)
-; RV32D-ILP32D-NEXT: lw a1, 4(sp)
-; RV32D-ILP32D-NEXT: addi sp, sp, 48
-; RV32D-ILP32D-NEXT: ret
-;
-; RV64-LABEL: va2_va_arg:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -80
-; RV64-NEXT: addi a0, sp, 24
-; RV64-NEXT: sd a1, 0(a0)
-; RV64-NEXT: addi a0, sp, 32
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: addi a0, sp, 40
-; RV64-NEXT: sd a3, 0(a0)
-; RV64-NEXT: addi a0, sp, 48
-; RV64-NEXT: sd a4, 0(a0)
-; RV64-NEXT: addi a0, sp, 56
-; RV64-NEXT: sd a5, 0(a0)
-; RV64-NEXT: addi a0, sp, 64
-; RV64-NEXT: sd a6, 0(a0)
-; RV64-NEXT: addi a0, sp, 72
-; RV64-NEXT: sd a7, 0(a0)
-; RV64-NEXT: addi a0, sp, 8
-; RV64-NEXT: addi a1, sp, 24
-; RV64-NEXT: srli a2, a0, 32
-; RV64-NEXT: addi a3, a1, 4
-; RV64-NEXT: srliw a4, a0, 16
-; RV64-NEXT: addi a5, a1, 2
-; RV64-NEXT: lui a6, 16
-; RV64-NEXT: addi a6, a6, -1
-; RV64-NEXT: and a7, a0, a6
-; RV64-NEXT: srliw a7, a7, 8
-; RV64-NEXT: addi t0, a1, 1
-; RV64-NEXT: sb a0, 0(a1)
-; RV64-NEXT: sb a7, 0(t0)
-; RV64-NEXT: srliw a1, a4, 8
-; RV64-NEXT: addi a7, a5, 1
-; RV64-NEXT: sb a4, 0(a5)
-; RV64-NEXT: sb a1, 0(a7)
-; RV64-NEXT: srliw a1, a2, 16
-; RV64-NEXT: addi a4, a3, 2
-; RV64-NEXT: and a5, a2, a6
-; RV64-NEXT: srliw a5, a5, 8
-; RV64-NEXT: addi a6, a3, 1
-; RV64-NEXT: sb a2, 0(a3)
-; RV64-NEXT: sb a5, 0(a6)
-; RV64-NEXT: srliw a2, a1, 8
-; RV64-NEXT: addi a3, a4, 1
-; RV64-NEXT: sb a1, 0(a4)
-; RV64-NEXT: sb a2, 0(a3)
-; RV64-NEXT: ld a1, 0(a0)
-; RV64-NEXT: addi a1, a1, 7
-; RV64-NEXT: andi a1, a1, -8
-; RV64-NEXT: addi a2, a1, 8
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: ld a0, 0(a1)
-; RV64-NEXT: addi sp, sp, 80
-; RV64-NEXT: ret
- %va = alloca ptr
- call void @llvm.va_start(ptr %va)
- %1 = va_arg ptr %va, double
- call void @llvm.va_end(ptr %va)
- %2 = bitcast double %1 to i64
- ret i64 %2
-}
-
-define void @va2_caller() nounwind {
-; RV32-LABEL: va2_caller:
-; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: li a1, 1
-; RV32-NEXT: call va2 at plt
-; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-NEXT: addi sp, sp, 16
-; RV32-NEXT: ret
-;
-; RV64-LABEL: va2_caller:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: li a1, 1
-; RV64-NEXT: call va2 at plt
-; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: ret
- %1 = call i64 (ptr, ...) @va2(ptr undef, i32 1)
- ret void
-}
-
-; On RV32, Ensure a named 2*xlen argument is passed in a1 and a2, while the
-; vararg double is passed in a4 and a5 (rather than a3 and a4)
-
-define i64 @va3(i32 %a, i64 %b, ...) nounwind {
-; ILP32-LABEL: va3:
-; ILP32: # %bb.0:
-; ILP32-NEXT: addi sp, sp, -32
-; ILP32-NEXT: addi a0, sp, 12
-; ILP32-NEXT: sw a3, 0(a0)
-; ILP32-NEXT: addi a0, sp, 16
-; ILP32-NEXT: sw a4, 0(a0)
-; ILP32-NEXT: addi a0, sp, 20
-; ILP32-NEXT: sw a5, 0(a0)
-; ILP32-NEXT: addi a0, sp, 4
-; ILP32-NEXT: addi a3, sp, 12
-; ILP32-NEXT: lui a4, 16
-; ILP32-NEXT: addi a4, a4, -1
-; ILP32-NEXT: and a4, a0, a4
-; ILP32-NEXT: srli a4, a4, 8
-; ILP32-NEXT: addi a5, a3, 1
-; ILP32-NEXT: sb a4, 0(a5)
-; ILP32-NEXT: addi a4, sp, 24
-; ILP32-NEXT: srli a5, a0, 16
-; ILP32-NEXT: sb a0, 0(a3)
-; ILP32-NEXT: addi a3, a3, 2
-; ILP32-NEXT: sb a5, 0(a3)
-; ILP32-NEXT: srli a5, a5, 8
-; ILP32-NEXT: addi a3, a3, 1
-; ILP32-NEXT: sb a5, 0(a3)
-; ILP32-NEXT: lw a3, 0(a0)
-; ILP32-NEXT: sw a6, 0(a4)
-; ILP32-NEXT: addi a4, sp, 28
-; ILP32-NEXT: sw a7, 0(a4)
-; ILP32-NEXT: addi a3, a3, 7
-; ILP32-NEXT: andi a4, a3, -8
-; ILP32-NEXT: addi a3, a3, 8
-; ILP32-NEXT: sw a3, 0(a0)
-; ILP32-NEXT: lw a3, 0(a4)
-; ILP32-NEXT: addi a4, a4, 4
-; ILP32-NEXT: lw a4, 0(a4)
-; ILP32-NEXT: add a0, a1, a3
-; ILP32-NEXT: sltu a1, a0, a3
-; ILP32-NEXT: add a2, a2, a4
-; ILP32-NEXT: add a1, a2, a1
-; ILP32-NEXT: addi sp, sp, 32
-; ILP32-NEXT: ret
-;
-; RV32D-ILP32-LABEL: va3:
-; RV32D-ILP32: # %bb.0:
-; RV32D-ILP32-NEXT: addi sp, sp, -48
-; RV32D-ILP32-NEXT: addi a0, sp, 28
-; RV32D-ILP32-NEXT: sw a3, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 32
-; RV32D-ILP32-NEXT: sw a4, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 36
-; RV32D-ILP32-NEXT: sw a5, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 20
-; RV32D-ILP32-NEXT: addi a3, sp, 28
-; RV32D-ILP32-NEXT: lui a4, 16
-; RV32D-ILP32-NEXT: addi a4, a4, -1
-; RV32D-ILP32-NEXT: and a4, a0, a4
-; RV32D-ILP32-NEXT: srli a4, a4, 8
-; RV32D-ILP32-NEXT: addi a5, a3, 1
-; RV32D-ILP32-NEXT: sb a4, 0(a5)
-; RV32D-ILP32-NEXT: addi a4, sp, 40
-; RV32D-ILP32-NEXT: srli a5, a0, 16
-; RV32D-ILP32-NEXT: sb a0, 0(a3)
-; RV32D-ILP32-NEXT: addi a3, a3, 2
-; RV32D-ILP32-NEXT: sb a5, 0(a3)
-; RV32D-ILP32-NEXT: srli a5, a5, 8
-; RV32D-ILP32-NEXT: addi a3, a3, 1
-; RV32D-ILP32-NEXT: sb a5, 0(a3)
-; RV32D-ILP32-NEXT: lw a3, 0(a0)
-; RV32D-ILP32-NEXT: sw a6, 0(a4)
-; RV32D-ILP32-NEXT: addi a4, sp, 44
-; RV32D-ILP32-NEXT: sw a7, 0(a4)
-; RV32D-ILP32-NEXT: addi a3, a3, 7
-; RV32D-ILP32-NEXT: andi a4, a3, -8
-; RV32D-ILP32-NEXT: fld fa5, 0(a4)
-; RV32D-ILP32-NEXT: addi a3, a3, 8
-; RV32D-ILP32-NEXT: sw a3, 0(a0)
-; RV32D-ILP32-NEXT: fsd fa5, 8(sp)
-; RV32D-ILP32-NEXT: lw a3, 8(sp)
-; RV32D-ILP32-NEXT: lw a4, 12(sp)
-; RV32D-ILP32-NEXT: add a0, a1, a3
-; RV32D-ILP32-NEXT: sltu a1, a0, a3
-; RV32D-ILP32-NEXT: add a2, a2, a4
-; RV32D-ILP32-NEXT: add a1, a2, a1
-; RV32D-ILP32-NEXT: addi sp, sp, 48
-; RV32D-ILP32-NEXT: ret
-;
-; RV32D-ILP32F-LABEL: va3:
-; RV32D-ILP32F: # %bb.0:
-; RV32D-ILP32F-NEXT: addi sp, sp, -48
-; RV32D-ILP32F-NEXT: addi a0, sp, 28
-; RV32D-ILP32F-NEXT: sw a3, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 32
-; RV32D-ILP32F-NEXT: sw a4, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 36
-; RV32D-ILP32F-NEXT: sw a5, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 20
-; RV32D-ILP32F-NEXT: addi a3, sp, 28
-; RV32D-ILP32F-NEXT: lui a4, 16
-; RV32D-ILP32F-NEXT: addi a4, a4, -1
-; RV32D-ILP32F-NEXT: and a4, a0, a4
-; RV32D-ILP32F-NEXT: srli a4, a4, 8
-; RV32D-ILP32F-NEXT: addi a5, a3, 1
-; RV32D-ILP32F-NEXT: sb a4, 0(a5)
-; RV32D-ILP32F-NEXT: addi a4, sp, 40
-; RV32D-ILP32F-NEXT: srli a5, a0, 16
-; RV32D-ILP32F-NEXT: sb a0, 0(a3)
-; RV32D-ILP32F-NEXT: addi a3, a3, 2
-; RV32D-ILP32F-NEXT: sb a5, 0(a3)
-; RV32D-ILP32F-NEXT: srli a5, a5, 8
-; RV32D-ILP32F-NEXT: addi a3, a3, 1
-; RV32D-ILP32F-NEXT: sb a5, 0(a3)
-; RV32D-ILP32F-NEXT: lw a3, 0(a0)
-; RV32D-ILP32F-NEXT: sw a6, 0(a4)
-; RV32D-ILP32F-NEXT: addi a4, sp, 44
-; RV32D-ILP32F-NEXT: sw a7, 0(a4)
-; RV32D-ILP32F-NEXT: addi a3, a3, 7
-; RV32D-ILP32F-NEXT: andi a4, a3, -8
-; RV32D-ILP32F-NEXT: fld fa5, 0(a4)
-; RV32D-ILP32F-NEXT: addi a3, a3, 8
-; RV32D-ILP32F-NEXT: sw a3, 0(a0)
-; RV32D-ILP32F-NEXT: fsd fa5, 8(sp)
-; RV32D-ILP32F-NEXT: lw a3, 8(sp)
-; RV32D-ILP32F-NEXT: lw a4, 12(sp)
-; RV32D-ILP32F-NEXT: add a0, a1, a3
-; RV32D-ILP32F-NEXT: sltu a1, a0, a3
-; RV32D-ILP32F-NEXT: add a2, a2, a4
-; RV32D-ILP32F-NEXT: add a1, a2, a1
-; RV32D-ILP32F-NEXT: addi sp, sp, 48
-; RV32D-ILP32F-NEXT: ret
-;
-; RV32D-ILP32D-LABEL: va3:
-; RV32D-ILP32D: # %bb.0:
-; RV32D-ILP32D-NEXT: addi sp, sp, -48
-; RV32D-ILP32D-NEXT: addi a0, sp, 28
-; RV32D-ILP32D-NEXT: sw a3, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 32
-; RV32D-ILP32D-NEXT: sw a4, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 36
-; RV32D-ILP32D-NEXT: sw a5, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 20
-; RV32D-ILP32D-NEXT: addi a3, sp, 28
-; RV32D-ILP32D-NEXT: lui a4, 16
-; RV32D-ILP32D-NEXT: addi a4, a4, -1
-; RV32D-ILP32D-NEXT: and a4, a0, a4
-; RV32D-ILP32D-NEXT: srli a4, a4, 8
-; RV32D-ILP32D-NEXT: addi a5, a3, 1
-; RV32D-ILP32D-NEXT: sb a4, 0(a5)
-; RV32D-ILP32D-NEXT: addi a4, sp, 40
-; RV32D-ILP32D-NEXT: srli a5, a0, 16
-; RV32D-ILP32D-NEXT: sb a0, 0(a3)
-; RV32D-ILP32D-NEXT: addi a3, a3, 2
-; RV32D-ILP32D-NEXT: sb a5, 0(a3)
-; RV32D-ILP32D-NEXT: srli a5, a5, 8
-; RV32D-ILP32D-NEXT: addi a3, a3, 1
-; RV32D-ILP32D-NEXT: sb a5, 0(a3)
-; RV32D-ILP32D-NEXT: lw a3, 0(a0)
-; RV32D-ILP32D-NEXT: sw a6, 0(a4)
-; RV32D-ILP32D-NEXT: addi a4, sp, 44
-; RV32D-ILP32D-NEXT: sw a7, 0(a4)
-; RV32D-ILP32D-NEXT: addi a3, a3, 7
-; RV32D-ILP32D-NEXT: andi a4, a3, -8
-; RV32D-ILP32D-NEXT: fld fa5, 0(a4)
-; RV32D-ILP32D-NEXT: addi a3, a3, 8
-; RV32D-ILP32D-NEXT: sw a3, 0(a0)
-; RV32D-ILP32D-NEXT: fsd fa5, 8(sp)
-; RV32D-ILP32D-NEXT: lw a3, 8(sp)
-; RV32D-ILP32D-NEXT: lw a4, 12(sp)
-; RV32D-ILP32D-NEXT: add a0, a1, a3
-; RV32D-ILP32D-NEXT: sltu a1, a0, a3
-; RV32D-ILP32D-NEXT: add a2, a2, a4
-; RV32D-ILP32D-NEXT: add a1, a2, a1
-; RV32D-ILP32D-NEXT: addi sp, sp, 48
-; RV32D-ILP32D-NEXT: ret
-;
-; RV64-LABEL: va3:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -64
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: addi a0, sp, 24
-; RV64-NEXT: sd a3, 0(a0)
-; RV64-NEXT: addi a0, sp, 32
-; RV64-NEXT: sd a4, 0(a0)
-; RV64-NEXT: addi a0, sp, 40
-; RV64-NEXT: sd a5, 0(a0)
-; RV64-NEXT: addi a0, sp, 48
-; RV64-NEXT: sd a6, 0(a0)
-; RV64-NEXT: addi a0, sp, 56
-; RV64-NEXT: sd a7, 0(a0)
-; RV64-NEXT: addi a0, sp, 8
-; RV64-NEXT: addi a2, sp, 16
-; RV64-NEXT: srli a3, a0, 32
-; RV64-NEXT: addi a4, a2, 4
-; RV64-NEXT: srliw a5, a0, 16
-; RV64-NEXT: addi a6, a2, 2
-; RV64-NEXT: lui a7, 16
-; RV64-NEXT: addi a7, a7, -1
-; RV64-NEXT: and t0, a0, a7
-; RV64-NEXT: srliw t0, t0, 8
-; RV64-NEXT: addi t1, a2, 1
-; RV64-NEXT: sb a0, 0(a2)
-; RV64-NEXT: sb t0, 0(t1)
-; RV64-NEXT: srliw a2, a5, 8
-; RV64-NEXT: addi t0, a6, 1
-; RV64-NEXT: sb a5, 0(a6)
-; RV64-NEXT: sb a2, 0(t0)
-; RV64-NEXT: srliw a2, a3, 16
-; RV64-NEXT: addi a5, a4, 2
-; RV64-NEXT: and a6, a3, a7
-; RV64-NEXT: srliw a6, a6, 8
-; RV64-NEXT: addi a7, a4, 1
-; RV64-NEXT: sb a3, 0(a4)
-; RV64-NEXT: sb a6, 0(a7)
-; RV64-NEXT: srliw a3, a2, 8
-; RV64-NEXT: lw a4, 0(a0)
-; RV64-NEXT: addi a6, a5, 1
-; RV64-NEXT: sb a2, 0(a5)
-; RV64-NEXT: sb a3, 0(a6)
-; RV64-NEXT: addi a4, a4, 7
-; RV64-NEXT: andi a2, a4, -8
-; RV64-NEXT: slli a4, a4, 32
-; RV64-NEXT: srli a4, a4, 32
-; RV64-NEXT: addi a4, a4, 8
-; RV64-NEXT: srli a3, a4, 32
-; RV64-NEXT: addi a5, a0, 4
-; RV64-NEXT: sw a4, 0(a0)
-; RV64-NEXT: sw a3, 0(a5)
-; RV64-NEXT: slli a2, a2, 32
-; RV64-NEXT: srli a2, a2, 32
-; RV64-NEXT: ld a0, 0(a2)
-; RV64-NEXT: add a0, a1, a0
-; RV64-NEXT: addi sp, sp, 64
-; RV64-NEXT: ret
- %va = alloca ptr
- call void @llvm.va_start(ptr %va)
- %argp.cur = load i32, ptr %va, align 4
- %1 = add i32 %argp.cur, 7
- %2 = and i32 %1, -8
- %argp.cur.aligned = inttoptr i32 %1 to ptr
- %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 8
- store ptr %argp.next, ptr %va, align 4
- %3 = inttoptr i32 %2 to ptr
- %4 = load double, ptr %3, align 8
- call void @llvm.va_end(ptr %va)
- %5 = bitcast double %4 to i64
- %6 = add i64 %b, %5
- ret i64 %6
-}
-
-define i64 @va3_va_arg(i32 %a, i64 %b, ...) nounwind {
-; ILP32-LABEL: va3_va_arg:
-; ILP32: # %bb.0:
-; ILP32-NEXT: addi sp, sp, -32
-; ILP32-NEXT: addi a0, sp, 12
-; ILP32-NEXT: sw a3, 0(a0)
-; ILP32-NEXT: addi a0, sp, 16
-; ILP32-NEXT: sw a4, 0(a0)
-; ILP32-NEXT: addi a0, sp, 20
-; ILP32-NEXT: sw a5, 0(a0)
-; ILP32-NEXT: addi a0, sp, 24
-; ILP32-NEXT: sw a6, 0(a0)
-; ILP32-NEXT: addi a0, sp, 28
-; ILP32-NEXT: sw a7, 0(a0)
-; ILP32-NEXT: addi a0, sp, 4
-; ILP32-NEXT: addi a3, sp, 12
-; ILP32-NEXT: srli a4, a0, 16
-; ILP32-NEXT: addi a5, a3, 2
-; ILP32-NEXT: lui a6, 16
-; ILP32-NEXT: addi a6, a6, -1
-; ILP32-NEXT: and a6, a0, a6
-; ILP32-NEXT: srli a6, a6, 8
-; ILP32-NEXT: addi a7, a3, 1
-; ILP32-NEXT: sb a0, 0(a3)
-; ILP32-NEXT: sb a6, 0(a7)
-; ILP32-NEXT: srli a3, a4, 8
-; ILP32-NEXT: addi a6, a5, 1
-; ILP32-NEXT: sb a4, 0(a5)
-; ILP32-NEXT: sb a3, 0(a6)
-; ILP32-NEXT: lw a3, 0(a0)
-; ILP32-NEXT: addi a3, a3, 7
-; ILP32-NEXT: andi a3, a3, -8
-; ILP32-NEXT: addi a4, a3, 8
-; ILP32-NEXT: sw a4, 0(a0)
-; ILP32-NEXT: lw a4, 0(a3)
-; ILP32-NEXT: addi a3, a3, 4
-; ILP32-NEXT: lw a3, 0(a3)
-; ILP32-NEXT: add a0, a1, a4
-; ILP32-NEXT: sltu a1, a0, a4
-; ILP32-NEXT: add a2, a2, a3
-; ILP32-NEXT: add a1, a2, a1
-; ILP32-NEXT: addi sp, sp, 32
-; ILP32-NEXT: ret
-;
-; RV32D-ILP32-LABEL: va3_va_arg:
-; RV32D-ILP32: # %bb.0:
-; RV32D-ILP32-NEXT: addi sp, sp, -48
-; RV32D-ILP32-NEXT: addi a0, sp, 28
-; RV32D-ILP32-NEXT: sw a3, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 32
-; RV32D-ILP32-NEXT: sw a4, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 36
-; RV32D-ILP32-NEXT: sw a5, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 40
-; RV32D-ILP32-NEXT: sw a6, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 44
-; RV32D-ILP32-NEXT: sw a7, 0(a0)
-; RV32D-ILP32-NEXT: addi a0, sp, 20
-; RV32D-ILP32-NEXT: addi a3, sp, 28
-; RV32D-ILP32-NEXT: srli a4, a0, 16
-; RV32D-ILP32-NEXT: addi a5, a3, 2
-; RV32D-ILP32-NEXT: lui a6, 16
-; RV32D-ILP32-NEXT: addi a6, a6, -1
-; RV32D-ILP32-NEXT: and a6, a0, a6
-; RV32D-ILP32-NEXT: srli a6, a6, 8
-; RV32D-ILP32-NEXT: addi a7, a3, 1
-; RV32D-ILP32-NEXT: sb a0, 0(a3)
-; RV32D-ILP32-NEXT: sb a6, 0(a7)
-; RV32D-ILP32-NEXT: srli a3, a4, 8
-; RV32D-ILP32-NEXT: addi a6, a5, 1
-; RV32D-ILP32-NEXT: sb a4, 0(a5)
-; RV32D-ILP32-NEXT: sb a3, 0(a6)
-; RV32D-ILP32-NEXT: lw a3, 0(a0)
-; RV32D-ILP32-NEXT: addi a3, a3, 7
-; RV32D-ILP32-NEXT: andi a3, a3, -8
-; RV32D-ILP32-NEXT: addi a4, a3, 8
-; RV32D-ILP32-NEXT: sw a4, 0(a0)
-; RV32D-ILP32-NEXT: fld fa5, 0(a3)
-; RV32D-ILP32-NEXT: fsd fa5, 8(sp)
-; RV32D-ILP32-NEXT: lw a3, 8(sp)
-; RV32D-ILP32-NEXT: lw a4, 12(sp)
-; RV32D-ILP32-NEXT: add a0, a1, a3
-; RV32D-ILP32-NEXT: sltu a1, a0, a3
-; RV32D-ILP32-NEXT: add a2, a2, a4
-; RV32D-ILP32-NEXT: add a1, a2, a1
-; RV32D-ILP32-NEXT: addi sp, sp, 48
-; RV32D-ILP32-NEXT: ret
-;
-; RV32D-ILP32F-LABEL: va3_va_arg:
-; RV32D-ILP32F: # %bb.0:
-; RV32D-ILP32F-NEXT: addi sp, sp, -48
-; RV32D-ILP32F-NEXT: addi a0, sp, 28
-; RV32D-ILP32F-NEXT: sw a3, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 32
-; RV32D-ILP32F-NEXT: sw a4, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 36
-; RV32D-ILP32F-NEXT: sw a5, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 40
-; RV32D-ILP32F-NEXT: sw a6, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 44
-; RV32D-ILP32F-NEXT: sw a7, 0(a0)
-; RV32D-ILP32F-NEXT: addi a0, sp, 20
-; RV32D-ILP32F-NEXT: addi a3, sp, 28
-; RV32D-ILP32F-NEXT: srli a4, a0, 16
-; RV32D-ILP32F-NEXT: addi a5, a3, 2
-; RV32D-ILP32F-NEXT: lui a6, 16
-; RV32D-ILP32F-NEXT: addi a6, a6, -1
-; RV32D-ILP32F-NEXT: and a6, a0, a6
-; RV32D-ILP32F-NEXT: srli a6, a6, 8
-; RV32D-ILP32F-NEXT: addi a7, a3, 1
-; RV32D-ILP32F-NEXT: sb a0, 0(a3)
-; RV32D-ILP32F-NEXT: sb a6, 0(a7)
-; RV32D-ILP32F-NEXT: srli a3, a4, 8
-; RV32D-ILP32F-NEXT: addi a6, a5, 1
-; RV32D-ILP32F-NEXT: sb a4, 0(a5)
-; RV32D-ILP32F-NEXT: sb a3, 0(a6)
-; RV32D-ILP32F-NEXT: lw a3, 0(a0)
-; RV32D-ILP32F-NEXT: addi a3, a3, 7
-; RV32D-ILP32F-NEXT: andi a3, a3, -8
-; RV32D-ILP32F-NEXT: addi a4, a3, 8
-; RV32D-ILP32F-NEXT: sw a4, 0(a0)
-; RV32D-ILP32F-NEXT: fld fa5, 0(a3)
-; RV32D-ILP32F-NEXT: fsd fa5, 8(sp)
-; RV32D-ILP32F-NEXT: lw a3, 8(sp)
-; RV32D-ILP32F-NEXT: lw a4, 12(sp)
-; RV32D-ILP32F-NEXT: add a0, a1, a3
-; RV32D-ILP32F-NEXT: sltu a1, a0, a3
-; RV32D-ILP32F-NEXT: add a2, a2, a4
-; RV32D-ILP32F-NEXT: add a1, a2, a1
-; RV32D-ILP32F-NEXT: addi sp, sp, 48
-; RV32D-ILP32F-NEXT: ret
-;
-; RV32D-ILP32D-LABEL: va3_va_arg:
-; RV32D-ILP32D: # %bb.0:
-; RV32D-ILP32D-NEXT: addi sp, sp, -48
-; RV32D-ILP32D-NEXT: addi a0, sp, 28
-; RV32D-ILP32D-NEXT: sw a3, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 32
-; RV32D-ILP32D-NEXT: sw a4, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 36
-; RV32D-ILP32D-NEXT: sw a5, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 40
-; RV32D-ILP32D-NEXT: sw a6, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 44
-; RV32D-ILP32D-NEXT: sw a7, 0(a0)
-; RV32D-ILP32D-NEXT: addi a0, sp, 20
-; RV32D-ILP32D-NEXT: addi a3, sp, 28
-; RV32D-ILP32D-NEXT: srli a4, a0, 16
-; RV32D-ILP32D-NEXT: addi a5, a3, 2
-; RV32D-ILP32D-NEXT: lui a6, 16
-; RV32D-ILP32D-NEXT: addi a6, a6, -1
-; RV32D-ILP32D-NEXT: and a6, a0, a6
-; RV32D-ILP32D-NEXT: srli a6, a6, 8
-; RV32D-ILP32D-NEXT: addi a7, a3, 1
-; RV32D-ILP32D-NEXT: sb a0, 0(a3)
-; RV32D-ILP32D-NEXT: sb a6, 0(a7)
-; RV32D-ILP32D-NEXT: srli a3, a4, 8
-; RV32D-ILP32D-NEXT: addi a6, a5, 1
-; RV32D-ILP32D-NEXT: sb a4, 0(a5)
-; RV32D-ILP32D-NEXT: sb a3, 0(a6)
-; RV32D-ILP32D-NEXT: lw a3, 0(a0)
-; RV32D-ILP32D-NEXT: addi a3, a3, 7
-; RV32D-ILP32D-NEXT: andi a3, a3, -8
-; RV32D-ILP32D-NEXT: addi a4, a3, 8
-; RV32D-ILP32D-NEXT: sw a4, 0(a0)
-; RV32D-ILP32D-NEXT: fld fa5, 0(a3)
-; RV32D-ILP32D-NEXT: fsd fa5, 8(sp)
-; RV32D-ILP32D-NEXT: lw a3, 8(sp)
-; RV32D-ILP32D-NEXT: lw a4, 12(sp)
-; RV32D-ILP32D-NEXT: add a0, a1, a3
-; RV32D-ILP32D-NEXT: sltu a1, a0, a3
-; RV32D-ILP32D-NEXT: add a2, a2, a4
-; RV32D-ILP32D-NEXT: add a1, a2, a1
-; RV32D-ILP32D-NEXT: addi sp, sp, 48
-; RV32D-ILP32D-NEXT: ret
-;
-; RV64-LABEL: va3_va_arg:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -64
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: addi a0, sp, 24
-; RV64-NEXT: sd a3, 0(a0)
-; RV64-NEXT: addi a0, sp, 32
-; RV64-NEXT: sd a4, 0(a0)
-; RV64-NEXT: addi a0, sp, 40
-; RV64-NEXT: sd a5, 0(a0)
-; RV64-NEXT: addi a0, sp, 48
-; RV64-NEXT: sd a6, 0(a0)
-; RV64-NEXT: addi a0, sp, 56
-; RV64-NEXT: sd a7, 0(a0)
-; RV64-NEXT: addi a0, sp, 8
-; RV64-NEXT: addi a2, sp, 16
-; RV64-NEXT: srli a3, a0, 32
-; RV64-NEXT: addi a4, a2, 4
-; RV64-NEXT: srliw a5, a0, 16
-; RV64-NEXT: addi a6, a2, 2
-; RV64-NEXT: lui a7, 16
-; RV64-NEXT: addi a7, a7, -1
-; RV64-NEXT: and t0, a0, a7
-; RV64-NEXT: srliw t0, t0, 8
-; RV64-NEXT: addi t1, a2, 1
-; RV64-NEXT: sb a0, 0(a2)
-; RV64-NEXT: sb t0, 0(t1)
-; RV64-NEXT: srliw a2, a5, 8
-; RV64-NEXT: addi t0, a6, 1
-; RV64-NEXT: sb a5, 0(a6)
-; RV64-NEXT: sb a2, 0(t0)
-; RV64-NEXT: srliw a2, a3, 16
-; RV64-NEXT: addi a5, a4, 2
-; RV64-NEXT: and a6, a3, a7
-; RV64-NEXT: srliw a6, a6, 8
-; RV64-NEXT: addi a7, a4, 1
-; RV64-NEXT: sb a3, 0(a4)
-; RV64-NEXT: sb a6, 0(a7)
-; RV64-NEXT: srliw a3, a2, 8
-; RV64-NEXT: addi a4, a5, 1
-; RV64-NEXT: sb a2, 0(a5)
-; RV64-NEXT: sb a3, 0(a4)
-; RV64-NEXT: ld a2, 0(a0)
-; RV64-NEXT: addi a2, a2, 7
-; RV64-NEXT: andi a2, a2, -8
-; RV64-NEXT: addi a3, a2, 8
-; RV64-NEXT: sd a3, 0(a0)
-; RV64-NEXT: ld a0, 0(a2)
-; RV64-NEXT: add a0, a1, a0
-; RV64-NEXT: addi sp, sp, 64
-; RV64-NEXT: ret
- %va = alloca ptr
- call void @llvm.va_start(ptr %va)
- %1 = va_arg ptr %va, double
- call void @llvm.va_end(ptr %va)
- %2 = bitcast double %1 to i64
- %3 = add i64 %b, %2
- ret i64 %3
-}
-
-define void @va3_caller() nounwind {
-; RV32-LABEL: va3_caller:
-; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-NEXT: lui a0, 5
-; RV32-NEXT: addi a3, a0, -480
-; RV32-NEXT: li a0, 2
-; RV32-NEXT: li a1, 1111
-; RV32-NEXT: li a2, 0
-; RV32-NEXT: call va3 at plt
-; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32-NEXT: addi sp, sp, 16
-; RV32-NEXT: ret
-;
-; RV64-LABEL: va3_caller:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: lui a0, 5
-; RV64-NEXT: addiw a2, a0, -480
-; RV64-NEXT: li a0, 2
-; RV64-NEXT: li a1, 1111
-; RV64-NEXT: call va3 at plt
-; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: ret
- %1 = call i64 (i32, i64, ...) @va3(i32 2, i64 1111, i32 20000)
- ret void
-}
-
-declare void @llvm.va_copy(ptr, ptr)
-
-define i32 @va4_va_copy(i32 %argno, ...) nounwind {
-; RV32-LABEL: va4_va_copy:
-; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -64
-; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32-NEXT: addi a0, sp, 36
-; RV32-NEXT: sw a1, 0(a0)
-; RV32-NEXT: addi a0, sp, 40
-; RV32-NEXT: sw a2, 0(a0)
-; RV32-NEXT: addi a0, sp, 44
-; RV32-NEXT: sw a3, 0(a0)
-; RV32-NEXT: addi a0, sp, 48
-; RV32-NEXT: sw a4, 0(a0)
-; RV32-NEXT: addi a0, sp, 52
-; RV32-NEXT: sw a5, 0(a0)
-; RV32-NEXT: addi a0, sp, 56
-; RV32-NEXT: sw a6, 0(a0)
-; RV32-NEXT: addi a0, sp, 60
-; RV32-NEXT: sw a7, 0(a0)
-; RV32-NEXT: addi s0, sp, 16
-; RV32-NEXT: addi a0, sp, 36
-; RV32-NEXT: srli a1, s0, 16
-; RV32-NEXT: addi a2, a0, 2
-; RV32-NEXT: lui a3, 16
-; RV32-NEXT: addi a3, a3, -1
-; RV32-NEXT: and a3, s0, a3
-; RV32-NEXT: srli a3, a3, 8
-; RV32-NEXT: addi a4, a0, 1
-; RV32-NEXT: sb s0, 0(a0)
-; RV32-NEXT: sb a3, 0(a4)
-; RV32-NEXT: srli a0, a1, 8
-; RV32-NEXT: addi a3, a2, 1
-; RV32-NEXT: sb a1, 0(a2)
-; RV32-NEXT: sb a0, 0(a3)
-; RV32-NEXT: lw a0, 0(s0)
-; RV32-NEXT: addi a0, a0, 3
-; RV32-NEXT: andi a0, a0, -4
-; RV32-NEXT: addi a1, a0, 4
-; RV32-NEXT: sw a1, 0(s0)
-; RV32-NEXT: lw a1, 0(s0)
-; RV32-NEXT: addi a2, sp, 12
-; RV32-NEXT: lw s1, 0(a0)
-; RV32-NEXT: sw a2, 0(a1)
-; RV32-NEXT: lw a0, 0(a2)
-; RV32-NEXT: call notdead at plt
-; RV32-NEXT: lw a0, 0(s0)
-; RV32-NEXT: addi a0, a0, 3
-; RV32-NEXT: andi a0, a0, -4
-; RV32-NEXT: addi a1, a0, 4
-; RV32-NEXT: sw a1, 0(s0)
-; RV32-NEXT: lw a1, 0(s0)
-; RV32-NEXT: lw a0, 0(a0)
-; RV32-NEXT: addi a1, a1, 3
-; RV32-NEXT: andi a1, a1, -4
-; RV32-NEXT: addi a2, a1, 4
-; RV32-NEXT: sw a2, 0(s0)
-; RV32-NEXT: lw a2, 0(s0)
-; RV32-NEXT: lw a1, 0(a1)
-; RV32-NEXT: addi a2, a2, 3
-; RV32-NEXT: andi a2, a2, -4
-; RV32-NEXT: addi a3, a2, 4
-; RV32-NEXT: sw a3, 0(s0)
-; RV32-NEXT: lw a2, 0(a2)
-; RV32-NEXT: add a0, a0, s1
-; RV32-NEXT: add a1, a1, a2
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32-NEXT: addi sp, sp, 64
-; RV32-NEXT: ret
-;
-; RV64-LABEL: va4_va_copy:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -112
-; RV64-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64-NEXT: addi a0, sp, 56
-; RV64-NEXT: sd a1, 0(a0)
-; RV64-NEXT: addi a0, sp, 64
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: addi a0, sp, 72
-; RV64-NEXT: sd a3, 0(a0)
-; RV64-NEXT: addi a0, sp, 80
-; RV64-NEXT: sd a4, 0(a0)
-; RV64-NEXT: addi a0, sp, 88
-; RV64-NEXT: sd a5, 0(a0)
-; RV64-NEXT: addi a0, sp, 96
-; RV64-NEXT: sd a6, 0(a0)
-; RV64-NEXT: addi a0, sp, 104
-; RV64-NEXT: sd a7, 0(a0)
-; RV64-NEXT: addi s0, sp, 16
-; RV64-NEXT: addi a0, sp, 56
-; RV64-NEXT: srli a1, s0, 32
-; RV64-NEXT: addi a2, a0, 4
-; RV64-NEXT: srliw a3, s0, 16
-; RV64-NEXT: addi a4, a0, 2
-; RV64-NEXT: lui a5, 16
-; RV64-NEXT: addi a5, a5, -1
-; RV64-NEXT: and a6, s0, a5
-; RV64-NEXT: srliw a6, a6, 8
-; RV64-NEXT: addi a7, a0, 1
-; RV64-NEXT: sb s0, 0(a0)
-; RV64-NEXT: sb a6, 0(a7)
-; RV64-NEXT: srliw a0, a3, 8
-; RV64-NEXT: addi a6, a4, 1
-; RV64-NEXT: sb a3, 0(a4)
-; RV64-NEXT: sb a0, 0(a6)
-; RV64-NEXT: srliw a0, a1, 16
-; RV64-NEXT: addi a3, a2, 2
-; RV64-NEXT: and a5, a1, a5
-; RV64-NEXT: srliw a4, a5, 8
-; RV64-NEXT: addi a5, a2, 1
-; RV64-NEXT: sb a1, 0(a2)
-; RV64-NEXT: sb a4, 0(a5)
-; RV64-NEXT: srliw a1, a0, 8
-; RV64-NEXT: addi a2, a3, 1
-; RV64-NEXT: sb a0, 0(a3)
-; RV64-NEXT: sb a1, 0(a2)
-; RV64-NEXT: ld a0, 0(s0)
-; RV64-NEXT: addi a0, a0, 3
-; RV64-NEXT: andi a0, a0, -4
-; RV64-NEXT: addi a1, a0, 4
-; RV64-NEXT: sd a1, 0(s0)
-; RV64-NEXT: ld a1, 0(s0)
-; RV64-NEXT: addi a2, sp, 8
-; RV64-NEXT: lw s1, 0(a0)
-; RV64-NEXT: sd a2, 0(a1)
-; RV64-NEXT: addi a0, a2, 4
-; RV64-NEXT: lw a0, 0(a0)
-; RV64-NEXT: lwu a1, 0(a2)
-; RV64-NEXT: slli a0, a0, 32
-; RV64-NEXT: or a0, a0, a1
-; RV64-NEXT: call notdead at plt
-; RV64-NEXT: ld a0, 0(s0)
-; RV64-NEXT: addi a0, a0, 3
-; RV64-NEXT: andi a0, a0, -4
-; RV64-NEXT: addi a1, a0, 4
-; RV64-NEXT: sd a1, 0(s0)
-; RV64-NEXT: ld a1, 0(s0)
-; RV64-NEXT: lw a0, 0(a0)
-; RV64-NEXT: addi a1, a1, 3
-; RV64-NEXT: andi a1, a1, -4
-; RV64-NEXT: addi a2, a1, 4
-; RV64-NEXT: sd a2, 0(s0)
-; RV64-NEXT: ld a2, 0(s0)
-; RV64-NEXT: lw a1, 0(a1)
-; RV64-NEXT: addi a2, a2, 3
-; RV64-NEXT: andi a2, a2, -4
-; RV64-NEXT: addi a3, a2, 4
-; RV64-NEXT: sd a3, 0(s0)
-; RV64-NEXT: lw a2, 0(a2)
-; RV64-NEXT: add a0, a0, s1
-; RV64-NEXT: add a1, a1, a2
-; RV64-NEXT: addw a0, a0, a1
-; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64-NEXT: addi sp, sp, 112
-; RV64-NEXT: ret
- %vargs = alloca ptr
- %wargs = alloca ptr
- call void @llvm.va_start(ptr %vargs)
- %1 = va_arg ptr %vargs, i32
- call void @llvm.va_copy(ptr %wargs, ptr %vargs)
- %2 = load ptr, ptr %wargs, align 4
- call void @notdead(ptr %2)
- %3 = va_arg ptr %vargs, i32
- %4 = va_arg ptr %vargs, i32
- %5 = va_arg ptr %vargs, i32
- call void @llvm.va_end(ptr %vargs)
- call void @llvm.va_end(ptr %wargs)
- %add1 = add i32 %3, %1
- %add2 = add i32 %add1, %4
- %add3 = add i32 %add2, %5
- ret i32 %add3
-}
-
-; A function with no fixed arguments is not valid C, but can be
-; specified in LLVM IR. We must ensure the vararg save area is
-; still set up correctly.
-
-define i32 @va6_no_fixed_args(...) nounwind {
-; RV32-LABEL: va6_no_fixed_args:
-; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -48
-; RV32-NEXT: addi t0, sp, 16
-; RV32-NEXT: sw a0, 0(t0)
-; RV32-NEXT: addi a0, sp, 20
-; RV32-NEXT: sw a1, 0(a0)
-; RV32-NEXT: addi a0, sp, 24
-; RV32-NEXT: sw a2, 0(a0)
-; RV32-NEXT: addi a0, sp, 28
-; RV32-NEXT: sw a3, 0(a0)
-; RV32-NEXT: addi a0, sp, 32
-; RV32-NEXT: sw a4, 0(a0)
-; RV32-NEXT: addi a0, sp, 36
-; RV32-NEXT: sw a5, 0(a0)
-; RV32-NEXT: addi a0, sp, 40
-; RV32-NEXT: sw a6, 0(a0)
-; RV32-NEXT: addi a0, sp, 44
-; RV32-NEXT: sw a7, 0(a0)
-; RV32-NEXT: addi a0, sp, 12
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: srli a2, a0, 16
-; RV32-NEXT: addi a3, a1, 2
-; RV32-NEXT: lui a4, 16
-; RV32-NEXT: addi a4, a4, -1
-; RV32-NEXT: and a4, a0, a4
-; RV32-NEXT: srli a4, a4, 8
-; RV32-NEXT: addi a5, a1, 1
-; RV32-NEXT: sb a0, 0(a1)
-; RV32-NEXT: sb a4, 0(a5)
-; RV32-NEXT: srli a1, a2, 8
-; RV32-NEXT: addi a4, a3, 1
-; RV32-NEXT: sb a2, 0(a3)
-; RV32-NEXT: sb a1, 0(a4)
-; RV32-NEXT: lw a1, 0(a0)
-; RV32-NEXT: addi a1, a1, 3
-; RV32-NEXT: andi a1, a1, -4
-; RV32-NEXT: addi a2, a1, 4
-; RV32-NEXT: sw a2, 0(a0)
-; RV32-NEXT: lw a0, 0(a1)
-; RV32-NEXT: addi sp, sp, 48
-; RV32-NEXT: ret
-;
-; RV64-LABEL: va6_no_fixed_args:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -80
-; RV64-NEXT: addi t0, sp, 16
-; RV64-NEXT: sd a0, 0(t0)
-; RV64-NEXT: addi a0, sp, 24
-; RV64-NEXT: sd a1, 0(a0)
-; RV64-NEXT: addi a0, sp, 32
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: addi a0, sp, 40
-; RV64-NEXT: sd a3, 0(a0)
-; RV64-NEXT: addi a0, sp, 48
-; RV64-NEXT: sd a4, 0(a0)
-; RV64-NEXT: addi a0, sp, 56
-; RV64-NEXT: sd a5, 0(a0)
-; RV64-NEXT: addi a0, sp, 64
-; RV64-NEXT: sd a6, 0(a0)
-; RV64-NEXT: addi a0, sp, 72
-; RV64-NEXT: sd a7, 0(a0)
-; RV64-NEXT: addi a0, sp, 8
-; RV64-NEXT: addi a1, sp, 16
-; RV64-NEXT: srli a2, a0, 32
-; RV64-NEXT: addi a3, a1, 4
-; RV64-NEXT: srliw a4, a0, 16
-; RV64-NEXT: addi a5, a1, 2
-; RV64-NEXT: lui a6, 16
-; RV64-NEXT: addi a6, a6, -1
-; RV64-NEXT: and a7, a0, a6
-; RV64-NEXT: srliw a7, a7, 8
-; RV64-NEXT: addi t0, a1, 1
-; RV64-NEXT: sb a0, 0(a1)
-; RV64-NEXT: sb a7, 0(t0)
-; RV64-NEXT: srliw a1, a4, 8
-; RV64-NEXT: addi a7, a5, 1
-; RV64-NEXT: sb a4, 0(a5)
-; RV64-NEXT: sb a1, 0(a7)
-; RV64-NEXT: srliw a1, a2, 16
-; RV64-NEXT: addi a4, a3, 2
-; RV64-NEXT: and a5, a2, a6
-; RV64-NEXT: srliw a5, a5, 8
-; RV64-NEXT: addi a6, a3, 1
-; RV64-NEXT: sb a2, 0(a3)
-; RV64-NEXT: sb a5, 0(a6)
-; RV64-NEXT: srliw a2, a1, 8
-; RV64-NEXT: addi a3, a4, 1
-; RV64-NEXT: sb a1, 0(a4)
-; RV64-NEXT: sb a2, 0(a3)
-; RV64-NEXT: ld a1, 0(a0)
-; RV64-NEXT: addi a1, a1, 3
-; RV64-NEXT: andi a1, a1, -4
-; RV64-NEXT: addi a2, a1, 4
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: lw a0, 0(a1)
-; RV64-NEXT: addi sp, sp, 80
-; RV64-NEXT: ret
- %va = alloca ptr
- call void @llvm.va_start(ptr %va)
- %1 = va_arg ptr %va, i32
- call void @llvm.va_end(ptr %va)
- ret i32 %1
-}
-
-; TODO: improve constant materialization of stack addresses
-
-define i32 @va_large_stack(ptr %fmt, ...) {
-; RV32-LABEL: va_large_stack:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 24414
-; RV32-NEXT: addi a0, a0, 304
-; RV32-NEXT: sub sp, sp, a0
-; RV32-NEXT: .cfi_def_cfa_offset 100000048
-; RV32-NEXT: lui a0, 24414
-; RV32-NEXT: addi a0, a0, 276
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: sw a1, 0(a0)
-; RV32-NEXT: lui a0, 24414
-; RV32-NEXT: addi a0, a0, 280
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: sw a2, 0(a0)
-; RV32-NEXT: lui a0, 24414
-; RV32-NEXT: addi a0, a0, 284
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: sw a3, 0(a0)
-; RV32-NEXT: lui a0, 24414
-; RV32-NEXT: addi a0, a0, 288
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: sw a4, 0(a0)
-; RV32-NEXT: lui a0, 24414
-; RV32-NEXT: addi a0, a0, 292
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: sw a5, 0(a0)
-; RV32-NEXT: lui a0, 24414
-; RV32-NEXT: addi a0, a0, 296
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a1, sp, 12
-; RV32-NEXT: lui a2, 24414
-; RV32-NEXT: addi a2, a2, 276
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: srli a3, a1, 16
-; RV32-NEXT: addi a4, a2, 2
-; RV32-NEXT: lui a5, 16
-; RV32-NEXT: addi a5, a5, -1
-; RV32-NEXT: and a5, a1, a5
-; RV32-NEXT: srli a5, a5, 8
-; RV32-NEXT: sb a1, 0(a2)
-; RV32-NEXT: addi a2, a2, 1
-; RV32-NEXT: sb a5, 0(a2)
-; RV32-NEXT: srli a2, a3, 8
-; RV32-NEXT: addi a5, a4, 1
-; RV32-NEXT: sb a3, 0(a4)
-; RV32-NEXT: sb a2, 0(a5)
-; RV32-NEXT: lw a2, 0(a1)
-; RV32-NEXT: sw a6, 0(a0)
-; RV32-NEXT: lui a0, 24414
-; RV32-NEXT: addi a0, a0, 300
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: sw a7, 0(a0)
-; RV32-NEXT: addi a0, a2, 4
-; RV32-NEXT: sw a0, 0(a1)
-; RV32-NEXT: lw a0, 0(a2)
-; RV32-NEXT: lui a1, 24414
-; RV32-NEXT: addi a1, a1, 304
-; RV32-NEXT: add sp, sp, a1
-; RV32-NEXT: ret
-;
-; RV64-LABEL: va_large_stack:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 24414
-; RV64-NEXT: addiw a0, a0, 336
-; RV64-NEXT: sub sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa_offset 100000080
-; RV64-NEXT: lui a0, 24414
-; RV64-NEXT: addiw a0, a0, 280
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: sd a1, 0(a0)
-; RV64-NEXT: lui a0, 24414
-; RV64-NEXT: addiw a0, a0, 288
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: lui a0, 24414
-; RV64-NEXT: addiw a0, a0, 296
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: sd a3, 0(a0)
-; RV64-NEXT: lui a0, 24414
-; RV64-NEXT: addiw a0, a0, 304
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: sd a4, 0(a0)
-; RV64-NEXT: lui a0, 24414
-; RV64-NEXT: addiw a0, a0, 312
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: sd a5, 0(a0)
-; RV64-NEXT: lui a0, 24414
-; RV64-NEXT: addiw a0, a0, 320
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: sd a6, 0(a0)
-; RV64-NEXT: addi a0, sp, 8
-; RV64-NEXT: lui a1, 24414
-; RV64-NEXT: addiw a1, a1, 280
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: srli a2, a0, 32
-; RV64-NEXT: addi a3, a1, 4
-; RV64-NEXT: srliw a4, a0, 16
-; RV64-NEXT: addi a5, a1, 2
-; RV64-NEXT: lui a6, 16
-; RV64-NEXT: addi a6, a6, -1
-; RV64-NEXT: and t0, a0, a6
-; RV64-NEXT: srliw t0, t0, 8
-; RV64-NEXT: sb a0, 0(a1)
-; RV64-NEXT: addi a1, a1, 1
-; RV64-NEXT: sb t0, 0(a1)
-; RV64-NEXT: srliw a1, a4, 8
-; RV64-NEXT: addi t0, a5, 1
-; RV64-NEXT: sb a4, 0(a5)
-; RV64-NEXT: sb a1, 0(t0)
-; RV64-NEXT: srliw a1, a2, 16
-; RV64-NEXT: addi a4, a3, 2
-; RV64-NEXT: and a5, a2, a6
-; RV64-NEXT: srliw a5, a5, 8
-; RV64-NEXT: addi a6, a3, 1
-; RV64-NEXT: sb a2, 0(a3)
-; RV64-NEXT: sb a5, 0(a6)
-; RV64-NEXT: srliw a2, a1, 8
-; RV64-NEXT: addi a3, a4, 1
-; RV64-NEXT: sb a1, 0(a4)
-; RV64-NEXT: sb a2, 0(a3)
-; RV64-NEXT: addi a1, a0, 4
-; RV64-NEXT: lw a2, 0(a1)
-; RV64-NEXT: lwu a3, 0(a0)
-; RV64-NEXT: lui a4, 24414
-; RV64-NEXT: addiw a4, a4, 328
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: sd a7, 0(a4)
-; RV64-NEXT: slli a2, a2, 32
-; RV64-NEXT: or a2, a2, a3
-; RV64-NEXT: addi a3, a2, 4
-; RV64-NEXT: srli a4, a3, 32
-; RV64-NEXT: sw a3, 0(a0)
-; RV64-NEXT: sw a4, 0(a1)
-; RV64-NEXT: lw a0, 0(a2)
-; RV64-NEXT: lui a1, 24414
-; RV64-NEXT: addiw a1, a1, 336
-; RV64-NEXT: add sp, sp, a1
-; RV64-NEXT: ret
- %large = alloca [ 100000000 x i8 ]
- %va = alloca ptr
- call void @llvm.va_start(ptr %va)
- %argp.cur = load ptr, ptr %va, align 4
- %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4
- store ptr %argp.next, ptr %va, align 4
- %1 = load i32, ptr %argp.cur, align 4
- call void @llvm.va_end(ptr %va)
- ret i32 %1
-}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; LP64: {{.*}}
-; LP64D: {{.*}}
-; LP64F: {{.*}}
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