[llvm] [PowerPC] Add a set of extended mnemonics that are missing from Power 10. (PR #73003)
Stefan Pintilie via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 7 09:02:11 PST 2023
https://github.com/stefanp-ibm updated https://github.com/llvm/llvm-project/pull/73003
>From 7eee710921246e58f8a085896b77e73fa42d539a Mon Sep 17 00:00:00 2001
From: Stefan Pintilie <stefanp at ca.ibm.com>
Date: Fri, 3 Nov 2023 14:49:59 -0500
Subject: [PATCH] [PowerPC] Add a set of extended mnemonics that are missing
from Power 10.
This patch adds the majority of the missing extended mnemonics that were
introduced in Power 10.
The only extended menemonics that were not added are related to the plq and pstq
instructions. These will be added in a separate patch as the instructions
themselves would also have to be added.
---
.../Target/PowerPC/AsmParser/PPCAsmParser.cpp | 29 ++
llvm/lib/Target/PowerPC/P10InstrResources.td | 3 +-
.../lib/Target/PowerPC/PPCBack2BackFusion.def | 1 +
llvm/lib/Target/PowerPC/PPCInstrFormats.td | 32 ++
llvm/lib/Target/PowerPC/PPCInstrInfo.td | 34 +-
llvm/lib/Target/PowerPC/PPCInstrP10.td | 207 +++++++++---
.../PowerPC/pcrel-tls-local-dynamic.ll | 4 +-
.../CodeGen/PowerPC/pcrel-tls-local-exec.ll | 20 +-
.../PowerPC/pcrel-tls_get_addr_clobbers.ll | 2 +-
llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s | 298 ++++++++++++++++++
llvm/test/MC/PowerPC/ppc64-errors.s | 4 +-
11 files changed, 556 insertions(+), 78 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index ed52b9a9cf27b..a33f44542eb5c 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -886,6 +886,26 @@ void PPCAsmParser::ProcessInstruction(MCInst &Inst,
Inst = TmpInst;
break;
}
+ case PPC::PLA8:
+ case PPC::PLA: {
+ MCInst TmpInst;
+ TmpInst.setOpcode(Opcode == PPC::PLA ? PPC::PADDI : PPC::PADDI8);
+ TmpInst.addOperand(Inst.getOperand(0));
+ TmpInst.addOperand(Inst.getOperand(1));
+ TmpInst.addOperand(Inst.getOperand(2));
+ Inst = TmpInst;
+ break;
+ }
+ case PPC::PLA8pc:
+ case PPC::PLApc: {
+ MCInst TmpInst;
+ TmpInst.setOpcode(Opcode == PPC::PLApc ? PPC::PADDIpc : PPC::PADDI8pc);
+ TmpInst.addOperand(Inst.getOperand(0));
+ TmpInst.addOperand(MCOperand::createImm(0));
+ TmpInst.addOperand(Inst.getOperand(1));
+ Inst = TmpInst;
+ break;
+ }
case PPC::SUBI: {
MCInst TmpInst;
TmpInst.setOpcode(PPC::ADDI);
@@ -895,6 +915,15 @@ void PPCAsmParser::ProcessInstruction(MCInst &Inst,
Inst = TmpInst;
break;
}
+ case PPC::PSUBI: {
+ MCInst TmpInst;
+ TmpInst.setOpcode(PPC::PADDI);
+ TmpInst.addOperand(Inst.getOperand(0));
+ TmpInst.addOperand(Inst.getOperand(1));
+ addNegOperand(TmpInst, Inst.getOperand(2), getContext());
+ Inst = TmpInst;
+ break;
+ }
case PPC::SUBIS: {
MCInst TmpInst;
TmpInst.setOpcode(PPC::ADDIS);
diff --git a/llvm/lib/Target/PowerPC/P10InstrResources.td b/llvm/lib/Target/PowerPC/P10InstrResources.td
index 66a050955631a..3bbc5a63ca7ab 100644
--- a/llvm/lib/Target/PowerPC/P10InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P10InstrResources.td
@@ -875,7 +875,7 @@ def : InstRW<[P10W_FX_3C, P10W_DISP_ANY],
MCRXRX,
MFCTR, MFCTR8,
MFLR, MFLR8,
- WAIT
+ WAIT, WAITP10
)>;
// 3 Cycles ALU operations, 1 input operands
@@ -1884,6 +1884,7 @@ def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read,
def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY],
(instrs
ISYNC,
+ SYNCP10,
SYNC
)>;
diff --git a/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def b/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
index 5d97d187b2969..8bbe315a2bb9a 100644
--- a/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
+++ b/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
@@ -958,6 +958,7 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
V_SET0B,
V_SET0H,
WAIT,
+ WAITP10,
XOR,
XOR8,
XOR8_rec,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index 6501c17dd810e..5389f42a325ce 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -725,6 +725,38 @@ class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
let Inst{31} = 0;
}
+class XForm_IMM2_IMM2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<2> L;
+ bits<2> PL;
+
+ let Pattern = pattern;
+ let Inst{6-8} = 0;
+ let Inst{9-10} = L;
+ let Inst{11-13} = 0;
+ let Inst{14-15} = PL;
+ let Inst{16-20} = 0;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
+class XForm_IMM3_IMM2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<3> L;
+ bits<2> SC;
+
+ let Pattern = pattern;
+ let Inst{6-7} = 0;
+ let Inst{8-10} = L;
+ let Inst{11-13} = 0;
+ let Inst{14-15} = SC;
+ let Inst{16-20} = 0;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern>
: XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index a97062e0c643f..6199785206b2f 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3437,6 +3437,23 @@ def crnot : OutPatFrag<(ops node:$in),
def : Pat<(not i1:$in),
(crnot $in)>;
+// Pseudo-instructions for alternate assembly syntax (never used by codegen).
+// These are aliases that require C++ handling to convert to the target
+// instruction, while InstAliases can be handled directly by tblgen.
+class PPCAsmPseudo<string asm, dag iops>
+ : Instruction {
+ let Namespace = "PPC";
+ bit PPC64 = 0; // Default value, override with isPPC64
+
+ let OutOperandList = (outs);
+ let InOperandList = iops;
+ let Pattern = [];
+ let AsmString = asm;
+ let isAsmParserOnly = 1;
+ let isPseudo = 1;
+ let hasNoSchedulingInfo = 1;
+}
+
// Prefixed instructions may require access to the above defs at a later
// time so we include this after the def.
include "PPCInstrP10.td"
@@ -4458,23 +4475,6 @@ def ICBIEP : XForm_1a<31, 991, (outs), (ins (memrr $RA, $RB):$addr), "icbiep $a
// PowerPC Assembler Instruction Aliases
//
-// Pseudo-instructions for alternate assembly syntax (never used by codegen).
-// These are aliases that require C++ handling to convert to the target
-// instruction, while InstAliases can be handled directly by tblgen.
-class PPCAsmPseudo<string asm, dag iops>
- : Instruction {
- let Namespace = "PPC";
- bit PPC64 = 0; // Default value, override with isPPC64
-
- let OutOperandList = (outs);
- let InOperandList = iops;
- let Pattern = [];
- let AsmString = asm;
- let isAsmParserOnly = 1;
- let isPseudo = 1;
- let hasNoSchedulingInfo = 1;
-}
-
def : InstAlias<"sc", (SC 0)>;
def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index f72a52d5b26f6..d5a372e4dc101 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -575,33 +575,54 @@ class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
}
multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
- dag PCRel_IOL, string asmstr,
+ dag PCRel_IOL, dag PCRelOnly_IOL,
+ string asmstr, string asmstr_pcext,
InstrItinClass itin> {
def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
!strconcat(asmstr, ", 0"), itin, []>;
def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
!strconcat(asmstr, ", 1"), itin, []>,
isPCRel;
+ let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
+ def nopc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;
+ let RA = 0 in
+ def onlypc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL,
+ asmstr_pcext, itin, []>, isPCRel;
+ }
}
multiclass 8LS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
- dag PCRel_IOL, string asmstr,
+ dag PCRel_IOL, dag PCRelOnly_IOL,
+ string asmstr, string asmstr_pcext,
InstrItinClass itin> {
def NAME : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
!strconcat(asmstr, ", 0"), itin, []>;
def pc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
!strconcat(asmstr, ", 1"), itin, []>,
isPCRel;
+ let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
+ def nopc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;
+ let RA = 0 in
+ def onlypc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL,
+ asmstr_pcext, itin, []>, isPCRel;
+ }
}
multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL,
- dag PCRel_IOL, string asmstr,
+ dag PCRel_IOL, dag PCRelOnly_IOL,
+ string asmstr, string asmstr_pcext,
InstrItinClass itin> {
def NAME : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL,
!strconcat(asmstr, ", 0"), itin, []>;
def pc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRel_IOL,
!strconcat(asmstr, ", 1"), itin, []>,
isPCRel;
+ let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
+ def nopc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;
+ let RA = 0 in
+ def onlypc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRelOnly_IOL,
+ asmstr_pcext, itin, []>, isPCRel;
+ }
}
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
@@ -638,68 +659,88 @@ let Predicates = [PrefixInstrs] in {
defm PLXV :
8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- "plxv $XST, $addr", IIC_LdStLFD>;
+ (ins s34imm_pcrel:$D),
+ "plxv $XST, $addr", "plxv $XST, $D", IIC_LdStLFD>;
defm PLFS :
MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plfs $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plfs $RST, $addr",
+ "plfs $RST, $D", IIC_LdStLFD>;
defm PLFD :
MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plfd $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plfd $RST, $addr",
+ "plfd $RST, $D", IIC_LdStLFD>;
defm PLXSSP :
8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- "plxssp $RST, $addr", IIC_LdStLFD>;
+ (ins s34imm_pcrel:$D),
+ "plxssp $RST, $addr", "plxssp $RST, $D",
+ IIC_LdStLFD>;
defm PLXSD :
8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- "plxsd $RST, $addr", IIC_LdStLFD>;
+ (ins s34imm_pcrel:$D),
+ "plxsd $RST, $addr", "plxsd $RST, $D",
+ IIC_LdStLFD>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm PLBZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plbz $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plbz $RST, $addr",
+ "plbz $RST, $D", IIC_LdStLFD>;
defm PLHZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plhz $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plhz $RST, $addr",
+ "plhz $RST, $D", IIC_LdStLFD>;
defm PLHA8 :
MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plha $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plha $RST, $addr",
+ "plha $RST, $D", IIC_LdStLFD>;
defm PLWA8 :
8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- "plwa $RST, $addr", IIC_LdStLFD>;
+ (ins s34imm_pcrel:$D),
+ "plwa $RST, $addr", "plwa $RST, $D", IIC_LdStLFD>;
defm PLWZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plwz $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plwz $RST, $addr",
+ "plwz $RST, $D", IIC_LdStLFD>;
}
defm PLBZ :
MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plbz $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plbz $RST, $addr",
+ "plbz $RST, $D", IIC_LdStLFD>;
defm PLHZ :
MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plhz $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plhz $RST, $addr",
+ "plhz $RST, $D", IIC_LdStLFD>;
defm PLHA :
MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plha $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plha $RST, $addr",
+ "plha $RST, $D", IIC_LdStLFD>;
defm PLWZ :
MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plwz $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plwz $RST, $addr",
+ "plwz $RST, $D", IIC_LdStLFD>;
defm PLWA :
8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plwa $RST, $addr",
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D),
+ "plwa $RST, $addr", "plwa $RST, $D",
IIC_LdStLFD>;
defm PLD :
8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "pld $RST, $addr",
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D),
+ "pld $RST, $addr", "pld $RST, $D",
IIC_LdStLFD>;
}
@@ -707,53 +748,65 @@ let Predicates = [PrefixInstrs] in {
defm PSTXV :
8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, (memri34 $D, $RA):$addr),
(ins vsrc:$XST, (memri34_pcrel $D, $RA):$addr),
- "pstxv $XST, $addr", IIC_LdStLFD>;
+ (ins vsrc:$XST, s34imm_pcrel:$D),
+ "pstxv $XST, $addr", "pstxv $XST, $D", IIC_LdStLFD>;
defm PSTFS :
MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, (memri34 $D, $RA):$addr),
(ins f4rc:$RST, (memri34_pcrel $D, $RA):$addr),
- "pstfs $RST, $addr", IIC_LdStLFD>;
+ (ins f4rc:$RST, s34imm_pcrel:$D),
+ "pstfs $RST, $addr", "pstfs $RST, $D", IIC_LdStLFD>;
defm PSTFD :
MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, (memri34 $D, $RA):$addr),
(ins f8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- "pstfd $RST, $addr", IIC_LdStLFD>;
+ (ins f8rc:$RST, s34imm_pcrel:$D),
+ "pstfd $RST, $addr", "pstfd $RST, $D", IIC_LdStLFD>;
defm PSTXSSP :
8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
(ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
- "pstxssp $RST, $addr", IIC_LdStLFD>;
+ (ins vfrc:$RST, s34imm_pcrel:$D),
+ "pstxssp $RST, $addr", "pstxssp $RST, $D", IIC_LdStLFD>;
defm PSTXSD :
8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
(ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
- "pstxsd $RST, $addr", IIC_LdStLFD>;
+ (ins vfrc:$RST, s34imm_pcrel:$D),
+ "pstxsd $RST, $addr", "pstxsd $RST, $D", IIC_LdStLFD>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm PSTB8 :
MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
(ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- "pstb $RST, $addr", IIC_LdStLFD>;
+ (ins g8rc:$RST, s34imm_pcrel:$D),
+ "pstb $RST, $addr", "pstb $RST, $D", IIC_LdStLFD>;
defm PSTH8 :
MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
(ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- "psth $RST, $addr", IIC_LdStLFD>;
+ (ins g8rc:$RST, s34imm_pcrel:$D),
+ "psth $RST, $addr", "psth $RST, $D", IIC_LdStLFD>;
defm PSTW8 :
MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
(ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- "pstw $RST, $addr", IIC_LdStLFD>;
+ (ins g8rc:$RST, s34imm_pcrel:$D),
+ "pstw $RST, $addr", "pstw $RST, $D", IIC_LdStLFD>;
}
defm PSTB :
MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),
(ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),
- "pstb $RST, $addr", IIC_LdStLFD>;
+ (ins gprc:$RST, s34imm_pcrel:$D),
+ "pstb $RST, $addr", "pstb $RST, $D", IIC_LdStLFD>;
defm PSTH :
MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),
(ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),
- "psth $RST, $addr", IIC_LdStLFD>;
+ (ins gprc:$RST, s34imm_pcrel:$D),
+ "psth $RST, $addr", "psth $RST, $D", IIC_LdStLFD>;
defm PSTW :
MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),
(ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),
- "pstw $RST, $addr", IIC_LdStLFD>;
+ (ins gprc:$RST, s34imm_pcrel:$D),
+ "pstw $RST, $addr", "pstw $RST, $D", IIC_LdStLFD>;
defm PSTD :
8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
(ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- "pstd $RST, $addr", IIC_LdStLFD>;
+ (ins g8rc:$RST, s34imm_pcrel:$D),
+ "pstd $RST, $addr", "pstd $RST, $D", IIC_LdStLFD>;
}
}
@@ -812,13 +865,20 @@ class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
}
multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL,
- dag IOL, dag PCRel_IOL,
- string asmstr, InstrItinClass itin> {
+ dag IOL, dag PCRel_IOL, dag PCRelOnly_IOL,
+ string asmstr, string asmstr_pcext,
+ InstrItinClass itin> {
def NAME : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL,
!strconcat(asmstr, ", 0"), itin, []>;
def pc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRel_IOL,
!strconcat(asmstr, ", 1"), itin, []>,
isPCRel;
+ let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
+ def nopc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL, asmstr, itin, []>;
+ let RA = 0 in
+ def onlypc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRelOnly_IOL,
+ asmstr_pcext, itin, []>, isPCRel;
+ }
}
@@ -1079,7 +1139,9 @@ let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in {
let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in {
defm PLXVP :
8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plxvp $XTp, $addr",
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D),
+ "plxvp $XTp, $addr", "plxvp $XTp, $D",
IIC_LdStLFD>;
}
@@ -1087,7 +1149,8 @@ let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] i
defm PSTXVP :
8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, (memri34 $D, $RA):$addr),
(ins vsrprc:$XTp, (memri34_pcrel $D, $RA):$addr),
- "pstxvp $XTp, $addr", IIC_LdStLFD>;
+ (ins vsrprc:$XTp, s34imm_pcrel:$D),
+ "pstxvp $XTp, $addr", "pstxvp $XTp, $D", IIC_LdStLFD>;
}
let Predicates = [PairedVectorMemops] in {
@@ -1855,6 +1918,13 @@ let Predicates = [IsISA3_1, HasVSX] in {
[(set f128:$RST, (PPCxsminc f128:$RA, f128:$RB))]>;
}
+let Predicates = [IsISA3_1] in {
+ def WAITP10 : XForm_IMM2_IMM2<31, 30, (outs), (ins u2imm:$L, u2imm:$PL),
+ "wait $L $PL", IIC_LdStLoad, []>;
+ def SYNCP10 : XForm_IMM3_IMM2<31, 598, (outs), (ins u3imm:$L, u2imm:$SC),
+ "sync $L, $SC", IIC_LdStSync, []>;
+}
+
// Multiclass defining patterns for Set Boolean Extension Reverse Instructions.
// This is analogous to the CRNotPat multiclass but specifically for Power10
// and newer subtargets since the extended forms use Set Boolean instructions.
@@ -2386,3 +2456,50 @@ let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsBigEndian] in {
def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, Idx)),
(VINSD $vDi, !mul(Idx, 8), $rA)>;
}
+
+
+//===----------------------------------------------------------------------===//
+// PowerPC ISA 3.1 Extended Mnemonics.
+//
+
+let Predicates = [IsISA3_1] in {
+ def : InstAlias<"wait", (WAITP10 0, 0)>;
+ def : InstAlias<"wait 0", (WAITP10 0, 0), 0>;
+ def : InstAlias<"wait 1", (WAITP10 1, 0), 0>;
+ def : InstAlias<"waitrsv", (WAITP10 1, 0)>;
+ def : InstAlias<"pause_short", (WAITP10 2, 0), 0>;
+
+ def : InstAlias<"sync", (SYNCP10 0, 0)>;
+ def : InstAlias<"hwsync", (SYNCP10 0, 0), 0>;
+ def : InstAlias<"wsync", (SYNCP10 1, 0), 0>;
+ def : InstAlias<"ptesync", (SYNCP10 2, 0)>;
+ def : InstAlias<"phwsync", (SYNCP10 4, 0)>;
+ def : InstAlias<"plwsync", (SYNCP10 5, 0)>;
+ def : InstAlias<"sync $L", (SYNCP10 u3imm:$L, 0)>;
+ def : InstAlias<"stncisync", (SYNCP10 1, 1)>;
+ def : InstAlias<"stcisync", (SYNCP10 0, 2)>;
+ def : InstAlias<"stsync", (SYNCP10 0, 3)>;
+
+ def : InstAlias<"paddi $RT, $RA, $SI", (PADDI8 g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI)>;
+}
+
+let Predicates = [IsISA3_1, PrefixInstrs], isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
+ let Interpretation64Bit = 1 in {
+ def PLA8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
+ (ins g8rc_nox0:$RA, s34imm:$SI),
+ "pla $RT, ${SI} ${RA}", IIC_IntSimple, []>;
+ def PLA8pc : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
+ (ins s34imm_pcrel:$SI),
+ "pla $RT, $SI", IIC_IntSimple, []>, isPCRel;
+ }
+
+ def PSUBI : PPCAsmPseudo<"psubi $RT, $RA, $SI",
+ (ins g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI)>;
+
+ def PLA : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
+ (ins gprc_nor0:$RA, s34imm:$SI),
+ "pla $RT, ${SI} ${RA}", IIC_IntSimple, []>;
+ def PLApc : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
+ (ins s34imm_pcrel:$SI),
+ "pla $RT, $SI", IIC_IntSimple, []>, isPCRel;
+}
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-tls-local-dynamic.ll b/llvm/test/CodeGen/PowerPC/pcrel-tls-local-dynamic.ll
index 0b0fdbcaf0a4e..da9844348f603 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel-tls-local-dynamic.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-tls-local-dynamic.ll
@@ -13,7 +13,7 @@ define nonnull ptr @LocalDynamicAddressLoad() {
; CHECK-S-LABEL: LocalDynamicAddressLoad:
; CHECK-S: paddi r3, 0, x at got@tlsld at pcrel, 1
; CHECK-S-NEXT: bl __tls_get_addr at notoc(x at tlsld)
- ; CHECK-S-NEXT: paddi r3, r3, x at DTPREL, 0
+ ; CHECK-S-NEXT: paddi r3, r3, x at DTPREL
; CHECK-S-NEXT: addi r1, r1, 32
; CHECK-S-NEXT: ld r0, 16(r1)
; CHECK-S-NEXT: mtlr r0
@@ -34,7 +34,7 @@ define i32 @LocalDynamicValueLoad() {
; CHECK-S-LABEL: LocalDynamicValueLoad:
; CHECK-S: paddi r3, 0, x at got@tlsld at pcrel, 1
; CHECK-S-NEXT: bl __tls_get_addr at notoc(x at tlsld)
- ; CHECK-S-NEXT: paddi r3, r3, x at DTPREL, 0
+ ; CHECK-S-NEXT: paddi r3, r3, x at DTPREL
; CHECK-S-NEXT: lwz r3, 0(r3)
; CHECK-S-NEXT: addi r1, r1, 32
; CHECK-S-NEXT: ld r0, 16(r1)
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-tls-local-exec.ll b/llvm/test/CodeGen/PowerPC/pcrel-tls-local-exec.ll
index 77d18e1b64de2..e4a22e0e2427e 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel-tls-local-exec.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-tls-local-exec.ll
@@ -14,10 +14,10 @@
define dso_local ptr @LocalExecAddressLoad() {
; CHECK-S-LABEL: LocalExecAddressLoad:
; CHECK-S: # %bb.0: # %entry
-; CHECK-S-NEXT: paddi r3, r13, x at TPREL, 0
+; CHECK-S-NEXT: paddi r3, r13, x at TPREL
; CHECK-S-NEXT: blr
; CHECK-O-LABEL: <LocalExecAddressLoad>:
-; CHECK-O: 0: paddi 3, 13, 0, 0
+; CHECK-O: 0: paddi 3, 13, 0
; CHECK-O-NEXT: 0000000000000000: R_PPC64_TPREL34 x
; CHECK-O-NEXT: 8: blr
entry:
@@ -27,11 +27,11 @@ entry:
define dso_local i32 @LocalExecValueLoad() {
; CHECK-S-LABEL: LocalExecValueLoad:
; CHECK-S: # %bb.0: # %entry
-; CHECK-S-NEXT: paddi r3, r13, x at TPREL, 0
+; CHECK-S-NEXT: paddi r3, r13, x at TPREL
; CHECK-S-NEXT: lwz r3, 0(r3)
; CHECK-S-NEXT: blr
; CHECK-O-LABEL: <LocalExecValueLoad>:
-; CHECK-O: 20: paddi 3, 13, 0, 0
+; CHECK-O: 20: paddi 3, 13, 0
; CHECK-O-NEXT: 0000000000000020: R_PPC64_TPREL34 x
; CHECK-O-NEXT: 28: lwz 3, 0(3)
; CHECK-O-NEXT: 2c: blr
@@ -43,11 +43,11 @@ entry:
define dso_local void @LocalExecValueStore(i32 %in) {
; CHECK-S-LABEL: LocalExecValueStore:
; CHECK-S: # %bb.0: # %entry
-; CHECK-S-NEXT: paddi r4, r13, x at TPREL, 0
+; CHECK-S-NEXT: paddi r4, r13, x at TPREL
; CHECK-S-NEXT: stw r3, 0(r4)
; CHECK-S-NEXT: blr
; CHECK-O-LABEL: <LocalExecValueStore>:
-; CHECK-O: 40: paddi 4, 13, 0, 0
+; CHECK-O: 40: paddi 4, 13, 0
; CHECK-O-NEXT: 0000000000000040: R_PPC64_TPREL34 x
; CHECK-O-NEXT: 48: stw 3, 0(4)
; CHECK-O-NEXT: 4c: blr
@@ -59,11 +59,11 @@ entry:
define dso_local i32 @LocalExecValueLoadOffset() {
; CHECK-S-LABEL: LocalExecValueLoadOffset:
; CHECK-S: # %bb.0: # %entry
-; CHECK-S-NEXT: paddi r3, r13, y at TPREL, 0
+; CHECK-S-NEXT: paddi r3, r13, y at TPREL
; CHECK-S-NEXT: lwz r3, 12(r3)
; CHECK-S-NEXT: blr
; CHECK-O-LABEL: <LocalExecValueLoadOffset>:
-; CHECK-O: 60: paddi 3, 13, 0, 0
+; CHECK-O: 60: paddi 3, 13, 0
; CHECK-O-NEXT: 0000000000000060: R_PPC64_TPREL34 y
; CHECK-O-NEXT: 68: lwz 3, 12(3)
; CHECK-O-NEXT: 6c: blr
@@ -76,11 +76,11 @@ entry:
define dso_local ptr @LocalExecValueLoadOffsetNoLoad() {
; CHECK-S-LABEL: LocalExecValueLoadOffsetNoLoad:
; CHECK-S: # %bb.0: # %entry
-; CHECK-S-NEXT: paddi r3, r13, y at TPREL, 0
+; CHECK-S-NEXT: paddi r3, r13, y at TPREL
; CHECK-S-NEXT: addi r3, r3, 12
; CHECK-S-NEXT: blr
; CHECK-O-LABEL: <LocalExecValueLoadOffsetNoLoad>:
-; CHECK-O: 80: paddi 3, 13, 0, 0
+; CHECK-O: 80: paddi 3, 13, 0
; CHECK-O-NEXT: 0000000000000080: R_PPC64_TPREL34 y
; CHECK-O-NEXT: 88: addi 3, 3, 12
; CHECK-O-NEXT: 8c: blr
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-tls_get_addr_clobbers.ll b/llvm/test/CodeGen/PowerPC/pcrel-tls_get_addr_clobbers.ll
index 38f55dac1ea81..905d13814ab7d 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel-tls_get_addr_clobbers.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-tls_get_addr_clobbers.ll
@@ -13,7 +13,7 @@ define void @test(ptr %arg) {
; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: paddi r3, 0, x at got@tlsld at pcrel, 1
; CHECK-NEXT: bl __tls_get_addr at notoc(x at tlsld)
-; CHECK-NEXT: paddi r3, r3, x at DTPREL, 0
+; CHECK-NEXT: paddi r3, r3, x at DTPREL
; CHECK-NEXT: std r30, 0(r3)
; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1)
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
index d2d0d44f639a9..03179480147a5 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -1044,3 +1044,301 @@
# CHECK-BE: hashchkp 5, -512(1) # encoding: [0x7c,0x01,0x2d,0x64]
# CHECK-LE: hashchkp 5, -512(1) # encoding: [0x64,0x2d,0x01,0x7c]
hashchkp 5, -512(1)
+
+##
+## Extended Mnemonics
+##
+
+# CHECK-BE: wait # encoding: [0x7c,0x00,0x00,0x3c]
+# CHECK-LE: wait # encoding: [0x3c,0x00,0x00,0x7c]
+ wait
+# CHECK-BE: wait # encoding: [0x7c,0x00,0x00,0x3c]
+# CHECK-LE: wait # encoding: [0x3c,0x00,0x00,0x7c]
+ wait 0
+# CHECK-BE: waitrsv # encoding: [0x7c,0x20,0x00,0x3c]
+# CHECK-LE: waitrsv # encoding: [0x3c,0x00,0x20,0x7c]
+ wait 1
+# CHECK-BE: waitrsv # encoding: [0x7c,0x20,0x00,0x3c]
+# CHECK-LE: waitrsv # encoding: [0x3c,0x00,0x20,0x7c]
+ waitrsv
+# CHECK-BE: wait 2 0 # encoding: [0x7c,0x40,0x00,0x3c]
+# CHECK-LE: wait 2 0 # encoding: [0x3c,0x00,0x40,0x7c]
+ pause_short
+
+# CHECK-BE: sync # encoding: [0x7c,0x00,0x04,0xac]
+# CHECK-LE: sync # encoding: [0xac,0x04,0x00,0x7c]
+ sync
+# CHECK-BE: ptesync # encoding: [0x7c,0x40,0x04,0xac]
+# CHECK-LE: ptesync # encoding: [0xac,0x04,0x40,0x7c]
+ sync 2
+# CHECK-BE: sync # encoding: [0x7c,0x00,0x04,0xac]
+# CHECK-LE: sync # encoding: [0xac,0x04,0x00,0x7c]
+ hwsync
+# CHECK-BE: sync 1 # encoding: [0x7c,0x20,0x04,0xac]
+# CHECK-LE: sync 1 # encoding: [0xac,0x04,0x20,0x7c]
+ wsync
+# CHECK-BE: ptesync # encoding: [0x7c,0x40,0x04,0xac]
+# CHECK-LE: ptesync # encoding: [0xac,0x04,0x40,0x7c]
+ ptesync
+# CHECK-BE: phwsync # encoding: [0x7c,0x80,0x04,0xac]
+# CHECK-LE: phwsync # encoding: [0xac,0x04,0x80,0x7c]
+ phwsync
+# CHECK-BE: plwsync # encoding: [0x7c,0xa0,0x04,0xac]
+# CHECK-LE: plwsync # encoding: [0xac,0x04,0xa0,0x7c]
+ plwsync
+# CHECK-BE: stncisync # encoding: [0x7c,0x21,0x04,0xac]
+# CHECK-LE: stncisync # encoding: [0xac,0x04,0x21,0x7c]
+ stncisync
+# CHECK-BE: stcisync # encoding: [0x7c,0x02,0x04,0xac]
+# CHECK-LE: stcisync # encoding: [0xac,0x04,0x02,0x7c]
+ stcisync
+# CHECK-BE: stsync # encoding: [0x7c,0x03,0x04,0xac]
+# CHECK-LE: stsync # encoding: [0xac,0x04,0x03,0x7c]
+ stsync
+
+# CHECK-BE: paddi 4, 5, 4294965249 # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0x38,0x85,0xf8,0x01]
+# CHECK-LE: paddi 4, 5, 4294965249 # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0x85,0x38]
+ paddi 4, 5, 4294965249
+# CHECK-BE: pli 4, 4294965249 # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0x38,0x80,0xf8,0x01]
+# CHECK-LE: pli 4, 4294965249 # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0x80,0x38]
+ pli 4, 4294965249
+# CHECK-BE: paddi 4, 3, 4294965249 # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0x38,0x83,0xf8,0x01]
+# CHECK-LE: paddi 4, 3, 4294965249 # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0x83,0x38]
+ pla 4, 4294965249(3)
+# CHECK-BE: paddi 4, 0, 4294965249, 1 # encoding: [0x06,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0x38,0x80,0xf8,0x01]
+# CHECK-LE: paddi 4, 0, 4294965249, 1 # encoding: [0xff,0xff,0x10,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0x80,0x38]
+ pla 4, 4294965249
+# CHECK-BE: paddi 4, 5, -80, 0 # encoding: [0x06,0x03,0xff,0xff,
+# CHECK-BE-SAME: 0x38,0x85,0xff,0xb0]
+# CHECK-LE: paddi 4, 5, -80, 0 # encoding: [0xff,0xff,0x03,0x06,
+# CHECK-LE-SAME: 0xb0,0xff,0x85,0x38]
+ psubi 4, 5, 80
+
+# CHECK-BE: plbz 5, 4294965249(3) # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0x88,0xa3,0xf8,0x01]
+# CHECK-LE: plbz 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0x88]
+ plbz 5, 4294965249(3)
+# CHECK-BE: plbz 5, 4294965249 # encoding: [0x06,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0x88,0xa0,0xf8,0x01]
+# CHECK-LE: plbz 5, 4294965249 # encoding: [0xff,0xff,0x10,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0x88]
+ plbz 5, 4294965249
+# CHECK-BE: plhz 5, 4294965249(3) # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xa0,0xa3,0xf8,0x01]
+# CHECK-LE: plhz 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xa0]
+ plhz 5, 4294965249(3)
+# CHECK-BE: plhz 5, 4294965249 # encoding: [0x06,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xa0,0xa0,0xf8,0x01]
+# CHECK-LE: plhz 5, 4294965249 # encoding: [0xff,0xff,0x10,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xa0]
+ plhz 5, 4294965249
+# CHECK-BE: plha 5, 4294965249(3) # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xa8,0xa3,0xf8,0x01]
+# CHECK-LE: plha 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xa8]
+ plha 5, 4294965249(3)
+# CHECK-BE: plha 5, 4294965249 # encoding: [0x06,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xa8,0xa0,0xf8,0x01]
+# CHECK-LE: plha 5, 4294965249 # encoding: [0xff,0xff,0x10,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xa8]
+ plha 5, 4294965249
+# CHECK-BE: plwz 5, 4294965249(3) # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0x80,0xa3,0xf8,0x01]
+# CHECK-LE: plwz 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0x80]
+ plwz 5, 4294965249(3)
+# CHECK-BE: plwz 5, 4294965249 # encoding: [0x06,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0x80,0xa0,0xf8,0x01]
+# CHECK-LE: plwz 5, 4294965249 # encoding: [0xff,0xff,0x10,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0x80]
+ plwz 5, 4294965249
+# CHECK-BE: plwa 5, 4294965249(3) # encoding: [0x04,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xa4,0xa3,0xf8,0x01]
+# CHECK-LE: plwa 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xa4]
+ plwa 5, 4294965249(3)
+# CHECK-BE: plwa 5, 4294965249 # encoding: [0x04,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xa4,0xa0,0xf8,0x01]
+# CHECK-LE: plwa 5, 4294965249 # encoding: [0xff,0xff,0x10,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xa4]
+ plwa 5, 4294965249
+# CHECK-BE: pld 5, 4294965249(3) # encoding: [0x04,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xe4,0xa3,0xf8,0x01]
+# CHECK-LE: pld 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xe4]
+ pld 5, 4294965249(3)
+# CHECK-BE: pld 5, 4294965249 # encoding: [0x04,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xe4,0xa0,0xf8,0x01]
+# CHECK-LE: pld 5, 4294965249 # encoding: [0xff,0xff,0x10,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xe4]
+ pld 5, 4294965249
+# CHECK-BE: pstb 5, 4294965249(3) # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0x98,0xa3,0xf8,0x01]
+# CHECK-LE: pstb 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0x98]
+ pstb 5, 4294965249(3)
+# CHECK-BE: pstb 5, 4294965249 # encoding: [0x06,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0x98,0xa0,0xf8,0x01]
+# CHECK-LE: pstb 5, 4294965249 # encoding: [0xff,0xff,0x10,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0x98]
+ pstb 5, 4294965249
+# CHECK-BE: psth 5, 4294965249(3) # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xb0,0xa3,0xf8,0x01]
+# CHECK-LE: psth 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xb0]
+ psth 5, 4294965249(3)
+# CHECK-BE: psth 5, 4294965249 # encoding: [0x06,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xb0,0xa0,0xf8,0x01]
+# CHECK-LE: psth 5, 4294965249 # encoding: [0xff,0xff,0x10,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xb0]
+ psth 5, 4294965249
+# CHECK-BE: pstw 5, 4294965249(3) # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0x90,0xa3,0xf8,0x01]
+# CHECK-LE: pstw 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0x90]
+ pstw 5, 4294965249(3)
+# CHECK-BE: pstw 5, 4294965249 # encoding: [0x06,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0x90,0xa0,0xf8,0x01]
+# CHECK-LE: pstw 5, 4294965249 # encoding: [0xff,0xff,0x10,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0x90]
+ pstw 5, 4294965249
+# CHECK-BE: pstd 5, 4294965249(3) # encoding: [0x04,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xf4,0xa3,0xf8,0x01]
+# CHECK-LE: pstd 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xf4]
+ pstd 5, 4294965249(3)
+# CHECK-BE: pstd 5, 4294965249 # encoding: [0x04,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xf4,0xa0,0xf8,0x01]
+# CHECK-LE: pstd 5, 4294965249 # encoding: [0xff,0xff,0x10,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xf4]
+ pstd 5, 4294965249
+# CHECK-BE: plfs 5, 4294965249(3) # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xc0,0xa3,0xf8,0x01]
+# CHECK-LE: plfs 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xc0]
+ plfs 5, 4294965249(3)
+# CHECK-BE: plfs 5, 4294965249 # encoding: [0x06,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xc0,0xa0,0xf8,0x01]
+# CHECK-LE: plfs 5, 4294965249 # encoding: [0xff,0xff,0x10,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xc0]
+ plfs 5, 4294965249
+# CHECK-BE: plfd 5, 4294965249(3) # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xc8,0xa3,0xf8,0x01]
+# CHECK-LE: plfd 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xc8]
+ plfd 5, 4294965249(3)
+# CHECK-BE: plfd 5, 4294965249 # encoding: [0x06,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xc8,0xa0,0xf8,0x01]
+# CHECK-LE: plfd 5, 4294965249 # encoding: [0xff,0xff,0x10,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xc8]
+ plfd 5, 4294965249
+# CHECK-BE: pstfs 5, 4294965249(3) # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xd0,0xa3,0xf8,0x01]
+# CHECK-LE: pstfs 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xd0]
+ pstfs 5, 4294965249(3)
+# CHECK-BE: pstfs 5, 4294965249 # encoding: [0x06,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xd0,0xa0,0xf8,0x01]
+# CHECK-LE: pstfs 5, 4294965249 # encoding: [0xff,0xff,0x10,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xd0]
+ pstfs 5, 4294965249
+# CHECK-BE: pstfd 5, 4294965249(3) # encoding: [0x06,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xd8,0xa3,0xf8,0x01]
+# CHECK-LE: pstfd 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xd8]
+ pstfd 5, 4294965249(3)
+# CHECK-BE: pstfd 5, 4294965249 # encoding: [0x06,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xd8,0xa0,0xf8,0x01]
+# CHECK-LE: pstfd 5, 4294965249 # encoding: [0xff,0xff,0x10,0x06,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xd8]
+ pstfd 5, 4294965249
+# CHECK-BE: plxsd 5, 4294965249(3) # encoding: [0x04,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xa8,0xa3,0xf8,0x01]
+# CHECK-LE: plxsd 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xa8]
+ plxsd 5, 4294965249(3)
+# CHECK-BE: plxsd 5, 4294965249 # encoding: [0x04,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xa8,0xa0,0xf8,0x01]
+# CHECK-LE: plxsd 5, 4294965249 # encoding: [0xff,0xff,0x10,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xa8]
+ plxsd 5, 4294965249
+# CHECK-BE: plxssp 5, 4294965249(3) # encoding: [0x04,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xac,0xa3,0xf8,0x01]
+# CHECK-LE: plxssp 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xac]
+ plxssp 5, 4294965249(3)
+# CHECK-BE: plxssp 5, 4294965249 # encoding: [0x04,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xac,0xa0,0xf8,0x01]
+# CHECK-LE: plxssp 5, 4294965249 # encoding: [0xff,0xff,0x10,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xac]
+ plxssp 5, 4294965249
+# CHECK-BE: plxv 5, 4294965249(3) # encoding: [0x04,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xc8,0xa3,0xf8,0x01]
+# CHECK-LE: plxv 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xc8]
+ plxv 5, 4294965249(3)
+# CHECK-BE: plxv 5, 4294965249 # encoding: [0x04,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xc8,0xa0,0xf8,0x01]
+# CHECK-LE: plxv 5, 4294965249 # encoding: [0xff,0xff,0x10,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xc8]
+ plxv 5, 4294965249
+# CHECK-BE: plxvp 6, 4294965249(3) # encoding: [0x04,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xe8,0xc3,0xf8,0x01]
+# CHECK-LE: plxvp 6, 4294965249(3) # encoding: [0xff,0xff,0x00,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xc3,0xe8]
+ plxvp 6, 4294965249(3)
+# CHECK-BE: plxvp 6, 4294965249 # encoding: [0x04,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xe8,0xc0,0xf8,0x01]
+# CHECK-LE: plxvp 6, 4294965249 # encoding: [0xff,0xff,0x10,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xc0,0xe8]
+ plxvp 6, 4294965249
+# CHECK-BE: pstxsd 5, 4294965249(3) # encoding: [0x04,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xb8,0xa3,0xf8,0x01]
+# CHECK-LE: pstxsd 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xb8]
+ pstxsd 5, 4294965249(3)
+# CHECK-BE: pstxsd 5, 4294965249 # encoding: [0x04,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xb8,0xa0,0xf8,0x01]
+# CHECK-LE: pstxsd 5, 4294965249 # encoding: [0xff,0xff,0x10,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xb8]
+ pstxsd 5, 4294965249
+# CHECK-BE: pstxssp 5, 4294965249(3) # encoding: [0x04,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xbc,0xa3,0xf8,0x01]
+# CHECK-LE: pstxssp 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xbc]
+ pstxssp 5, 4294965249(3)
+# CHECK-BE: pstxssp 5, 4294965249 # encoding: [0x04,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xbc,0xa0,0xf8,0x01]
+# CHECK-LE: pstxssp 5, 4294965249 # encoding: [0xff,0xff,0x10,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xbc]
+ pstxssp 5, 4294965249
+# CHECK-BE: pstxv 5, 4294965249(3) # encoding: [0x04,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xd8,0xa3,0xf8,0x01]
+# CHECK-LE: pstxv 5, 4294965249(3) # encoding: [0xff,0xff,0x00,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa3,0xd8]
+ pstxv 5, 4294965249(3)
+# CHECK-BE: pstxv 5, 4294965249 # encoding: [0x04,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xd8,0xa0,0xf8,0x01]
+# CHECK-LE: pstxv 5, 4294965249 # encoding: [0xff,0xff,0x10,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xa0,0xd8]
+ pstxv 5, 4294965249
+# CHECK-BE: pstxvp 6, 4294965249(3) # encoding: [0x04,0x00,0xff,0xff,
+# CHECK-BE-SAME: 0xf8,0xc3,0xf8,0x01]
+# CHECK-LE: pstxvp 6, 4294965249(3) # encoding: [0xff,0xff,0x00,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xc3,0xf8]
+ pstxvp 6, 4294965249(3)
+# CHECK-BE: pstxvp 6, 4294965249 # encoding: [0x04,0x10,0xff,0xff,
+# CHECK-BE-SAME: 0xf8,0xc0,0xf8,0x01]
+# CHECK-LE: pstxvp 6, 4294965249 # encoding: [0xff,0xff,0x10,0x04,
+# CHECK-LE-SAME: 0x01,0xf8,0xc0,0xf8]
+ pstxvp 6, 4294965249
diff --git a/llvm/test/MC/PowerPC/ppc64-errors.s b/llvm/test/MC/PowerPC/ppc64-errors.s
index 627ae410db882..1c03dc084acdf 100644
--- a/llvm/test/MC/PowerPC/ppc64-errors.s
+++ b/llvm/test/MC/PowerPC/ppc64-errors.s
@@ -53,8 +53,8 @@
wait 4
# CHECK: error: invalid operand for instruction
-# CHECK-NEXT: sync 4
- sync 4
+# CHECK-NEXT: sync 8
+ sync 8
# Unsigned 3-bit immediate operands
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