[llvm] [MachineCopyPropagation] When the source of PreviousCopy is undef, we cannot replace sub register (PR #74682)

[via llvm-commits]

https://github.com/DianQK updated https://github.com/llvm/llvm-project/pull/74682

>From efbd7f1b6022d194bc91302667d8850504cf0df0 Mon Sep 17 00:00:00 2001
From: DianQK <dianqk at dianqk.net>
Date: Thu, 7 Dec 2023 22:40:33 +0800
Subject: [PATCH] [MachineCopyPropagation] Pre-commit test case

---
 llvm/lib/CodeGen/MachineCopyPropagation.cpp   |  3 ++
 .../test/CodeGen/AArch64/machine-cp-undef.mir | 33 +++++++++++++++++++
 2 files changed, 36 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/machine-cp-undef.mir

diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index a032b31a1fc7c..fdbdaa0a6d641 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -443,6 +443,9 @@ static bool isNopCopy(const MachineInstr &PreviousCopy, MCRegister Src,
     return true;
   if (!TRI->isSubRegister(PreviousSrc, Src))
     return false;
+  // When the source of PreviousCopy is undef, we cannot replace sub register.
+  if (CopyOperands->Source->isUndef())
+    return false;
   unsigned SubIdx = TRI->getSubRegIndex(PreviousSrc, Src);
   return SubIdx == TRI->getSubRegIndex(PreviousDef, Def);
 }
diff --git a/llvm/test/CodeGen/AArch64/machine-cp-undef.mir b/llvm/test/CodeGen/AArch64/machine-cp-undef.mir
new file mode 100644
index 0000000000000..6c09f2ce7fcc1
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/machine-cp-undef.mir
@@ -0,0 +1,33 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -o - %s -O3 --run-pass=machine-cp -mcp-use-is-copy-instr -mtriple=arm64-apple-macos -mcpu=apple-m1 --verify-machineinstrs | FileCheck %s
+
+---
+name: test
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: test
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   $x8 = ORRXrs $xzr, undef $x0, 0, implicit $w0
+  ; CHECK-NEXT:   $w8 = ORRWrs $wzr, $w0, 0, implicit-def $x8
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   liveins: $x8
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   $x0 = ADDXri $x8, 1, 0
+  ; CHECK-NEXT:   RET undef $lr, implicit $x0
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $w0
+
+    $x8 = ORRXrs $xzr, undef $x0, 0, implicit $w0
+    $w8 = ORRWrs $wzr, $w0, 0, implicit-def $x8
+
+  bb.1:
+    liveins: $x8
+    $x0 = ADDXri $x8, 1, 0
+
+    RET undef $lr, implicit $x0
+...