[llvm] [RISCV] Add vmv.x.s to RISCVOptWInstrs. (PR #74519)

[Philip Reames via llvm-commits]

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@@ -368,6 +368,18 @@ static bool isSignExtendingOpW(const MachineInstr &MI,
     return MI.getOperand(1).getReg() == RISCV::X0;
   case RISCV::PseudoAtomicLoadNand32:
     return true;
+  case RISCV::PseudoVMV_X_S_MF8:
+  case RISCV::PseudoVMV_X_S_MF4:
+  case RISCV::PseudoVMV_X_S_MF2:
+  case RISCV::PseudoVMV_X_S_M1:
+  case RISCV::PseudoVMV_X_S_M2:
+  case RISCV::PseudoVMV_X_S_M4:
+  case RISCV::PseudoVMV_X_S_M8: {
+    // vmv.x.s returns a sign extended value if log2(sew) <= 5.
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preames wrote:

I found this very confusing at first.

The relevant wording is "If SEW < XLEN, the value is sign-extended to XLEN bits."  It's given the fact that XLEN must be 64 here, your code is correct, but maybe reword slightly?  

https://github.com/llvm/llvm-project/pull/74519