[llvm] [RISCV][GISel] Instruction select for vector G_ADD, G_SUB (PR #74114)

[Craig Topper via llvm-commits]

================
@@ -240,6 +254,10 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       &RISCV::ValueMappings[GPRSize == 64 ? RISCV::GPRB64Idx
                                           : RISCV::GPRB32Idx];
 
+  unsigned VRBSize = getMaximumSize(RISCV::VRBRegBankID);
+  const ValueMapping *VRBValueMapping =
+      &RISCV::ValueMappings[VRBSize == 64 ? RISCV::VRB64Idx : RISCV::VRB32Idx];
----------------
topperc wrote:

`getMaximumSize(RISCV::VRBRegBankID)` will always return the same value. I don't know what that value is. It's probably 512?

PartialMappingIdx should be
```
enum PartialMappingIdx {                                                         
  PMI_GPRB32 = 0,
  PMI_GPRB64 = 1,
  PMI_FPRB32 = 2,
  PMI_FPRB64 = 3,
  PMI_VRB64 = 4,
  PMI_VRB128 = 5,
  PMI_VRB256 = 6,
  PMI_VRB512 = 7,
};
```

PartMappings should be 
```
const RegisterBankInfo::PartialMapping PartMappings[] = {                        
    {0, 32, GPRBRegBank},
    {0, 64, GPRBRegBank},
    {0, 32, FPRBRegBank},
    {0, 64, FPRBRegBank},
    {0, 64, VRBRegBank},
    {0, 128, VRBRegBank},
    {0, 256, VRBRegBank},
    {0, 512, VRBRegBank},
};
```

ValueMappings should be
```
const RegisterBankInfo::ValueMapping ValueMappings[] = {                         
    // Invalid value mapping.                                                    
    {nullptr, 0},
    // Maximum 3 GPR operands; 32 bit.
    {&PartMappings[PMI_GPRB32], 1},
    {&PartMappings[PMI_GPRB32], 1},
    {&PartMappings[PMI_GPRB32], 1},
    // Maximum 3 GPR operands; 64 bit.
    {&PartMappings[PMI_GPRB64], 1},
    {&PartMappings[PMI_GPRB64], 1},
    {&PartMappings[PMI_GPRB64], 1},
    // Maximum 3 FPR operands; 32 bit.
    {&PartMappings[PMI_FPRB32], 1},
    {&PartMappings[PMI_FPRB32], 1},
    {&PartMappings[PMI_FPRB32], 1},
    // Maximum 3 FPR operands; 64 bit.
    {&PartMappings[PMI_FPRB64], 1},
    {&PartMappings[PMI_FPRB64], 1},
    {&PartMappings[PMI_FPRB64], 1},
    // Maximum 3 VR LMUL=1 operands;
    {&PartMappings[PMI_VRB64], 1},
    {&PartMappings[PMI_VRB64], 1},
    {&PartMappings[PMI_VRB64], 1},
    // Maximum 3 VR LMUL=2 operands;
    {&PartMappings[PMI_VRB128], 1},
    {&PartMappings[PMI_VRB128], 1},
    {&PartMappings[PMI_VRB128], 1},
    // Maximum 3 VR LMUL=4 operands;
    {&PartMappings[PMI_VRB256], 1},
    {&PartMappings[PMI_VRB256], 1},
    {&PartMappings[PMI_VRB256], 1},
    // Maximum 3 VR LMUL=8 operands;
    {&PartMappings[PMI_VRB512], 1},
    {&PartMappings[PMI_VRB512], 1},
    {&PartMappings[PMI_VRB512], 1},
};
```

ValueMappingIdx should be
```
enum ValueMappingIdx {
  InvalidIdx = 0,
  GPRB32Idx = 1,
  GPRB64Idx = 4,
  FPRB32Idx = 7,
  FPRB64Idx = 10,
  VPRB64Idx = 13,
  VPRB128Idx = 16,
  VPRB256Idx = 19,
  VPRB512Idx = 22,
};
```

You'll need a function like `getFPValueMapping` to pick the correct VRB*Idx from the minimum type size. If the size is <=64 pick VPRB64Idx, if the size is 128 pick VPRB128Idx, if the size is 256 pick VPRB256Idx, and if the size is 512 VPRB512Idx.

https://github.com/llvm/llvm-project/pull/74114