[llvm] [RISCV][GISel] Instruction select for vector G_ADD, G_SUB (PR #74114)

[Craig Topper via llvm-commits]

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@@ -240,6 +254,10 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       &RISCV::ValueMappings[GPRSize == 64 ? RISCV::GPRB64Idx
                                           : RISCV::GPRB32Idx];
 
+  unsigned VRBSize = getMaximumSize(RISCV::VRBRegBankID);
+  const ValueMapping *VRBValueMapping =
+      &RISCV::ValueMappings[VRBSize == 64 ? RISCV::VRB64Idx : RISCV::VRB32Idx];
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topperc wrote:

512 is the size of LMUL=8. we should have 4 different sizes in the mapping for the 4 different whole LMUL register sizes. We should pick based on the known minimum size of the type. 512, 256, 128, and 64. Anything less than 64 should use the 64.

https://github.com/llvm/llvm-project/pull/74114