[llvm] f866fde - [RISCV][GISel] Lower G_FCONSTANT to constant pool load without F or D. (#73034)
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Fri Dec 1 10:24:34 PST 2023
Author: Craig Topper
Date: 2023-12-01T10:24:26-08:00
New Revision: f866fde59854fd12dcc067388e4a60b218a0f818
URL: https://github.com/llvm/llvm-project/commit/f866fde59854fd12dcc067388e4a60b218a0f818
DIFF: https://github.com/llvm/llvm-project/commit/f866fde59854fd12dcc067388e4a60b218a0f818.diff
LOG: [RISCV][GISel] Lower G_FCONSTANT to constant pool load without F or D. (#73034)
I used an IR test because it was easier than constructing different MIR
test for each type of addressing.
Added:
llvm/test/CodeGen/RISCV/GlobalISel/constantpool.ll
Modified:
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index c926a380a273965..140dd58fdc5b9ca 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -540,6 +540,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
GV->hasExternalWeakLinkage());
}
case TargetOpcode::G_JUMP_TABLE:
+ case TargetOpcode::G_CONSTANT_POOL:
return selectAddr(MI, MIB, MRI);
case TargetOpcode::G_BRCOND: {
Register LHS, RHS;
@@ -875,7 +876,8 @@ bool RISCVInstructionSelector::selectAddr(MachineInstr &MI,
bool IsLocal,
bool IsExternWeak) const {
assert((MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
- MI.getOpcode() == TargetOpcode::G_JUMP_TABLE) &&
+ MI.getOpcode() == TargetOpcode::G_JUMP_TABLE ||
+ MI.getOpcode() == TargetOpcode::G_CONSTANT_POOL) &&
"Unexpected opcode");
const MachineOperand &DispMO = MI.getOperand(1);
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 153bac34986ec1c..97222ce452d8cf1 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -195,7 +195,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.widenScalarToNextPow2(0)
.clampScalar(0, sXLen, sXLen);
- getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE}).legalFor({p0});
+ getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE, G_CONSTANT_POOL})
+ .legalFor({p0});
if (ST.hasStdExtM() || ST.hasStdExtZmmul()) {
getActionDefinitionsBuilder(G_MUL)
@@ -283,7 +284,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
getActionDefinitionsBuilder(G_IS_FPCLASS)
.customIf(all(typeIs(0, s1), typeIsScalarFPArith(1, ST)));
- getActionDefinitionsBuilder(G_FCONSTANT).legalIf(typeIsScalarFPArith(0, ST));
+ getActionDefinitionsBuilder(G_FCONSTANT)
+ .legalIf(typeIsScalarFPArith(0, ST))
+ .lowerFor({s32, s64});
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
.legalIf(all(typeInSet(0, {s32, sXLen}), typeIsScalarFPArith(1, ST)))
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/constantpool.ll b/llvm/test/CodeGen/RISCV/GlobalISel/constantpool.ll
new file mode 100644
index 000000000000000..1eeeb60c2eb4051
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/constantpool.ll
@@ -0,0 +1,122 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=riscv32 -global-isel -code-model=small \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV32-SMALL
+; RUN: llc < %s -mtriple=riscv32 -global-isel -code-model=medium \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV32-MEDIUM
+; RUN: llc < %s -mtriple=riscv32 -global-isel -relocation-model=pic \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV32-PIC
+; RUN: llc < %s -mtriple=riscv64 -global-isel -code-model=small \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV64-SMALL
+; RUN: llc < %s -mtriple=riscv64 -global-isel -code-model=medium \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV64-MEDIUM
+; RUN: llc < %s -mtriple=riscv64 -global-isel -relocation-model=pic \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV64-PIC
+
+define void @constpool_f32(ptr %p) {
+; RV32-SMALL-LABEL: constpool_f32:
+; RV32-SMALL: # %bb.0:
+; RV32-SMALL-NEXT: lui a1, %hi(.LCPI0_0)
+; RV32-SMALL-NEXT: lw a1, %lo(.LCPI0_0)(a1)
+; RV32-SMALL-NEXT: sw a1, 0(a0)
+; RV32-SMALL-NEXT: ret
+;
+; RV32-MEDIUM-LABEL: constpool_f32:
+; RV32-MEDIUM: # %bb.0:
+; RV32-MEDIUM-NEXT: .Lpcrel_hi0:
+; RV32-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
+; RV32-MEDIUM-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
+; RV32-MEDIUM-NEXT: sw a1, 0(a0)
+; RV32-MEDIUM-NEXT: ret
+;
+; RV32-PIC-LABEL: constpool_f32:
+; RV32-PIC: # %bb.0:
+; RV32-PIC-NEXT: .Lpcrel_hi0:
+; RV32-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
+; RV32-PIC-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
+; RV32-PIC-NEXT: sw a1, 0(a0)
+; RV32-PIC-NEXT: ret
+;
+; RV64-SMALL-LABEL: constpool_f32:
+; RV64-SMALL: # %bb.0:
+; RV64-SMALL-NEXT: lui a1, %hi(.LCPI0_0)
+; RV64-SMALL-NEXT: lw a1, %lo(.LCPI0_0)(a1)
+; RV64-SMALL-NEXT: sw a1, 0(a0)
+; RV64-SMALL-NEXT: ret
+;
+; RV64-MEDIUM-LABEL: constpool_f32:
+; RV64-MEDIUM: # %bb.0:
+; RV64-MEDIUM-NEXT: .Lpcrel_hi0:
+; RV64-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
+; RV64-MEDIUM-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
+; RV64-MEDIUM-NEXT: sw a1, 0(a0)
+; RV64-MEDIUM-NEXT: ret
+;
+; RV64-PIC-LABEL: constpool_f32:
+; RV64-PIC: # %bb.0:
+; RV64-PIC-NEXT: .Lpcrel_hi0:
+; RV64-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
+; RV64-PIC-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
+; RV64-PIC-NEXT: sw a1, 0(a0)
+; RV64-PIC-NEXT: ret
+ store float 1.0, ptr %p
+ ret void
+}
+
+define void @constpool_f64(ptr %p) {
+; RV32-SMALL-LABEL: constpool_f64:
+; RV32-SMALL: # %bb.0:
+; RV32-SMALL-NEXT: lui a1, %hi(.LCPI1_0)
+; RV32-SMALL-NEXT: addi a1, a1, %lo(.LCPI1_0)
+; RV32-SMALL-NEXT: lw a2, 0(a1)
+; RV32-SMALL-NEXT: lw a1, 4(a1)
+; RV32-SMALL-NEXT: sw a2, 0(a0)
+; RV32-SMALL-NEXT: sw a1, 4(a0)
+; RV32-SMALL-NEXT: ret
+;
+; RV32-MEDIUM-LABEL: constpool_f64:
+; RV32-MEDIUM: # %bb.0:
+; RV32-MEDIUM-NEXT: .Lpcrel_hi1:
+; RV32-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
+; RV32-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
+; RV32-MEDIUM-NEXT: lw a2, 0(a1)
+; RV32-MEDIUM-NEXT: lw a1, 4(a1)
+; RV32-MEDIUM-NEXT: sw a2, 0(a0)
+; RV32-MEDIUM-NEXT: sw a1, 4(a0)
+; RV32-MEDIUM-NEXT: ret
+;
+; RV32-PIC-LABEL: constpool_f64:
+; RV32-PIC: # %bb.0:
+; RV32-PIC-NEXT: .Lpcrel_hi1:
+; RV32-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
+; RV32-PIC-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
+; RV32-PIC-NEXT: lw a2, 0(a1)
+; RV32-PIC-NEXT: lw a1, 4(a1)
+; RV32-PIC-NEXT: sw a2, 0(a0)
+; RV32-PIC-NEXT: sw a1, 4(a0)
+; RV32-PIC-NEXT: ret
+;
+; RV64-SMALL-LABEL: constpool_f64:
+; RV64-SMALL: # %bb.0:
+; RV64-SMALL-NEXT: lui a1, %hi(.LCPI1_0)
+; RV64-SMALL-NEXT: ld a1, %lo(.LCPI1_0)(a1)
+; RV64-SMALL-NEXT: sd a1, 0(a0)
+; RV64-SMALL-NEXT: ret
+;
+; RV64-MEDIUM-LABEL: constpool_f64:
+; RV64-MEDIUM: # %bb.0:
+; RV64-MEDIUM-NEXT: .Lpcrel_hi1:
+; RV64-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
+; RV64-MEDIUM-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
+; RV64-MEDIUM-NEXT: sd a1, 0(a0)
+; RV64-MEDIUM-NEXT: ret
+;
+; RV64-PIC-LABEL: constpool_f64:
+; RV64-PIC: # %bb.0:
+; RV64-PIC-NEXT: .Lpcrel_hi1:
+; RV64-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
+; RV64-PIC-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
+; RV64-PIC-NEXT: sd a1, 0(a0)
+; RV64-PIC-NEXT: ret
+ store double 1.0, ptr %p
+ ret void
+}
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