[llvm] [AMDGPU][True16] Support V_CEIL_F16. (PR #73108)

[Ivan Kosarev via llvm-commits]

================
@@ -2303,7 +2303,17 @@ bool AMDGPUOperand::isInlineValue() const {
 // AsmParser
 //===----------------------------------------------------------------------===//
 
-static int getRegClass(RegisterKind Is, unsigned RegWidth) {
+static int getRegClass(RegisterKind Is, unsigned RegWidth,
+                       RegisterSuffix Suffix) {
+  if (Suffix != RegisterSuffix::None) {
+    if (Is == IS_VGPR && RegWidth == 16) {
+      if (Suffix == RegisterSuffix::Lo)
+        return AMDGPU::VGPR_LO16RegClassID;
----------------
kosarev wrote:

> I think using VGPR_16 right now would be less complicated. Why use two separate register classes when one will do?

It can be seen downstream that using VGPR_16 involves special-casing that is not needed if we just follow the existing design. Looks neither simpler, nor clearer, nor more reliable to me:
```
  const MCRegisterInfo *TRI = getContext().getRegisterInfo();
  const MCRegisterClass RC = TRI->getRegClass(RCID);
  if (RCID == VGPR_16RegClassID || RCID == VGPR_16_Lo128RegClassID)
    // RegIdx depends on register class definition in SIRegisterInfo.td
    // Expected register order is alternating lo and hi :
    // VGPR0_LO16, VGPR0_HI16, VGPR1_LO16, VGPR1_HI16, ...
    RegIdx = RegIdx * 2 + (unsigned)IsHigh;
  if (RegIdx >= RC.getNumRegs()) {
```

https://github.com/llvm/llvm-project/pull/73108