[llvm] [AArch64] merge index address with large offset into base address (PR #72187)

[David Green via llvm-commits]

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@@ -15977,6 +15977,18 @@ bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
                                                           AM.Scale);
 }
 
+// Check whether the 2 offsets belong to the same imm24 range, and their high
+// 12bits are same.
+int64_t AArch64TargetLowering::getPreferBaseOffset(int64_t MinOffset,
+                                                   int64_t MaxOffset) const {
+  if (MinOffset >> 12 == MaxOffset >> 12 && MinOffset >> 24 == 0) {
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davemgreen wrote:

I think this is assuming a uimm12s1 addressing mode for the load/store? Should it be more precise about the type being used, and maybe make use of isLegalAddressingMode if it can?

https://github.com/llvm/llvm-project/pull/72187