[llvm] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #66915)

[Paul Kirth via llvm-commits]

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@@ -3107,6 +3136,41 @@ void RISCVAsmParser::emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc,
                     RISCV::ADDI, IDLoc, Out);
 }
 
+void RISCVAsmParser::emitLoadTLSDescAddress(MCInst &Inst, SMLoc IDLoc,
+                                            MCStreamer &Out) {
+  // The load TLS GD address pseudo-instruction "la.tlsdesc" is used in
+  // global-dynamic TLS model addressing of global symbols:
+  //   la.tlsdesc rdest, symbol
+  // expands to
+  //   TmpLabel: AUIPC rdest, %tlsdesc_hi(symbol)
+  //             ADDI rdest, rdest, %pcrel_lo(TmpLabel)
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ilovepi wrote:

So, AArch64 has the pseudo `TLSDESC_CALLSEQ`, and nothing in the AsmParser. They do have a translation in the AsmPrinter though, which I don't think is functionally different than the pseudo expansion. 

Do yo think its appropriate to omit the AsmParser bits here, since I don't expect for us to ever emit `la.tlsdesc` instructions? Otherwise, I'm not super sure how to adapt this, since its unclear to me how to write the code sequence, labels, and relocations in RISCVISelLowering. 

https://github.com/llvm/llvm-project/pull/66915