[llvm] AMDGPU/GlobalISel: Uniformity info based regbankselect (PR #73684)

Pierre van Houtryve via llvm-commits llvm-commits at lists.llvm.org
Wed Nov 29 01:15:53 PST 2023


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@@ -68,7 +71,24 @@ bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) {
   MachineUniformityInfo Uniformity =
       computeMachineUniformityInfo(MF, CycleInfo, DomTree.getBase(),
                                    !ST.isSingleLaneExecution(F));
-  (void)Uniformity; // TODO: Use this
+
+  for (MachineBasicBlock &MBB : MF) {
+    for (MachineInstr &MI : MBB) {
+      switch (MI.getOpcode()) {
+      case AMDGPU::G_FADD: {
+        Register Dst = MI.getOperand(0).getReg();
+        if (Uniformity.isUniform(Dst)) {
+          MRI->setRegBank(Dst, RBI->getRegBank(AMDGPU::SGPRRegBankID));
+        } else {
+          MRI->setRegBank(Dst, RBI->getRegBank(AMDGPU::VGPRRegBankID));
+        }
----------------
Pierre-vh wrote:

`{}` isn't needed

Also if this is going to be expanded for many opcodes, might be worth putting `RBI->getRegBank(AMDGPU::SGPRRegBankID)` and the VGPR one into variables to slightly reduce verbosity 

https://github.com/llvm/llvm-project/pull/73684


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