[llvm] [AArch64] merge index address with large offset into base address (PR #72187)

[via llvm-commits]

vfdff wrote:

hi @davemgreen 
  * I checked the `DAG combine` is placed before the `AArch64DAGToDAGISel`, and it doesn't hold the `machine IR`）, so it only uses a register `t4` to specify the destination address.
```
t4: i64 = add nuw t2, Constant:i64<1039992>
    t12: i32,ch = load<(load (s8) from %ir.arrayidx, !tbaa !6), zext from i8> t0, t4, undef:i64
```
* When I split the const offset into 2 immediate numbers, then it will merge back in `DAGCombiner::visitADD`.
```
t15: i64 = add t2, Constant:i64<1036288>
      t17: i64 = add t15, Constant:i64<3704>
    t18: i32,ch = load<(load (s8) from %ir.arrayidx, !tbaa !6), zext from i8> t0, t17, undef:i64
```
* then I try to stop above the back merging in `DAGCombiner::visitADD->..->FoldConstantArithmetic`, it still can't reuse the
  add instruction,  i.e: it has **same** output to the method done in  `AArch64DAGToDAGISel`.
  test with multiple offsets in one case : https://gcc.godbolt.org/z/dE8dETcvK
  ```
	add	x8, x0, #1015, lsl #12          // =4157440
	add	x9, x0, #1015, lsl #12          // =4157440
	add	x8, x8, #2528
	ldr	w9, [x9, #2528]
	ldr	w8, [x8, #8]
	add	w0, w8, w9
  ```

 so need adaptation support in **CodeGenPrepare::optimizeMemoryInst** ?
   

https://github.com/llvm/llvm-project/pull/72187