[llvm] [GISEL][RISCV] Add G_VACOPY GISEL opcode and add lowering code for it. (PR #73066)

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git-clang-format --diff 331111277a3e80aedd1a6877524feadfbcb41a88 e4065d0e309b769b2659b36516394111c53d9951 -- llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp llvm/lib/Target/RISCV/GISel/RISCVCallLowering.h llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
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diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 1808686bd1..4e190a7c34 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -78,7 +78,7 @@ private:
   bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB,
                        MachineRegisterInfo &MRI) const;
   bool selectMergeValues(MachineInstr &MI, MachineIRBuilder &MIB,
-                           MachineRegisterInfo &MRI) const;
+                         MachineRegisterInfo &MRI) const;
   bool selectUnmergeValues(MachineInstr &MI, MachineIRBuilder &MIB,
                            MachineRegisterInfo &MRI) const;
 
@@ -613,8 +613,7 @@ bool RISCVInstructionSelector::selectUnmergeValues(
   Register Src = MI.getOperand(2).getReg();
   Register Lo = MI.getOperand(0).getReg();
   Register Hi = MI.getOperand(1).getReg();
-  if (!isRegInFprb(Src, MRI) ||
-      !(isRegInGprb(Lo, MRI) && isRegInGprb(Hi, MRI)))
+  if (!isRegInFprb(Src, MRI) || !(isRegInGprb(Lo, MRI) && isRegInGprb(Hi, MRI)))
     return false;
   MachineInstr *Result = MIB.buildInstr(RISCV::SplitF64Pseudo, {Lo, Hi}, {Src});
 
@@ -706,12 +705,12 @@ const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank(
 }
 
 bool RISCVInstructionSelector::isRegInGprb(Register Reg,
-                                          MachineRegisterInfo &MRI) const {
+                                           MachineRegisterInfo &MRI) const {
   return RBI.getRegBank(Reg, MRI, TRI)->getID() == RISCV::GPRBRegBankID;
 }
 
 bool RISCVInstructionSelector::isRegInFprb(Register Reg,
-                                          MachineRegisterInfo &MRI) const {
+                                           MachineRegisterInfo &MRI) const {
   return RBI.getRegBank(Reg, MRI, TRI)->getID() == RISCV::FPRBRegBankID;
 }
 

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https://github.com/llvm/llvm-project/pull/73066