[llvm] c9fd76f - [RISCV] Replace XLenVT in RV64 only pattern with i64. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-21T11:22:08-08:00
New Revision: c9fd76f45f5a6ace7c87ce6fdc6efe455fd39e95

URL: https://github.com/llvm/llvm-project/commit/c9fd76f45f5a6ace7c87ce6fdc6efe455fd39e95
DIFF: https://github.com/llvm/llvm-project/commit/c9fd76f45f5a6ace7c87ce6fdc6efe455fd39e95.diff

LOG: [RISCV] Replace XLenVT in RV64 only pattern with i64. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 0f1d1d4cb23cee3..7e54c83ce4e2a8e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2013,7 +2013,7 @@ def : Pat<(XLenVT (abs GPR:$rs1)),
 let Predicates = [HasShortForwardBranchOpt, IsRV64] in
 def : Pat<(sext_inreg (abs 33signbits_node:$rs1), i32),
           (PseudoCCSUBW (i64 GPR:$rs1), (i64 X0), /* COND_LT */ 2,
-           (XLenVT GPR:$rs1), (i64 X0), (i64 GPR:$rs1))>;
+           (i64 GPR:$rs1), (i64 X0), (i64 GPR:$rs1))>;
 
 //===----------------------------------------------------------------------===//
 // Experimental RV64 i32 legalization patterns.